Memory and detection method

Abstract

The embodiment of the application discloses a memory and a detection method, and belongs to the technical field of storage. The memory comprises a storage array chip and a CMOS chip. The storage array chip comprises a first dielectric layer and a first electrode plate, the first electrode plate is located in the first dielectric layer, the CMOS chip comprises a second dielectric layer and a second electrode plate, and the second electrode plate is located in the second dielectric layer. The first dielectric layer and the second dielectric layer are bonded, and the first electrode plate and the second electrode plate form a capacitor at a bonding interface. Through the capacitor formed by the first electrode plate and the second electrode plate at the bonding interface, potential defects of the bonding interface can be detected.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory and a detection method. Background Technology

[0002] Currently, in the fabrication of 3D memory, chips with memory arrays (i.e., memory array chips) and chips with peripheral circuits (i.e., CMOS (complementary metal oxide semiconductor) chips) are typically bonded together to obtain a 3D memory with stacked memory arrays and peripheral circuits. If there are quality issues at the bonding interface after bonding different chips, it will affect the performance of the 3D memory. Therefore, after bonding different chips, it is necessary to perform quality inspection on the bonding interface.

[0003] In related technologies, a portion of the test circuitry is configured in the memory array chip, and another portion is configured in the CMOS chip. After the two chips are bonded, these two portions of the test circuitry are also connected, thus forming a conductive path intersecting the bonding interface. Then, different voltages are applied across this conductive path. If current flows through the conductive path, it indicates that there is no quality problem with the bonding interface; if no current flows through the conductive path, it indicates that there is a quality problem with the bonding interface.

[0004] The above detection methods can only detect existing quality problems at the bonding interface, and cannot detect potential quality problems induced by extreme external environmental conditions. Summary of the Invention

[0005] This application provides a memory and a detection method that can detect potential defects in bonding interfaces. The technical solution is as follows:

[0006] On one hand, a memory is provided, the memory including a memory array chip 10 and a complementary metal-oxide-semiconductor CMOS chip 20;

[0007] The storage array chip 10 includes a first dielectric layer 101 and a first electrode plate 102, wherein the first electrode plate 102 is located in the first dielectric layer 101;

[0008] The CMOS chip 20 includes a second dielectric layer 201 and a second electrode plate 202, wherein the second electrode plate 202 is located in the second dielectric layer 201;

[0009] The first dielectric layer 101 and the second dielectric layer 201 are bonded together, and the first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface.

[0010] Optionally, the first electrode plate 102 includes a first sub-electrode plate 1021 and a second sub-electrode plate 1022, and the second electrode plate 202 includes a third sub-electrode plate 2021 and a fourth sub-electrode plate 2022.

[0011] The first sub-electrode plate 1021 and the fourth sub-electrode plate 2022 are bonded together to form one electrode of the capacitor, and the second sub-electrode plate 1022 and the third sub-electrode plate 2021 are bonded together to form the other electrode of the capacitor.

[0012] Optionally, the number of the first sub-electrode plate 1021, the second sub-electrode plate 1022, the third sub-electrode plate 2021, and the fourth sub-electrode plate 2022 are all N, where N is greater than 1;

[0013] N first sub-electrode plates 1021 and N fourth sub-electrode plates 2022 are bonded one-to-one, and N second sub-electrode plates 1022 and N third sub-electrode plates 2021 are bonded one-to-one to form N capacitors at the bonding interface.

[0014] Optionally, the storage array chip 10 further includes a first conductive strip 103, which is located in the first dielectric layer 101. The first conductive strip 103 is connected to the end of the first sub-electrode plate 1021 away from the bonding interface, and the first conductive strip 103 is not connected to the end of the second sub-electrode plate 1022 away from the bonding interface.

[0015] The CMOS chip 20 further includes a second conductive strip 203, which is located in the second dielectric layer 201. The second conductive strip 203 is connected to the end of the third sub-electrode plate 2021 away from the bonding interface, and the second conductive strip 203 is not connected to the end of the fourth sub-electrode plate 2022 away from the bonding interface.

[0016] Optionally, the storage array chip 10 further includes a first connection line 104, which is connected to the first conductive strip 103;

[0017] The CMOS chip 20 further includes a second connection line 204, a first detection pin 205, and a second detection pin 206. The second connection line 204 is connected to the first detection pin 205 and is bonded to the first connection line 104. The second detection pin 206 is connected to the second conductive strip 203.

[0018] Optionally, the first electrode plate 102 and the second electrode plate 202 are located at opposite positions on both sides of the bonding interface, so as to serve as the two electrodes of the capacitor, respectively.

[0019] Optionally, the storage array chip 10 further includes a third connection line 105, which is connected to the first electrode plate 102;

[0020] The CMOS chip 20 further includes a fourth connection line 207, a third detection pin 208, and a fourth detection pin 209. The fourth connection line 207 is connected to the third detection pin 208, the fourth connection line 207 is bonded to the third connection line 105, and the fourth detection pin 209 is connected to the second electrode plate 202.

[0021] Optionally, the first dielectric layer 101 includes a first functional region portion 1011 and a first peripheral region portion 1012, the first peripheral region portion 1012 surrounding the first functional region portion 1011, and the first electrode plate 102 located in the first peripheral region portion 1012;

[0022] The second dielectric layer 201 includes a second functional region portion 2011 and a second peripheral region portion 2012, the second peripheral region portion 2012 surrounding the second functional region portion 2011, and the second electrode plate 202 located in the second peripheral region portion 2012.

[0023] On the other hand, a method for detecting a memory is provided, the memory being the memory provided in the above-mentioned aspect; the method includes:

[0024] Voltages are applied to the first electrode plate 102 and the second electrode plate 202 respectively;

[0025] Detect the current flow between the first electrode plate 102 and the second electrode plate 202;

[0026] When current is detected flowing between the first electrode plate 102 and the second electrode plate 202, it is determined that there is a potential defect in the bonding interface.

[0027] Optionally, the method further includes:

[0028] When no current is detected between the first electrode plate 102 and the second electrode plate 202, it is determined that there are no potential defects in the bonding interface.

[0029] Optionally, applying voltage to the first electrode plate 102 and the second electrode plate 202 respectively includes:

[0030] A first voltage and a second voltage are applied to the first electrode plate 102 and the second electrode plate 202 respectively, and the difference between the first voltage and the second voltage is the first voltage difference;

[0031] After applying the first voltage and the second voltage, a third voltage and a fourth voltage are applied to the first electrode plate 102 and the second electrode plate 202, respectively. The difference between the third voltage and the fourth voltage is the second voltage difference, which is less than the first voltage difference.

[0032] In this embodiment, a capacitor is formed by the first electrode plate 102 and the second electrode plate 202 at the bonding interface. Since the first electrode plate 102 is located in the first dielectric layer 101 and the second electrode plate 202 is located in the second dielectric layer 201, and the bonding interface is formed by bonding the first dielectric layer 101 and the second dielectric layer 201 together, there is at least a partial bonding interface between the two electrodes of the capacitor.

[0033] Therefore, if the bonding interface has excellent performance, even if a large voltage is applied to the two electrodes of the capacitor, the structure of the bonding interface will remain largely unchanged under a large electric field, and thus the large voltage will not cause the capacitor to break down. In this scenario, when the voltage is applied to the two electrodes of the capacitor again, no current will be detected between them because the two electrodes are currently in an open circuit state. However, if the bonding interface has poor performance, even if there are no defects at the bonding interface, applying a large voltage to the two electrodes may cause the structure of the bonding interface to change under a large electric field, leading to capacitor breakdown. In this scenario, if the capacitor breaks down, applying a voltage to the two electrodes again will result in a current being detected between them because the two electrodes are currently in a closed circuit state. Based on this, the capacitor formed by the first electrode plate 102 and the second electrode plate 202 at the bonding interface can detect potential defects in the bonding interface. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram illustrating the positional relationship between a wafer and a chip, provided in an embodiment of this application.

[0036] Figure 2 This is a schematic diagram of a bonding process provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the peripheral area and functional area of ​​a chip provided in an embodiment of this application;

[0038] Figure 4 This is a cross-sectional schematic diagram of a bonded memory array chip and a CMOS chip provided in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of a circuit under test provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of a first electrode plate and a second electrode plate provided in an embodiment of this application;

[0041] Figure 7 This is a schematic diagram of another first electrode plate and a second electrode plate provided in an embodiment of this application;

[0042] Figure 8 This is a schematic diagram of a first conductive strip and a second conductive strip provided in an embodiment of this application;

[0043] Figure 9 This is a schematic diagram of a first detection pin and a second detection pin provided in an embodiment of this application;

[0044] Figure 10 This is a schematic diagram showing the position of a first electrode plate according to an embodiment of this application;

[0045] Figure 11 This is a schematic diagram showing the position of a second electrode plate according to an embodiment of this application;

[0046] Figure 12 This is a schematic diagram of another first electrode plate and a second electrode plate provided in an embodiment of this application;

[0047] Figure 13 This is a schematic diagram of a third detection pin and a fourth detection pin provided in an embodiment of this application;

[0048] Figure 14 This is a schematic diagram showing the position of another first electrode plate provided in an embodiment of this application;

[0049] Figure 15 This is a schematic diagram showing the position of another second electrode plate provided in an embodiment of this application;

[0050] Figure 16 This is a flowchart of a memory detection method provided in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0052] Before providing a detailed explanation of the embodiments of this application, the application scenarios of the embodiments of this application will be explained first.

[0053] Currently, in the manufacturing process of 3D memory, a memory array wafer containing multiple memory array cells (dies) and a CMOS wafer containing multiple CMOS cells are usually prepared separately. Then, the memory array wafer and the CMOS wafer are bonded together as a whole, and then a high-performance 3D memory is obtained by slicing.

[0054] It should be noted that a memory array wafer includes multiple memory array chips, and a CMOS wafer includes multiple CMOS chips. During bonding, each memory array chip in the memory array wafer is bonded to one of the CMOS chips in the CMOS wafer.

[0055] Figure 1 This is a schematic diagram illustrating the positional relationship between a wafer and a chip, provided in an embodiment of this application. Figure 1 As shown, a memory array wafer contains multiple memory array chips 10, and a CMOS wafer contains multiple CMOS chips 20. During bonding, each memory array chip 10 and a CMOS chip 20 are bonded together. For example, in Figure 1 In the middle, a memory array chip 10 marked with a rhombus and a CMOS chip 20 marked with a rhombus are bonded together.

[0056] Figure 2 This is a schematic diagram of a bonding process provided in an embodiment of this application. Figure 2 As shown, the memory array chip 10 includes a first substrate and a memory array layer, in which a memory array is deployed. The CMOS chip 20 includes a second substrate and a peripheral circuit layer, in which peripheral circuits are deployed.

[0057] Bonding specifically refers to bonding the side of the memory array layer away from the first substrate to the side of the peripheral circuit layer away from the second substrate. For ease of explanation, as follows... Figure 2 As shown, the bonding interface is marked as SS.

[0058] Additionally, it should be noted that both the memory array chip 10 and the CMOS chip 20 include functional areas and peripheral areas. The functional area is used to deploy the core components of the chip; for example, the memory array chip's functional area houses the memory array, while the CMOS chip's functional area houses the peripheral circuitry of the memory. The peripheral area, like a Great Wall around the chip, surrounds the functional area from all sides. The peripheral area serves two purposes: firstly, it prevents damage to the internal circuitry of the functional area during dicing (chip cutting); secondly, it prevents external dust from entering the internal circuitry of the chip's functional area. Therefore, the peripheral area is also called a protected area.

[0059] Figure 3 This is a schematic diagram of the peripheral area and functional area of ​​a chip provided in an embodiment of this application. Figure 3 The chip shown can be either a memory array chip 10 or a CMOS chip 20. For example... Figure 3 As shown, the outer area surrounds the functional area. It should be noted that... Figure 3 To facilitate observation of the positional relationship between the peripheral and functional areas, the chip substrate is not... Figure 3 As shown in the image.

[0060] The structure of the bonded memory array chip and CMOS chip will be explained in detail below.

[0061] Figure 4 This is a cross-sectional schematic diagram of a bonded memory array chip and a CMOS chip provided in an embodiment of this application. Wherein, Figure 4 This can be understood as the functional areas of the bonded memory array chip and CMOS chip being aligned. Figure 3 The diagram shows the cross-section obtained after cutting off section CC'. The outer region is... Figure 4 It is not shown in the middle.

[0062] The bonded memory array chip and CMOS chip can be referred to as semiconductor devices, which may include any other suitable semiconductor devices with 2D, 2.5D or 3D architectures, such as logic devices, volatile memory devices (such as DRAM (dynamic random access memory) and SRAM (static random-access memory)) and non-volatile memory devices (such as flash memory).

[0063] like Figure 4 As shown, the semiconductor device includes a memory array chip 10 and a CMOS chip 20.

[0064] Figure 4 The diagram illustrates the directions of the x and y axes to further explain the spatial relationships between the components of a semiconductor device. For example... Figure 4 As shown, the CMOS chip 20 includes a substrate 210, which includes two lateral surfaces (e.g., a top surface and a bottom surface, the top and bottom surfaces being determined based on their relative positional relationship in the y-axis direction) extending laterally in the x-direction (i.e., the lateral direction). Figure 4 As shown, the bottom surface of substrate 210 is located in the lowest plane of the semiconductor device in the y-direction (i.e., the vertical direction). Whether one component (or layer) in the semiconductor device is located "above," "above," or "below" another component (or layer) is determined based on the relative positional relationship of the two components in the y-direction. The description of spatial relationships involved in the embodiments of this application can be referred to this explanation.

[0065] Based on the above description of positional relationships, it can be seen that, Figure 4 As shown, the memory array chip 10 is positioned above the CMOS chip 20. It is understandable that, although in Figure 4 The memory array chip 10 is positioned above the CMOS chip 20, but in some embodiments, their relative positions can be reversed. For example, in another semiconductor device, the memory array chip 10 may be positioned below the CMOS chip 20.

[0066] like Figure 4 As shown, the memory array chip 10 and the CMOS chip are bonded face-to-face at the bonding interface SS. The bonding interface SS is the location where the memory array chip 10 and the CMOS chip 20 are bonded. In some embodiments, the bonding interface SS may be a layer of a certain thickness, which includes the bottom surface of the memory array chip 10 and the top surface of the CMOS chip 20.

[0067] In some embodiments, the bonding interface SS can be disposed between the memory array chip 10 and the CMOS chip 20 by hybrid bonding (also known as "metal / dielectric hybrid bonding"). Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (such as solder or adhesive)). Hybrid bonding technique can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding.

[0068] also, Figure 4 An example of a substrate 210 for a CMOS chip 20 is shown. The substrate 210 of the CMOS chip 20 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI (silicon-on-insulator), or any other suitable material.

[0069] The internal structures of the memory array chip 10 and the CMOS chip 20 will be explained in detail below. Because... Figure 4The memory array chip 10 is located above the CMOS chip 20. To facilitate understanding, the detailed structure of the CMOS chip 20 will be explained first.

[0070] like Figure 4 As shown, the CMOS chip 20 includes a peripheral device layer 220 on a substrate 210. The peripheral device layer 220 may include peripheral devices (e.g., a plurality of transistors 221) formed on the substrate 210. Each transistor 211 is wholly or partially formed in the substrate 210 (e.g., below the top surface of the substrate 210) and / or directly on the substrate 210. Isolation regions (e.g., STI (shallow trench isolation) may also be present. Figure 4 (not shown) and doped regions (such as the source and drain regions of transistor 221, Figure 4 (Not shown) can be formed in substrate 210.

[0071] In some embodiments, the peripheral devices of peripheral device layer 220 may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating the operation of the semiconductor device. For example, the peripheral devices of peripheral device layer 220 may include one or more of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). In some embodiments, the peripheral devices of peripheral device layer 220 are formed on substrate 210 using CMOS (complementary metal oxide semiconductor) technology, and are therefore referred to as a CMOS chip.

[0072] The CMOS chip 20 may also include a peripheral interconnect layer 230 (also referred to as an "interconnect layer") above the peripheral device layer 220, which is used to transmit electrical signals to and from the peripheral device layer 220. The peripheral interconnect layer 230 may include a plurality of interconnects 231 (also referred to as "contacts" in this embodiment), which typically include lateral interconnects and vertical interconnect access (via) contacts.

[0073] It should be noted that the term "interconnect" can broadly include any suitable type of interconnect. For example, MEOL (middle end of line) interconnects and BEOL (back end of line) interconnects. As described in detail below, interconnects 231 in peripheral interconnect layer 230 may include functional interconnects electrically connected to peripheral devices. Optionally, it may also include dummy interconnects that are not electrically connected to any peripheral device in peripheral device layer 220. Peripheral interconnect layer 230 may also include one or more ILD (inter-level dielectric) layers (also referred to as "IMD (inter-metal dielectric) layers"), wherein interconnect lines and via contacts are formed in one or more ILD layers. That is, peripheral interconnect layer 230 includes interconnects 231 in multiple ILD layers.

[0074] The interconnects 231 in the peripheral interconnect layer 230 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer in the peripheral interconnect layer 230 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectrics, or any combination thereof.

[0075] In addition, such as Figure 4 As shown, the CMOS chip 20 may further include a bonding layer 240 at the bonding interface SS and above the peripheral interconnect layer 230 and the peripheral device layer 220. The bonding layer 240 may include a plurality of bonding contacts 241 and a dielectric 242 for electrically isolating the bonding contacts 241.

[0076] The bonding contacts 241 may include functional bonding contacts, each of which is part of the electrical connection between the CMOS chip 20 and the memory array chip 10. The bonding contacts 241 may also include dummy bonding contacts, each of which is not part of any electrical connection between the CMOS chip 20 and the memory array chip 10. The dummy bonding contacts can be used to increase the local density of the bonding contacts 241 at the bonding interface SS, thereby increasing the bonding strength.

[0077] The bonding contacts 241 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of ​​the bonding layer 240 may be formed of a dielectric 242, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 241 and dielectric 242 in the bonding layer 240 are used for hybrid bonding.

[0078] like Figure 4 As shown, the memory array chip 10 includes a memory array device layer 110, which includes arrayed memory strings 111 and alternately stacked conductor and dielectric layers, also referred to herein as a “memory stack layer” 112. Each memory string 111 extends vertically above the peripheral device layer 220 and extends vertically through the memory array device layer 110.

[0079] Figure 4 The storage string 111 in the example can be a NAND storage string.

[0080] Each memory string 111 may include a semiconductor channel and a dielectric layer (also referred to as a "memory film"). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite layer including a tunneling layer, a memory layer (also referred to as a "charge trapping / storage layer"), and a barrier layer (not shown). Each memory string 111 may have a cylindrical shape (e.g., a column). In this case, the semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially from the center of the column outwards. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof.

[0081] In some embodiments, memory string 111 further includes a plurality of control gates (each control gate being part of a word line). Each conductor layer in memory stack layer 112 can be used as a control gate for a memory cell in each memory string 111.

[0082] In some embodiments, the memory array chip 10 further includes a gate GLS 113 extending vertically through the memory stack layer 112. The GLS 1133 can be used to form conductor / dielectric layer pairs in the memory stack layer 112 through a gate replacement process and can be filled with conductive material for electrically connecting the array common source (ACS).

[0083] In some embodiments, the memory array chip 10 further includes a semiconductor layer 120 disposed above and in contact with the memory string 111. The memory array device layer 110 is disposed below the semiconductor layer 120. In some embodiments, the semiconductor layer 120 includes a plurality of semiconductor plugs electrically isolated by isolation regions. In some embodiments, each semiconductor plug is disposed at the upper end of a corresponding memory string 111 and serves as the drain of the corresponding memory string 111, and can therefore be considered as part of the corresponding memory string 111. The semiconductor plugs may comprise monocrystalline silicon. The semiconductor plugs may be undoped, partially doped (in the thickness and / or width directions) by p-type or n-type dopants, or fully doped.

[0084] In some embodiments, the memory array chip 10 includes local interconnects formed in one or more ILD layers and in contact with components such as word lines and memory strings 111 in the memory array device layer 110. Figure 4 (Not shown). Local interconnects may include word line via contacts, source line via contacts, and bit line via contacts. Each local interconnect may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Word line via contacts may extend vertically through one or more ILD layers. Each word line via contact may contact a corresponding semiconductor layer 120 to individually address a corresponding word line of a bonded semiconductor device. Each source line via contact may contact the source of a corresponding memory string 111. Bit line via contacts may extend vertically through one or more ILD layers. Each bit line via contact may be electrically connected to a corresponding semiconductor plug (e.g., drain) of the memory string 111 to individually address the corresponding memory string 111.

[0085] In some embodiments, another interconnect layer (referred to herein as the "BEOL interconnect layer") is used. Figure 4 An interconnect layer (not shown) may be disposed above the memory array device layer 110. This interconnect layer may include interconnects, such as interconnect lines and via contacts deployed in one or more ILD layers. The BEOL interconnect layer may also include contact pads and a redistribution layer (not shown) at the top of the bonded semiconductor device for wire bonding and / or bonding with intercalators. The BEOL interconnect layer and the array interconnect layer may be formed on opposite sides of the memory array device layer 110. In some embodiments, the interconnect lines, via contacts, and contact pads in the BEOL interconnect layer may transmit electrical signals between the semiconductor device and external circuitry.

[0086] Similar to the CMOS chip 20, the memory array chip 10 may also include an interconnect layer for transmitting electrical signals to and from the memory string 111. For example... Figure 4As shown, the memory array chip 10 may include an interconnect layer 130 (referred to herein as the "array interconnect layer") below the memory array device layer 110. The array interconnect layer 130 may include a plurality of interconnects 131, which may be interconnect lines and via contacts deployed in one or more ILD layers. As described in detail below, the interconnects 131 in the array interconnect layer 130 may include functional interconnects electrically connected to memory strings 111, and optionally, may also include dummy interconnects not electrically connected to any memory strings 111 in the memory array device layer 110.

[0087] like Figure 4 As shown, the memory array chip 10 may further include a bonding layer 140 at the bonding interface SS and below the array interconnect layer 130 and the memory array device layer 110. The bonding layer 140 may include a plurality of bonding contacts 141 and a dielectric 142 for electrically isolating bonding contacts 141.

[0088] The bonding contact 141 may include functional bonding contacts, each of which is part of an electrical connection between the CMOS chip 20 and the memory array chip 10. The bonding contact 141 may also include dummy bonding contacts, each of which is not part of any electrical connection between the CMOS chip 20 and the memory array chip 10. Dummy bonding contacts can be used to increase the local density of the bonding contacts 141 at the bonding interface SS to increase the bonding strength.

[0089] The bonding contacts 141 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of ​​the bonding layer 140 may be formed with a dielectric 142, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 141 and dielectric 142 in the bonding layer 140 may be used for hybrid bonding.

[0090] like Figure 4 As shown, a bonding interface SS can be formed between bonding layers 140 and 240. According to some embodiments, bonding contact 241 contacts bonding contact 141 at bonding interface SS, and dielectric 242 contacts dielectric 142.

[0091] Specifically, a pair of functional bonding contacts are in contact with each other at the bonding interface SS, and the pair of functional bonding contacts are in contact with a pair of interconnects 231 and 131 on opposite sides of the bonding interface SS, respectively.

[0092] Furthermore, a pair of dummy bonding contacts also contact each other at the bonding interface SS. As dummy bonding contacts used to improve the metal density and uniformity at the bonding interface SS for hybrid bonding, the pair of dummy bonding contacts are separated from the functional interconnects on at least one side of the bonding interface SS (e.g., in the peripheral interconnect layer 230 and / or the array interconnect layer 130) to avoid forming an electrical connection between the memory array chip 10 and the CMOS chip 20.

[0093] Furthermore, the peripheral interconnect layer 230 and the array interconnect layer 130 include a pair of dummy interconnects that are not electrically connected to the memory string 111 and the transistor 221, and a pair of dummy bonding contacts that can contact the pair of dummy interconnects on opposite sides of the bonding interface SS, without forming an electrical connection between the memory array chip 10 and the CMOS chip 20. Additionally, dielectrics 242 and 142 also contact each other at the bonding interface SS.

[0094] It should be noted that, Figure 4 The embodiments shown are optional structures of the bonded memory array chip and CMOS chip involved in the examples of this application. The embodiments of this application do not limit the internal structure of the bonded memory array chip and CMOS chip.

[0095] like Figure 4 As shown, the memory array chip 10 and the CMOS chip 20 are bonded at the bonding interface SS. If there are defects at the bonding interface SS, it can easily lead to… Figure 4 The electrical connection between the bonding contact 141 and the bonding contact 241 in the memory array chip 10 is faulty, which causes the electrical connection between the memory array chip 10 and the CMOS chip 20 to fail, thereby affecting the CMOS chip 20 to perform read, write and erase operations on the memory array chip 10.

[0096] Therefore, after the storage array chip 10 and the CMOS chip 20 are bonded at the bonding interface SS, it is necessary to detect defects at the bonding interface SS.

[0097] Currently, it is possible to... Figure 5 The test circuit 30 shown detects defects in the bonding interface SS. The test circuit 30 is located in the peripheral area of ​​the bonded memory array chip 10 and CMOS chip 20. Figure 5 This can be understood as the bonded memory array chip 10 and CMOS chip 20 along... Figure 3 A schematic diagram of the cross section near the bonding interface SS obtained after cutting the cross section DD'.

[0098] like Figure 4 and Figure 5As shown, the circuit under test 30 includes a plurality of conductive branches located in the bonding layer 140 of the memory array chip 10, and also includes a plurality of conductive branches located in the bonding layer 240 of the CMOS chip 20.

[0099] In this configuration, the two ends of each conductive branch of the memory array chip 10 are exposed on the bottom surface of the bonding layer 140 in the bonding interface SS, and the two ends of each conductive branch of the CMOS chip 20 are also exposed on the top surface of the bonding layer 240 in the bonding interface SS. After the memory array chip 10 and the CMOS chip 20 are bonded at the bonding interface SS, the conductive branches of the memory array chip 10 and the conductive branches of the CMOS chip 20 are arranged as follows: Figure 5 The circuits shown are also bonded together to form a conductive path that runs through the bonding interface SS. This conductive path is the circuit under test 30.

[0100] like Figure 5 As shown, the two ends of the circuit under test 30 are connected to pin A and pin B, respectively. When it is necessary to detect defects at the bonding interface SS, different voltages are applied to pin A and pin B, and then it is detected whether current flows through the circuit under test 30.

[0101] like Figure 5 As shown, if the bonding interface SS is in Figure 5 If the area marked with an "X" has a defect, then after applying different voltages to pins A and B, no current will be detected in the tested circuit 30 because it is currently in an open-circuit state. Conversely, if the bonding interface SS has no defect, then after applying different voltages to pins A and B, current will be detected in the tested circuit 30 because it is currently in a closed-circuit state.

[0102] Based on the above principles, Figure 5 In the circuit under test 30 shown, if no current is detected in the circuit under test 30 after applying different voltages to pins A and B, it can be determined that there is a defect at the bonding interface SS. If current is detected in the circuit under test 30, it can be determined that there is no defect at the bonding interface SS.

[0103] But through Figure 5 The circuit under test 30 shown can only detect defects already present at the bonding interface. For defects caused by extreme environmental conditions (i.e., potential defects), [the circuit can detect these defects]. Figure 5 The circuit under test shown cannot detect this potential defect. Therefore, this application provides a memory and detection method that can detect potential defects at the bonding interface.

[0104] Among them, potential defects refer to defects such as microcracks that occur at the bonding interface when the bonded chip is subjected to extreme environmental conditions (such as the chip being subjected to a high electric field or high temperature or the high pressure of the wafer dicing process) when there are no defects at the bonding interface.

[0105] The structure of the memory provided in the embodiments of this application will be explained in detail below.

[0106] The memory provided in this application embodiment includes a memory array chip 10 and a CMOS chip 20. The memory array chip 10 includes a first dielectric layer 101 and a first electrode plate 102, with the first electrode plate 102 located within the first dielectric layer 101. The CMOS chip 20 includes a second dielectric layer 201 and a second electrode plate 202, with the second electrode plate 202 located within the second dielectric layer 201. The first dielectric layer 101 and the second dielectric layer 201 are bonded together, and the first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface.

[0107] refer to Figure 4 The first dielectric layer 101 can be understood as a layer distributed upward along the bonding interface SS. In some embodiments, the first dielectric layer 101 can be... Figure 4 The bonding layer 140 is in the middle. Optionally, in other embodiments, the first dielectric layer 101 may be a layer that includes the bonding layer 140 and other layers located on top of the bonding layer 140.

[0108] refer to Figure 4 The second dielectric layer 201 can be understood as a layer distributed downward along the bonding interface SS. In some embodiments, the second dielectric layer 201 can be... Figure 4 The bonding layer 240 is located in the middle. Alternatively, in some embodiments, the second dielectric layer 201 may be a layer that includes the bonding layer 240 and other layers located below the bonding layer 240.

[0109] It should be noted that, in this embodiment, to facilitate understanding of the position of the first electrode plate 102 in the memory array chip 10 and the position of the second electrode plate 202 in the CMOS chip, a first dielectric layer 101 is defined in the memory array chip 10, and a second dielectric layer 201 is defined in the CMOS chip 20. However, the first dielectric layer 101 and the second dielectric layer 201 are not actual layers existing inside the chip. Those skilled in the art, when applying this embodiment, can deploy the first electrode plate 102 and the second electrode plate 202 based on specific scenarios, as long as the first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface SS.

[0110] The first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface SS. This can be understood as: there is a partial bonding interface SS in the space between the two electrodes of the capacitor formed by the first electrode plate 102 and the second electrode plate 202.

[0111] After the first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface SS, if the bonding interface has excellent performance, even if a large voltage is applied to the two electrodes of the capacitor, the structure of the bonding interface will not change significantly under the influence of a large electric field. Therefore, the large voltage will not cause the capacitor to break down. In this scenario, when a voltage is applied to the two electrodes of the capacitor again, no current will be detected between the two electrodes because the two electrodes are currently in an open circuit state. However, if the bonding interface has poor performance, even if there are no defects at the bonding interface, applying a large voltage to the two electrodes may cause the structure of the bonding interface to change under the influence of a large electric field, leading to capacitor breakdown. In this scenario, if the capacitor breaks down, applying a voltage to the two electrodes again will result in a current being detected between the two electrodes because the two electrodes are currently in a closed circuit state. Based on this, the capacitor formed by the first electrode plate 102 and the second electrode plate 202 at the bonding interface can be used to detect potential defects in the bonding interface.

[0112] In some embodiments, the capacitor formed by the first electrode plate 102 and the second electrode plate 202 at the bonding interface SS can be implemented in various ways. Two examples are described below. It should be noted that... Figure 6-9 as well as Figure 12-13 It can be understood as along Figure 3 The diagram shows a partial cross-sectional view of the bonding interface SS near the cross-section DD'. Other components in the cross-section DD' are not shown in the corresponding figures.

[0113] The first implementation method: the two electrodes of the capacitor intersect with the bonding interface.

[0114] Specifically, in some embodiments, such as Figure 6 As shown, the first electrode plate 102 includes a first sub-electrode plate 1021 and a second sub-electrode plate 1022, and the second electrode plate 202 includes a third sub-electrode plate 2021 and a fourth sub-electrode plate 2022. The first sub-electrode plate 1021 and the fourth sub-electrode plate 2022 are bonded together to form one electrode of the capacitor, and the second sub-electrode plate 1022 and the third sub-electrode plate 2021 are bonded together to form the other electrode of the capacitor.

[0115] That is, the first electrode plate 102 and the second electrode plate 202 are bonded together at the bonding interface SS, and the first sub-electrode plate 1021 and the fourth sub-electrode plate 2022 are bonded together to form one electrode of the capacitor, and the second sub-electrode plate 1022 and the third sub-electrode plate 2021 are bonded together to form the other electrode of the capacitor. In other words, each electrode of the capacitor is obtained by bonding a portion of the first electrode plate 102 and a portion of the second electrode plate 202.

[0116] In this process, the two electrodes of the capacitor formed after bonding are used to apply different voltages to detect potential defects in the bonding interface SS.

[0117] in addition, Figure 6 The first electrode plate 102 and the second electrode plate 202 shown can also be referred to as interdigitated electrode structures.

[0118] It should be noted that, Figure 6 Each sub-electrode plate is perpendicular to the bonding interface SS. Optionally, each sub-electrode plate may not be perpendicular to the bonding interface SS, as long as the first sub-electrode plate 1021 and the fourth sub-electrode plate 2022 are bonded at the bonding interface SS, and the second sub-electrode plate 1022 and the third sub-electrode plate 2021 are bonded at the bonding interface SS.

[0119] Optionally, to enable detection at multiple locations on the bonding interface SS, multiple capacitors as described above can be deployed at multiple locations on the bonding interface. Based on this, as... Figure 7 As shown, in some other embodiments, the number of the first sub-electrode plate 1021, the second sub-electrode plate 1022, the third sub-electrode plate 2021, and the fourth sub-electrode plate 2022 is all N, where N is greater than 1 ( Figure 7 (Taking N=4 as an example for explanation). Here, N first sub-electrode plates 1021 and N fourth sub-electrode plates 2022 are bonded one-to-one, and N second sub-electrode plates 1022 and N third sub-electrode plates 2021 are bonded one-to-one, forming N capacitors at the bonding interfaces.

[0120] That is, the first electrode plate 102 includes multiple first sub-electrode plates 1021 and multiple second sub-electrode plates 1022, and the second electrode plate 202 includes multiple third sub-electrode plates 2021 and multiple fourth sub-electrode plates 2022. The multiple first sub-electrode plates 1021 and multiple fourth sub-electrode plates 2022 are bonded in a one-to-one correspondence, and the multiple second sub-electrode plates 1022 and multiple third sub-electrode plates 2021 are bonded in a one-to-one correspondence, so that the first electrode plate 102 and the second electrode plate 202 form multiple capacitors at the bonding interface SS.

[0121] In scenarios consisting of multiple capacitors, each capacitor can be controlled individually to detect potential defects in the bonding interface SS. Controlling each capacitor individually can be understood as applying different voltages to two different capacitors, or applying voltages to two different capacitors for different durations, to achieve precise detection of potential defects at a specific location on the bonding interface SS.

[0122] Alternatively, voltage can be uniformly applied to both poles of each capacitor to quickly detect potential defects in the bonding interface SS.

[0123] Therefore, in other embodiments, such as Figure 8 As shown, the memory array chip 10 further includes a first conductive strip 103, and the CMOS chip further includes a second conductive strip 203. The first conductive strip 103 is connected to the end of the first sub-electrode plate 1021 away from the bonding interface, and is not connected to the end of the second sub-electrode plate 1022 away from the bonding interface. The second conductive strip 203 is connected to the end of the third sub-electrode plate 2021 away from the bonding interface, and is not connected to the end of the fourth sub-electrode plate 2022 away from the bonding interface.

[0124] Based on the above connection relationships, such as Figure 8 As shown, the first conductive strip 103 is uniformly connected to one electrode of each capacitor, and the second conductive strip 203 is uniformly connected to the other electrode of each capacitor. When different voltages are applied to the first conductive strip 103 and the second conductive strip 203 respectively, it is possible to uniformly apply different voltages to the two electrodes of each capacitor.

[0125] Optionally, to facilitate the application of voltage to the first conductive strip 103 and the second conductive strip 203, detection pins can also be configured on the chip. Currently, the bonded post-memory array chip 10 and CMOS chip 20 are basically controlled through pins on the CMOS chip. Based on this, such as Figure 9 As shown, in some embodiments, the memory array chip 10 further includes a first connection line 104, which is connected to the first conductive strip 103. The CMOS chip 20 further includes a second connection line 204, a first detection pin 205, and a second detection pin 206. The second connection line 204 is connected to the first detection pin 205 and is bonded to the first connection line 104. The second detection pin 206 is connected to the second conductive strip 203.

[0126] That is, voltage is applied to the first conductive strip 103 and the second conductive strip 203 through the first detection pin 205 and the second detection pin 206 set on the CMOS chip.

[0127] The first detection pin 205 and the second detection pin 206 are used to apply different voltages. When different voltages are applied to the first detection pin 205 and the second detection pin 206 respectively, the different voltages are applied to the two electrodes of each capacitor through the first conductive strip 103 and the second conductive strip 203 respectively.

[0128] In addition, the first connecting line 104 and the second connecting line 204 can be any lead capable of interconnecting two devices, and this application embodiment does not limit this.

[0129] Alternatively, in some embodiments, detection pins may not be configured on the chip. In this scenario, voltage can be applied to the first conductive strip 103 and the second conductive strip 203 in other ways. For example, dot etching can be performed on the chip surface to expose the first conductive strip 103 and the second conductive strip 203 partially on the chip surface, and then voltage can be applied to the first conductive strip 103 and the second conductive strip 203 through the exposed portion. As another example, when fabricating the first conductive strip 103 and the second conductive strip 203, it is possible to expose one end of the first conductive strip 103 and the second conductive strip 203 on the chip surface, and then apply voltage to the first conductive strip 103 and the second conductive strip 203 through the exposed portion.

[0130] It should be noted that the first conductive strip 103 and the second conductive strip 203, as well as the first detection pin 205 and the second detection pin 206, are described using a scenario with multiple capacitors as an example. Optionally, in a scenario where the first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface SS, the first conductive strip 103 and the second conductive strip 203, as well as the first detection pin 205 and the second detection pin 206, can also be configured, which will not be described in detail here.

[0131] In conclusion, Figure 8-9 The first electrode plate 102, the second electrode plate 202, the first conductive strip 103, and the second conductive strip 203 constitute a test circuit provided in this embodiment of the application. This test circuit can detect potential defects at the bonding interface SS.

[0132] Furthermore, to prevent the circuit under test from affecting the core functions of the chip, in some embodiments, the circuit under test can be deployed in... Figure 3 In the peripheral region of the chip shown. Specifically, as Figure 10 As shown, the first dielectric layer 101 includes a first functional region portion 1011 and a first peripheral region portion 1012, with the first peripheral region portion 1012 surrounding the first functional region portion 1011. Figure 11As shown, the second dielectric layer 201 includes a second functional region portion 2011 and a second peripheral region portion 2012, with the second peripheral region portion 2012 surrounding the second functional region portion 2011.

[0133] Among them, reference Figure 3 The first functional area portion 1011 can be understood as the portion of the first dielectric layer 101 located within the functional area of ​​the memory array chip 10. The first peripheral area portion 1012 can be understood as the portion of the first dielectric layer 101 located within the peripheral area of ​​the memory array chip 10. The second functional area portion 2011 can be understood as the portion of the second dielectric layer 201 located within the functional area of ​​the CMOS chip 20. The second peripheral area portion 2012 can be understood as the portion of the second dielectric layer 201 located within the peripheral area of ​​the CMOS chip 20.

[0134] In this scenario, such as Figure 10 and Figure 11 As shown, the first electrode plate 102 is located in the first peripheral region portion 1012, and the second electrode plate 202 is located in the second peripheral region portion 2012. Since the peripheral regions of the memory array chip 10 and the CMOS chip 20 are bonded together after bonding, it can be understood that the entire circuit under test is located in the peripheral region.

[0135] Additionally, the circuit under test can be deployed in a portion of the peripheral area, such as... Figure 3 The outer area shown is divided into four regions surrounding the functional area: top, bottom, left, and right. Therefore, the circuit under test can be deployed in only one, two, or three of the top four regions.

[0136] Optionally, the circuit under test can be deployed in all four regions (left, right, and top) to improve the comprehensiveness of the test. Specifically, multiple first electrode plates 102 are arranged around the functional area of ​​the memory array chip 10, and multiple second electrode plates 202 are arranged around the functional area of ​​the CMOS chip 20. Thus, after the memory array chip 10 and the CMOS chip 20 are bonded together, the multiple first electrode plates 102 and the multiple second electrode plates 202 are also bonded together to form a complete circuit under test, and this circuit under test is arranged around the functional areas of the two chips.

[0137] Furthermore, in a scenario where the memory array chip 10 also includes a first conductive strip 103 and the CMOS chip 20 also includes a second conductive strip 203, the first conductive strip 103 may also be located in the first peripheral region portion 1012 and the second conductive strip 203 may also be located in the second peripheral region portion 2012.

[0138] For example, such as Figure 10As shown, in the first dielectric layer 101, the first electrode plate 102 and the first conductive strip 103 are both located in the first peripheral region portion 1012, and the first conductive strip 103 is arranged in a ring around the first functional region portion 1011, with each first electrode plate 102 arranged perpendicular to the first conductive strip 103. Figure 11 As shown, in the second dielectric layer 201, the second electrode plate 202 and the second conductive strip 203 are both located in the second peripheral area portion 2012, and the second conductive strip 203 is arranged around the second functional area portion 2011 in a circle, and the second electrode plate 202 is arranged perpendicular to the second conductive strip 203.

[0139] That is, ring-shaped distributions are added to the peripheral areas of the memory array chip 10 and the CMOS chip 20 respectively. Figure 6 The interdigitated electrode structure shown enables the detection of potential defects in the bonding interface SS.

[0140] In addition, such as Figure 10 and Figure 11 As shown, in a scenario where the circuit under test is deployed in the four regions above the outer perimeter, the number and position of the electrode plates deployed in different regions can be the same or different, and this application does not limit this.

[0141] It should be noted that, Figure 10 and Figure 11 This can be understood as a cross-sectional view obtained by looking up and down along the bonding interface SS, and considering the dielectrics in the first and second dielectric layers as transparent.

[0142] The second implementation method: the two poles of the capacitor are not bonded at the interface.

[0143] Specifically, in some embodiments, such as Figure 12 As shown, the first electrode plate 102 and the second electrode plate 202 are located at opposite positions on both sides of the bonding interface, so as to serve as the two electrodes of the capacitor respectively.

[0144] The first electrode plate 102 and the second electrode plate 202 are located at opposite positions on both sides of the bonding interface SS. This can be understood as follows: the first electrode plate 102 and the second electrode plate 202 are located on both sides of the bonding interface SS, and their projection areas on the bonding interface SS are the same.

[0145] In the second implementation, the first electrode plate 102 and the second electrode plate 202 do not need to be bonded at the bonding interface SS. Instead, the first electrode plate 102 and the second electrode plate 202 directly form a capacitor, with the first electrode plate 102 and the second electrode plate 202 being the two electrodes of this capacitor. In this scenario, the bonding interface SS is directly located between the first electrode plate 102 and the second electrode plate 202. By applying different voltages to the first electrode plate 102 and the second electrode plate 202, potential defects at the bonding interface SS can be detected.

[0146] Furthermore, in order to facilitate applying different voltages to the first electrode plate 102 and the second electrode plate 202, such as Figure 13 As shown, in some embodiments, the storage array chip 10 further includes a third connection line 105, which is connected to the first electrode plate 102; the CMOS chip 20 further includes a fourth connection line 207, a third detection pin 208, and a fourth detection pin 209, wherein the fourth connection line 207 is connected to the third detection pin 208, the fourth connection line 207 is bonded to the third connection line 105, and the fourth detection pin 209 is connected to the second electrode plate 202.

[0147] That is, voltage is applied to the first electrode plate 102 and the second electrode plate 202 through the third detection pin 208 and the fourth detection pin 209 set on the CMOS chip.

[0148] The third detection pin 208 and the fourth detection pin 209 are used to apply different voltages. When different voltages are applied to the third detection pin 208 and the fourth detection pin 209 respectively, the different voltages are applied to the two ends of the capacitor formed by the first electrode plate 102 and the second electrode plate 202 respectively.

[0149] In addition, the third connecting line 105 and the fourth connecting line 207 can be any leads capable of interconnecting two devices, and this application embodiment does not limit this.

[0150] Alternatively, in some other embodiments, the detection pins may not be configured on the chip, referring to the first implementation method. The specific implementation method will not be described in detail here.

[0151] Furthermore, in the second implementation, also to avoid the tested circuit affecting the core functions of the chip, in some embodiments, the tested circuit can be deployed in... Figure 3 The chip's peripheral area is shown. For related details, please refer to the first implementation method; further explanation is omitted here.

[0152] For example, such as Figure 14As shown, in the first dielectric layer 101, the first electrode plate 102 is located in the first peripheral region portion 1012, and the first electrode plate 102 is arranged in a ring around the first functional region portion 1011. Figure 15 As shown, in the second dielectric layer 201, the second electrode plate 202 is located in the second peripheral region portion 2012, and the second electrode plate 202 is arranged in a ring around the second functional region portion 2011.

[0153] It should be noted that, Figure 14 and Figure 15 This can be understood as a cross-sectional view obtained by looking up and down along the bonding interface SS, and considering the dielectrics in the first and second dielectric layers as transparent.

[0154] The first and second implementations described above are for illustrative purposes. Optionally, the capacitor structure provided in this application embodiment can also exist in other forms, as long as a partial bonding interface SS exists in the space between the two electrodes of the capacitor composed of the first electrode plate 102 and the second electrode plate 202.

[0155] For example, the first and second implementation methods can be combined. For instance, when... Figure 3 When the peripheral area B shown is divided into four regions (up, down, left, and right), the circuit under test in the first implementation can be deployed in one region, and the circuit under test in the second implementation can be deployed in another region. This will not be explained in detail here.

[0156] Furthermore, the specific process of bonding the first dielectric layer 101 to the second dielectric layer 201 can be found in [reference needed]. Figure 2 The bonding process shown is not repeated here. It should be noted that the embodiments of this application do not limit the bonding process to any specific technology; any technology capable of bonding can be applied to the embodiments of this application.

[0157] Furthermore, in this embodiment, the memory may also include a current detection module. This current detection module is used to detect potential defects at the bonding interface SS via the circuit under test.

[0158] Specifically, the current detection module is used to: apply different voltages to the first electrode plate 102 and the second electrode plate 202 respectively; detect the current flow between the first electrode plate 102 and the second electrode plate 202; and determine that there is a potential defect in the bonding interface when current is detected flowing between the first electrode plate 102 and the second electrode plate 202. Correspondingly, the current detection module is also used to: determine that there is no potential defect in the bonding interface when no current is detected flowing between the first electrode plate 102 and the second electrode plate 202.

[0159] When current is detected flowing between the first electrode plate 102 and the second electrode plate 202, it indicates that the capacitor has broken down under the applied voltage, and therefore a potential defect can be considered to exist at the bonding interface. Conversely, when no current is detected flowing between the first electrode plate 102 and the second electrode plate 202, it indicates that the capacitor has not broken down under the applied voltage, and therefore a potential defect can be considered to exist at the bonding interface.

[0160] The detection of no current flowing between the first electrode plate 102 and the second electrode plate 202 can be understood as: there is no current flowing between the first electrode plate 102 and the second electrode plate 202, or the magnitude of the detected current is lower than the current threshold. The detection of current flowing between the first electrode plate 102 and the second electrode plate 202 can be understood as: the magnitude of the detected current between the first electrode plate 102 and the second electrode plate 202 exceeds the current threshold.

[0161] The current threshold can be configured in advance by a technician, and this application embodiment does not limit this.

[0162] Furthermore, the specific implementation process of the current detection module applying voltages to the first electrode plate 102 and the second electrode plate 202 can be as follows: a first voltage and a second voltage are applied to the first electrode plate 102 and the second electrode plate 202 respectively, and the difference between the first voltage and the second voltage is the first voltage difference; after applying the first voltage and the second voltage, a third voltage and a fourth voltage are applied to the first electrode plate 102 and the second electrode plate 202 respectively, and the difference between the third voltage and the fourth voltage is the second voltage difference, which is less than the first voltage difference.

[0163] In other words, a higher voltage is first applied to the two electrodes of the capacitor to cause it to break down in the presence of a potential defect, and then a lower voltage is applied to test whether the capacitor has broken down. Therefore, the first voltage can trigger capacitor breakdown in the presence of a potential defect at the bonding interface. Specifically, the first voltage can be set by a person skilled in the art based on relevant experience, and this application embodiment does not limit this. For example, the first voltage can be around 10V.

[0164] Furthermore, since the third and fourth voltages are used to test whether the capacitor has broken down under extreme conditions, the second voltage difference is typically smaller than the first voltage difference. For example, the second voltage difference could be around 5V.

[0165] For example, for Figure 9The structure shown allows the first detection pin 205 to be connected to a 10V high voltage, and the second detection pin 206 to be grounded, in order to trigger capacitor breakdown in the event of a potential defect at the bonding interface. This process can be called a stress process. Then, the first detection pin 205 is connected to a 5V high voltage, and the second detection pin 206 is grounded to detect the current between the two electrode plates.

[0166] Furthermore, there are no strict limitations on the loading durations of the first and second voltages, as well as the third and fourth voltages. When applying the embodiments of this application, the loading durations of the first and second voltages can be set shorter, such as around 10ms, to avoid prolonged loading of high voltages causing other negative effects on the chip. The loading durations of the third and fourth voltages can be set longer to accurately determine whether there is current between the two electrodes of the capacitor.

[0167] Optionally, after applying a first voltage and a second voltage to the first electrode plate 102 and the second electrode plate 202 respectively, after applying the first voltage and the second voltage for a period of time, it can be directly tested whether there is current flowing between the first electrode plate 102 and the second electrode plate 202 under the action of the first voltage and the second voltage, thereby determining whether there are potential defects at the bonding interface SS.

[0168] Furthermore, the current sensing module can be configured within the memory array chip 10 or the CMOS chip 20. In this scenario, the current sensing module is directly connected to the circuit under test, thus eliminating the need to deploy sensing pins for applying voltage within the memory array chip 10 or the CMOS chip 20.

[0169] Alternatively, the current sensing module can also be deployed elsewhere besides the memory array chip 10 or the CMOS chip 20. In this scenario, the current sensing module can be connected to the circuit under test via sensing pins located on the chip surface.

[0170] In summary, based on the memory provided in this application embodiment, since the first electrode plate 102 and the second electrode plate 202 form a capacitor at the bonding interface SS, if the performance of the bonding interface SS is excellent, even after applying a large voltage difference across the capacitor, the capacitor will not break down. In this scenario, after applying a voltage difference across the capacitor again, no current will be detected in the tested circuit because it is currently in an open circuit state. However, if the performance of the bonding interface SS is not very good, even if there are no defects at the bonding interface SS, applying a large voltage difference across the capacitor may cause it to break down. In this scenario, after applying a voltage difference across the capacitor again, current will be detected in the tested circuit because it is currently in a closed circuit state. Therefore, it can be seen that the capacitor formed by the first electrode plate 102 and the second electrode plate 202 at the bonding interface SS can realize the detection of potential defects in the bonding interface SS.

[0171] In addition, embodiments of this application also provide a method for detecting a memory. Figure 16 This is a flowchart of a memory detection method provided in an embodiment of this application, as shown below. Figure 16 As shown, the method includes the following steps.

[0172] Step 1601: Apply voltage to the first electrode plate and the second electrode plate respectively.

[0173] Step 1602: Detect the current flow between the first electrode plate and the second electrode plate.

[0174] Step 1603: When current is detected flowing between the first electrode plate and the second electrode plate, it is determined that there is a potential defect in the bonding interface.

[0175] Accordingly, when no current is detected flowing between the first and second electrode plates, it is determined that there are no potential defects at the bonding interface.

[0176] Optionally, the process of applying voltages to the first electrode plate and the second electrode plate can be as follows: applying a first voltage and a second voltage to the first electrode plate and the second electrode plate respectively, and the difference between the first voltage and the second voltage is the first voltage difference; after applying the first voltage and the second voltage, applying a third voltage and a fourth voltage to the first electrode plate and the second electrode plate respectively, and the difference between the third voltage and the fourth voltage is the second voltage difference, which is less than the first voltage difference.

[0177] The implementation methods of steps 1601 to 1603 can refer to the aforementioned content and will not be repeated here.

[0178] In this embodiment, a capacitor is formed at the bonding interface using a first electrode plate and a second electrode plate. If the bonding interface has excellent performance, even if a large voltage is applied to the two electrodes of the capacitor, the structure of the bonding interface will not change significantly under a large electric field, and therefore the large voltage will not cause the capacitor to break down. In this scenario, when a voltage is applied to the two electrodes of the capacitor again, no current will be detected between them because the two electrodes are currently in an open circuit state. However, if the bonding interface has poor performance, even if there are no defects at the bonding interface, applying a large voltage to the two electrodes may cause the structure of the bonding interface to change under a large electric field, leading to capacitor breakdown. In this scenario, if the capacitor breaks down, applying a voltage to the two electrodes again will result in a current being detected between them because the two electrodes are currently in a closed circuit state. Based on this, the capacitor formed by the first and second electrode plates at the bonding interface can detect potential defects at the bonding interface.

[0179] Therefore, this detection method can be used during chip fabrication to screen out chips with potential defects at the bonding interface, thereby improving the quality and reliability of the fabricated 3D memory products and shortening the development-to-mass production cycle. Furthermore, it can reduce the failure probability of end products using 3D memory, thus saving costs on subsequent end products.

[0180] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is understood that "first," "second," etc., may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0181] It should be understood that the phrase "some embodiments" throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0182] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0183] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory includes a memory array chip (10) and a complementary metal-oxide-semiconductor (CMOS) chip (20). The storage array chip (10) includes a first dielectric layer (101) and a first electrode plate (102), wherein the first electrode plate (102) is located in the first dielectric layer (101); The CMOS chip (20) includes a second dielectric layer (201) and a second electrode plate (202), wherein the second electrode plate (202) is located in the second dielectric layer (201); The first dielectric layer (101) and the second dielectric layer (201) are bonded together, and the first electrode plate (102) and the second electrode plate (202) form a capacitor at the bonding interface; The first dielectric layer (101) includes a first functional area portion (1011) and a first peripheral area portion (1012), the first peripheral area portion (1012) surrounds the first functional area portion (1011), and the first electrode plate (102) is located in the first peripheral area portion (1012); The second dielectric layer (201) includes a second functional region portion (2011) and a second peripheral region portion (2012), the second peripheral region portion (2012) surrounding the second functional region portion (2011), and the second electrode plate (202) located in the second peripheral region portion (2012); The memory further includes a test circuit, which includes a capacitor formed by the first electrode plate (102) and the second electrode plate (202) at the bonding interface of the first peripheral region and the second peripheral region. The test circuit is used to detect potential defects at the bonding interface of the first peripheral region and the second peripheral region.

2. The memory as claimed in claim 1, characterized in that, The first electrode plate (102) includes a first sub-electrode plate (1021) and a second sub-electrode plate (1022), and the second electrode plate (202) includes a third sub-electrode plate (2021) and a fourth sub-electrode plate (2022). The first sub-electrode plate (1021) and the fourth sub-electrode plate (2022) are bonded together to form one electrode of the capacitor, and the second sub-electrode plate (1022) and the third sub-electrode plate (2021) are bonded together to form the other electrode of the capacitor.

3. The memory as described in claim 2, characterized in that, The number of the first sub-electrode plate (1021), the second sub-electrode plate (1022), the third sub-electrode plate (2021), and the fourth sub-electrode plate (2022) is N, where N is greater than 1; N first sub-electrode plates (1021) and N fourth sub-electrode plates (2022) are bonded one-to-one, and N second sub-electrode plates (1022) and N third sub-electrode plates (2021) are bonded one-to-one to form N capacitors at the bonding interface.

4. The memory as described in claim 2 or 3, characterized in that, The storage array chip (10) further includes a first conductive strip (103), which is located in the first dielectric layer (101). The first conductive strip (103) is connected to the end of the first sub-electrode plate (1021) away from the bonding interface, and the first conductive strip (103) is not connected to the end of the second sub-electrode plate (1022) away from the bonding interface. The CMOS chip (20) further includes a second conductive strip (203), which is located in the second dielectric layer (201). The second conductive strip (203) is connected to the end of the third sub-electrode plate (2021) away from the bonding interface, and the second conductive strip (203) is not connected to the end of the fourth sub-electrode plate (2022) away from the bonding interface.

5. The memory as claimed in claim 4, characterized in that, The storage array chip (10) further includes a first connecting line (104), which is connected to the first conductive strip (103); The CMOS chip (20) further includes a second connection line (204), a first detection pin (205) and a second detection pin (206). The second connection line (204) is connected to the first detection pin (205), the second connection line (204) is bonded to the first connection line (104), and the second detection pin (206) is connected to the second conductive strip (203).

6. The memory as claimed in claim 1, characterized in that, The first electrode plate (102) and the second electrode plate (202) are located at opposite positions on both sides of the bonding interface to serve as the two electrodes of the capacitor, respectively.

7. The memory as claimed in claim 6, characterized in that, The storage array chip (10) also includes a third connection line (105), which is connected to the first electrode plate (102); The CMOS chip (20) further includes a fourth connection line (207), a third detection pin (208) and a fourth detection pin (209). The fourth connection line (207) is connected to the third detection pin (208), the fourth connection line (207) is bonded to the third connection line (105), and the fourth detection pin (209) is connected to the second electrode plate (202).

8. A method for detecting a memory, characterized in that, The memory is the memory according to any one of claims 1-7; the method includes: Voltages are applied to the first electrode plate (102) and the second electrode plate (202) respectively; The current flow between the first electrode plate (102) and the second electrode plate (202) is detected; When current is detected flowing between the first electrode plate (102) and the second electrode plate (202), it is determined that there is a potential defect in the bonding interface.

9. The method as described in claim 8, characterized in that, The method further includes: When no current is detected between the first electrode plate (102) and the second electrode plate (202), it is determined that there are no potential defects in the bonding interface.

10. The method as described in claim 8 or 9, characterized in that, Applying voltage to the first electrode plate (102) and the second electrode plate (202) respectively includes: A first voltage and a second voltage are applied to the first electrode plate (102) and the second electrode plate (202) respectively, and the difference between the first voltage and the second voltage is the first voltage difference; After the first voltage and the second voltage are applied, a third voltage and a fourth voltage are applied to the first electrode plate (102) and the second electrode plate (202) respectively. The difference between the third voltage and the fourth voltage is the second voltage difference, and the second voltage difference is less than the first voltage difference.

Images