Image sensors and semiconductor packaging

Abstract

An image sensor and semiconductor package are disclosed. The image sensor includes: a substrate including a plurality of functional chips, the plurality of functional chips including: a first analog-to-digital converter chip disposed along a first edge of the substrate; a first image signal processing chip disposed on a side of the first analog-to-digital converter chip facing the center of the substrate; and a first memory chip disposed along a second edge of the substrate adjacent to the first edge, or disposed at the center of the substrate; a first wiring layer including: an electrical connection between the first analog-to-digital converter chip and the first image signal processing chip; and an electrical connection between the first image signal processing chip and the first memory chip; a pixel array; and a second wiring layer formed on a surface of the pixel array away from the light incident surface, wherein the first wiring layer and the second wiring layer are co-bonded, such that the first analog-to-digital converter chip is electrically connected to the pixel array.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an image sensor and a semiconductor package. Background Technology

[0002] With the arrival of a new wave of technological advancements, technologies such as 5G, big data, the Internet of Things, artificial intelligence, and smart terminals are developing at an extremely rapid pace. Image sensors, as a typical representative of smart terminals, are one of the core components for realizing these technologies.

[0003] In terms of image sensor architecture, earlier planar structures designed and manufactured pixel arrays and functional modules on the same wafer. The improved multi-layer stacked structure, however, designs and manufactures pixel arrays and functional modules on different wafers, with different functional modules manufactured on separate wafers, and then integrates the system through wafer-level stacking.

[0004] However, due to the increased data acquisition volume and significantly higher requirements for image processing, computing, and storage in applications such as 5G and the Internet of Things, more wafers need to be stacked. However, when using multi-layer stacking structures, wafers of the same size can typically be used. Furthermore, as the number of stacked layers increases, the stacking process requirements become more stringent, overall yield decreases, and overall costs increase significantly. Summary of the Invention

[0005] It would be beneficial to provide a mechanism to alleviate, reduce, or even eliminate one or more of the aforementioned problems.

[0006] According to one aspect of this disclosure, an image sensor is provided, comprising: a substrate, the substrate including a plurality of functional chips integrated onto a first surface of the substrate, wherein the plurality of functional chips includes: a first analog-to-digital converter chip disposed along a first edge of the substrate; a first image signal processing chip disposed on a side of the first analog-to-digital converter chip facing the center of the substrate; and a first memory chip disposed along a second edge of the substrate adjacent to the first edge, or disposed at the center of the substrate; a first wiring layer formed on the plurality of functional chips, wherein the first wiring layer includes: an electrical connection between the first analog-to-digital converter chip and the first image signal processing chip; and an electrical connection between the first image signal processing chip and the first memory chip; a pixel array; and a second wiring layer formed on a surface of the pixel array away from a light incident surface, wherein the first wiring layer and the second wiring layer are co-bonded such that the first analog-to-digital converter chip is electrically connected to the pixel array.

[0007] According to another aspect of this disclosure, a semiconductor package is provided, including the image sensor as described above.

[0008] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0009] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0010] Figures 1A to 1B This is a schematic diagram illustrating an existing image sensor architecture;

[0011] Figures 2A to 2B This is a schematic diagram illustrating an image sensor according to an exemplary embodiment of the present disclosure;

[0012] Figure 3 This is a cross-sectional view showing an image sensor according to an exemplary embodiment of the present disclosure;

[0013] Figures 4A to 4E This is a schematic diagram illustrating the layout of a plurality of functional chips in an image sensor according to an exemplary embodiment of the present disclosure;

[0014] Figures 5A to 5E This is a schematic diagram illustrating the layout of a plurality of functional chips in an image sensor according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0015] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0016] Spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “above,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below,” “below,” or “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary terms “below” and “below” can cover both orientations above and below. Terms such as “before” or “in front” and “after” or “follow” can similarly be used, for example, to indicate the order in which light passes through the elements. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein shall be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or there can be one or more intermediate layers.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including” as used in this specification designate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items, and the phrase “at least one of A and B” means only A, only B, or both A and B.

[0018] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0019] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0020] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0021] As used herein, the terms chip and die are used interchangeably unless such interchange would cause conflict. It should be understood that the term "layer" includes thin films and should not be construed as indicating vertical or horizontal thickness unless otherwise stated.

[0022] Existing image sensor architectures include earlier planar structures and improved multi-layer stacked structures.

[0023] Figure 1A An image sensor 100A with a planar structure is shown. For example... Figure 1AAs shown, pixel array 101 and functional modules 102-105 are both located on substrate 110. As described above, pixel array 101 and functional modules 102-105 are designed and manufactured using the same wafer. The planar structure has a simple process and mature technology; however, the process is not flexible enough, making it difficult to simultaneously accommodate the processes of pixel array 101 and functional modules 102-105, and the image sensor's footprint area is relatively large.

[0024] Figure 1B An image sensor 100B employing a multi-layer stacked structure is shown. For example... Figure 1B As shown, the image sensor 100B includes a pixel array 101 and functional modules 102-105 stacked layer by layer. The pixel array 101 and functional modules 102-105 are designed and manufactured using different wafers, and then integrated into a system through wafer-level stacking. However, multi-layer stacking processes are quite challenging. Specifically, as the number of stacked layers increases, the yield decreases and the cost increases.

[0025] This disclosure provides an improved image sensor, comprising: a substrate, the substrate including a plurality of functional chips integrated onto a first surface of the substrate, wherein the plurality of functional chips include: a first analog-to-digital converter chip disposed along a first edge of the substrate; a first image signal processing chip disposed on a side of the first analog-to-digital converter chip facing the center of the substrate; and a first memory chip disposed along a second edge of the substrate adjacent to the first edge, or disposed at the center of the substrate; a first wiring layer formed on the plurality of functional chips, wherein the first wiring layer includes: an electrical connection between the first analog-to-digital converter chip and the first image signal processing chip; and an electrical connection between the first image signal processing chip and the first memory chip; a pixel array; and a second wiring layer formed on a surface of the pixel array away from the light incident surface, wherein the first wiring layer and the second wiring layer are co-bonded such that the first analog-to-digital converter chip is electrically connected to the pixel array.

[0026] Figure 2A-2B This is a schematic diagram illustrating an image sensor 200 according to an exemplary embodiment of the present disclosure.

[0027] like Figure 2A-2B As shown, the image sensor 200 includes a substrate 210, a first wiring layer 220, a second wiring layer 230, and a pixel array 240.

[0028] According to some embodiments, the substrate 210 includes a plurality of functional chips 201-203 integrated onto a first surface of the substrate 210, wherein the plurality of functional chips 201-203 include a first analog-to-digital converter (ADC) chip 201, a first image signal processor (ISP) chip 202, and a first memory chip 203.

[0029] According to some embodiments, such as Figure 2A As shown, a first ADC chip 201 is disposed along a first edge of the substrate 210, a first ISP chip 202 is disposed on the side of the first ADC chip 201 facing the center of the substrate 210, and a first memory chip 203 is disposed along a second edge of the substrate 210 adjacent to the first edge. According to other embodiments, such as... Figure 2B As shown, the first ADC chip is disposed along the first edge of the substrate 210, the first ISP chip 202 is disposed on the side of the first ADC chip facing the center of the substrate 210, and the first memory chip 203 is disposed at the center of the substrate 210.

[0030] According to some embodiments, a first wiring layer 220 is formed on a plurality of functional chips 201-203 to realize electrical connections between the plurality of functional chips 201-203 and to the pixel array 240. According to some embodiments, the first wiring layer 220 includes: an electrical connection between a first ADC chip 201 and a first ISP chip 202 and an electrical connection between the first ISP chip 202 and a first memory chip 203.

[0031] According to some embodiments, a second wiring layer 230 is formed on the surface of the pixel array 240 away from the light incident surface to achieve electrical connection between the pixel array 240 and the plurality of functional chips 201-203. According to some embodiments, the first wiring layer 220 and the second wiring layer 230 are co-bonded to electrically connect the first ADC chip 201 to the pixel array 240.

[0032] According to some embodiments, a plurality of functional chips 201-203 are disposed on a first surface of a substrate 210, wherein the substrate 210 further includes a filler formed on the first surface of the substrate 210 to fill the gaps between each of the plurality of functional chips 201-203 and expose the pads of the plurality of functional chips.

[0033] According to some embodiments, the image sensor 200 further includes: a color filter formed above the light incident surface of the pixel array 240; and a microlens formed above the color filter.

[0034] According to some embodiments, in addition to the ADC chip, ISP chip, and memory chip, the multiple functional chips integrated onto the substrate 210 also include a computing chip for further processing image data. According to some embodiments, the computing chip is an artificial intelligence chip and / or an FPGA chip.

[0035] According to some embodiments, the multiple functional chips are chips manufactured using multiple processes.

[0036] According to some embodiments, multiple functional chips are verified chips.

[0037] Therefore, in the image sensor as described in this disclosure, electrical signal transmission in the image sensor 200 is achieved through hybrid bonding between the first wiring layer 220, the second wiring layer 230, and the first wiring layer 220 and the second wiring layer 230. According to some embodiments, the pixel array 240 acquires image signals and transmits the acquired analog image signals to the first ADC chip 201; the first ADC chip 201 converts the received analog image signals into digital image signals and transmits the digital image signals to the first ISP chip 202; the first ISP chip 202 receives the digital image signals from the first ADC chip 201 and reads signals from the first storage chip 203 to perform image processing (e.g., noise reduction, high dynamic range lighting correction, etc.), and stores the received digital image signals or processed signals in the first storage chip 203.

[0038] In the image sensor architecture provided in this disclosure, functional diversification is achieved by integrating multiple functional chips onto the same substrate; and since only two layers of stacking of substrate and pixel wafer are required, the process difficulty can be significantly reduced while meeting the requirements of functional diversification.

[0039] Furthermore, in the exemplary embodiments of this disclosure, by setting the positions of multiple functional chips 201-203, the length of electrical connections in the image sensor is shortened, signal crosstalk is reduced, and efficient signal transmission is facilitated. Specifically, since the output pins of the pixel array 240 are located at the edge of the pixel array, setting the first ADC chip 201 at the edge of the substrate 210 can shorten the length of the electrical connection between the pixel array 240 and the first ADC chip 201. Since the first ISP chip 202 is located on one side of the first ADC chip 201, the length of the electrical connection between the first ADC chip 201 and the first ISP chip 202 can be shortened.

[0040] Figure 3 This is a cross-sectional view showing an image sensor 300 according to an exemplary embodiment of the present disclosure. According to some embodiments, the image sensor 300 may be an image sensor 200 as described with reference to FIG2.

[0041] like Figure 3 As shown, the image sensor 300 includes: a substrate 310, a first wiring layer 330, a pixel array 340, and a second wiring layer 350. The substrate 310 includes multiple sets of functional chips 301, 302, and 303 integrated onto its first surface. Each set of functional chips includes a memory chip, an analog-to-digital converter chip, and an image signal processing chip. The first wiring layer 330 is formed on the functional chips 301-303. The second wiring layer 350 is formed on the surface of the pixel array 340 away from the light incident surface.

[0042] According to some embodiments, each pixel array includes multiple photodiodes, for example, Figure 3 As shown, pixel array 340 includes photodiodes 3411-3415.

[0043] According to some embodiments, in the semiconductor device 300, the first wiring layer 330 and the second wiring layer 350 are co-bonded, so that a plurality of functional chips 301-303 are electrically connected to the pixel array 340.

[0044] According to some embodiments, such as Figure 3 As shown, a plurality of functional chips 301-303 are disposed on the first surface of substrate 310, and wherein substrate 310 further includes a filler 321 formed on the first surface of substrate 310 to fill the gaps between each of the plurality of functional chips 301-303 and expose the pads of the plurality of functional chips 301-303.

[0045] According to other embodiments, as Figure 3 In an alternative embodiment of the illustrated embodiment, substrate 310 further includes a plurality of recesses formed in the substrate, wherein each of the plurality of functional chips 301-303 is embedded in the recess corresponding to the functional chip. According to some embodiments, each of the plurality of functional chips 301-303 is disposed in the recess corresponding to the functional chip, and wherein substrate 310 further includes a filler disposed in each of the plurality of recesses to fill the gap between each recess and the chip disposed therein.

[0046] According to some embodiments, the first wiring layer 330 includes: a first metal interconnect portion (e.g. Figure 3 As shown, the first metal interconnect portion includes electrical interconnects 3311-3316 and a first insulator portion 332, wherein the first metal interconnect portion is connected to the pads (not shown) of a plurality of functional chips.

[0047] According to some embodiments, the first metal interconnect portion includes electrical interconnects between multiple chips in each group of functional chips to combine the multiple chips into a functional circuit for processing image signals.

[0048] According to other embodiments, the first metal interconnect portion also includes electrical interconnects from each of the multiple sets of functional chips to the corresponding pixel array.

[0049] According to some embodiments, the second wiring layer 350 includes: a second metal interconnect portion (e.g. Figure 3 As shown, the second metal interconnect portion includes electrical interconnects 3511-3515 and a second insulator portion 352, wherein the second metal interconnect portion is connected to the output pads (not shown) of the pixel array 340. According to some embodiments, the second metal interconnect portion includes electrical connections between the pixel array and the corresponding functional chip.

[0050] According to some embodiments, the first metal interconnect portion includes a first metal bonding portion, and the second metal interconnect portion includes a second metal bonding portion, wherein the first metal bonding portion is attached to the second metal bonding portion such that the first metal bonding portion and the second metal bonding portion are electrically connected.

[0051] According to some embodiments, the pixel array further includes: a BDTI structure (e.g., Figure 3 The BDTI structure 3421 is located between photodiodes 3411 and 3412, wherein the BDTI structure is formed between adjacent pixels and around the photodiode.

[0052] According to some embodiments, the pixel array further includes a back surface TSV extending from the side of the pixel array away from the light incident surface to the light incident surface, wherein the back surface TSV is formed in a non-pixel region of the pixel array.

[0053] According to some embodiments, the pixel array further includes a back pad, wherein the back pad is formed at a position on the light incident surface of the pixel array corresponding to the back TSV.

[0054] According to some embodiments, the pixel array further includes: a metal grid (e.g., Figure 3 The metal grid 3611 is located above the BDTI structure 3421, wherein the metal grid is formed at the position corresponding to the BDTI structure on the light incident surface of the pixel array.

[0055] According to some embodiments, the pixel array further includes: microlenses 361-365, formed above the light incident surface of the pixel array; and color filters 371-375, formed above the microlenses 361-365 (e.g., as shown in the original text). Figure 3As shown, microlens 371 is formed above color filter 361.

[0056] According to some embodiments, each group of functional chips also includes a computing chip, wherein the computing chip is an artificial intelligence chip and / or an FPGA chip.

[0057] According to some embodiments, each group of functional chips is a chip manufactured using multiple processes.

[0058] According to some embodiments, the functional chip is a verified chip.

[0059] It should be understood that Figure 3 The number of functional chip groups, the number of chips in each functional chip group, the number of pixel arrays, and the number of pixels in each pixel array shown are merely illustrative, and the number of functional chip groups, the number of chips in each functional chip group, the number of pixel arrays, or the number of pixels in each pixel array in a semiconductor device can be fewer or more. Similarly, it should be understood that... Figure 3 The structures of the first and second metal interconnect portions shown are merely illustrative; the first or second metal interconnect portion can be... Figure 3 The different structures shown.

[0060] In the image sensor architecture provided in this disclosure, since multiple functional chips are integrated onto the same substrate, it is crucial to rationally arrange these functional chips and their electrical connections. The following, in conjunction with... Figures 4A to 4E and Figures 5A-5E The layout of a plurality of functional chips in an image sensor according to exemplary embodiments of the present disclosure is described.

[0061] exist Figures 4A to 5E For ease of understanding, the signal flow between multiple functional chips is illustrated using lines. However, it should be understood that... Figures 4A to 5E The signal flow shown is merely illustrative, and other signal flow forms may also be used. In the image sensor provided in this disclosure, as described with reference to FIG2, multiple functional chips are interconnected through electrical connections in a first wiring layer. Figures 4A to 5E The signal flow shown can be achieved, for example, through various electrical connections in the first wiring layer.

[0062] According to some embodiments, the plurality of functional chips include a first ADC chip, a first ISP chip, and a first memory chip, wherein the first memory chip is disposed along the edge of the substrate.

[0063] Figure 4AThe illustration shows a plurality of functional chips on substrate 410, including a first ADC chip 401a, a first ISP chip 402a and a first memory chip 403a, with the first memory chip disposed along the edge of the substrate.

[0064] like Figure 4A As shown, the first ADC chip 401a is disposed along the first edge of the substrate 410, the first ISP chip 402a is disposed on the side of the first ADC chip 401a facing the center of the substrate 410, and the first memory chip 403a is disposed along the second edge of the substrate 410 adjacent to the first edge.

[0065] The first ADC chip 401a receives analog image signals from the pixel array and transmits the converted digital image signals to the first ISP chip 402a. The first ISP chip 402a receives the digital image signals from the first ADC chip 401a and reads the data stored in the first memory chip 403a to perform image processing (e.g., noise reduction, high dynamic range lighting correction, etc.), and stores the received digital image signals or processed data in the first memory chip 403a.

[0066] In such Figure 4A In the illustrated layout, since the output pins of the pixel array are typically located at the edge of the pixel array, placing the first ADC chip 401a along the first edge of the substrate 410 will shorten the length of the electrical connection between the pixel array and the first ADC chip 401a. Furthermore, since the first ISP chip 402a receives signals from the first ADC chip 401a, placing the first ISP chip 402a on one side of the first ADC chip 401a will shorten the length of the electrical connection between the first ADC chip 401a and the first ISP chip 402a. Shortening the length of the electrical connection helps reduce signal crosstalk and achieves efficient signal transmission.

[0067] According to some embodiments, the first memory chip is disposed along a second edge of the substrate adjacent to the first edge, and the plurality of functional chips further include: a computing chip disposed at the center of the substrate, wherein the first wiring layer further includes: an electrical connection between the first ISP chip and the computing chip; and an electrical connection between the computing chip and the first memory chip.

[0068] Figure 4B The illustration shows a combination of multiple functional chips on substrate 410, including a first ADC chip 401a, a first ISP chip 402a, a first memory chip 403a, and a computing chip 404.

[0069] like Figure 4B As shown, the positions and references of the first ADC chip 401a, the first ISP chip 402a, and the first memory chip 403a are... Figure 4A The same applies as described, except that the computing chip 404 is located at the center of the substrate 410.

[0070] The first ADC chip 401a receives an analog image signal from the pixel array and transmits the converted digital image signal to the first ISP chip 402a. The first ISP chip 402a receives the digital image signal from the first ADC chip 401a and reads the data stored in the first storage chip 403a to perform image processing, and stores the received digital image signal or the processed data in the first storage chip 403a. The computing chip 404 receives the processed signal from the first ISP chip 402a and reads the data stored in the first storage chip 403a to perform further image processing, and stores the data corresponding to the processed signal in the first storage chip 403a.

[0071] In such Figure 4B In the layout shown, besides the reference Figure 4A The described method can shorten the length of the electrical connection between the pixel array and the first ADC chip 401a and the electrical connection between the first ADC chip 401a and the first ISP chip 402a. Since the computing chip 404, which interacts with both the first ISP chip 402a and the first memory chip 403a, is located at the center of the substrate 410, the length of the electrical connection between the computing chip 404 and the first ISP chip 402a and the first memory chip 403a can be shortened.

[0072] According to some embodiments, the plurality of functional chips further include: a second ADC chip disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second ADC chip to be electrically connected to the pixel array; and a second ISP chip disposed on the side of the second ADC chip facing the center of the substrate, wherein the first wiring layer further includes: an electrical connection between the second ADC chip and the second ISP chip; an electrical connection between the second ISP chip and the computing chip; and an electrical connection between the second ISP chip and the first memory chip.

[0073] Figure 4C The illustration shows a combination of multiple functional chips on substrate 410, including a first ADC chip 401a, a first ISP chip 402a, a first memory chip 403a, a second ADC chip 401b, a second ISP chip 402b, and a computing chip 404.

[0074] like Figure 4C As shown, the positions and references of the first ADC chip 401a, the first ISP chip 402a, the first memory chip 403a, and the computing chip 404 are... Figure 4BThe same configuration is described, but the second ADC chip 401b is disposed along the third edge of the substrate 410 opposite to the first edge, and the second ISP chip 402b is disposed on the side of the second ADC chip 401b facing the center of the substrate 410. The hybrid bonding of the first wiring layer and the second wiring layer also enables the second ADC chip 401b to be electrically connected to the pixel array.

[0075] The first ADC chip 401a and the second ADC chip 401b receive analog image signals from the pixel array and transmit the converted digital image signals to the first ISP chip 402a and the second ISP chip 402b, respectively. The first ISP chip 402a receives the digital image signals from the first ADC chip 401a and reads data stored in the first storage chip 403a for image processing, and stores the received digital image signals or processed data in the first storage chip 403a. The second ISP chip 402b receives the digital image signals from the second ADC chip 401b and reads data stored in the second storage chip 403b for image processing, and stores the received digital image signals or processed data in the first storage chip 403a. The computing chip 404 receives the processed signals from the first ISP chip 402a and the second ISP chip 402b and reads data stored in the first storage chip 403a for further image processing, and stores the data corresponding to the processed signals in the first storage chip 403a.

[0076] In such Figure 4C In the layout shown, besides the reference Figure 4A The described method can shorten the length of the electrical connection between the pixel array and the first ADC chip 401a, and the electrical connection between the first ADC chip 401a and the first ISP chip 402a. Setting the second ADC chip 401b along the third edge of the substrate 410 will shorten the length of the electrical connection between the pixel array and the second ADC chip 401b. Since the second ISP chip 402b receives signals from the second ADC chip 401b, setting the second ISP chip 402b to one side of the second ADC chip 401b will shorten the length of the electrical connection between the second ADC chip 401b and the second ISP chip 402b. Since the computing chip 404, which interacts with the first ISP chip 402a, the second ISP chip 402b, and the first memory chip 403a, is located at the center of the substrate 410, the length of the electrical connection between the computing chip 404 and the first ISP chip 402a, the second ISP chip 402b, and the first memory chip 403a can be shortened.

[0077] According to some embodiments, the electrical connections in the first wiring layer include high-speed signal electrical connections and low-speed signal electrical connections. If the signal carried by the electrical connection has a frequency greater than 50MHz or a signal rise or fall time shorter than 50ps, then the electrical connection can be called a high-speed signal electrical connection; otherwise, the electrical connection is called a low-speed signal electrical connection.

[0078] In such Figure 4C In the example shown, the electrical connection between the computing chip 404 and the first memory chip 403a is a high-speed signal electrical connection, while the electrical connections between the first ADC chip 401a and the first ISP chip 402a, the first ISP chip 402a and the first memory chip 403a, the first ISP chip 402a and the computing chip 404, the second ADC chip 401b and the second ISP chip 402b, the second ISP chip 402b and the second memory chip 403b, and the second ISP chip 402b and the computing chip 404 are low-speed signal electrical connections.

[0079] To avoid crosstalk between high-speed and low-speed signals, the distance between the high-speed signal electrical connection and each low-speed signal electrical connection can be set to be greater than the distance between the low-speed signal electrical connections.

[0080] According to some embodiments, for electrical connections in the first wiring layer, the electrical connection between the computing chip and the first memory chip is a high-speed signal electrical connection, and the remaining electrical connections in the first wiring layer are low-speed signal electrical connections. The distance between the high-speed signal electrical connection and each low-speed signal electrical connection is greater than a first distance threshold, and the distance between each low-speed signal electrical connection is greater than a second distance threshold. The first distance threshold is greater than the second distance threshold.

[0081] For example, in Figure 4C In the example shown, the distance between the electrical connection between the computing chip 404 and the first memory chip 403a and the electrical connection between the first ISP chip 402a and the first memory chip 403a can be set to be greater than the distance between the electrical connection between the first ADC chip 401a and the first ISP chip 402a and the electrical connection between the first ISP chip 402a and the first memory chip 403a.

[0082] To further avoid crosstalk between high-speed and low-speed signals, the length of the parallel trace between the high-speed signal electrical connection and each low-speed signal electrical connection can be set to be less than the length of the parallel trace between the low-speed signal electrical connections.

[0083] According to some embodiments, the parallel trace length between the high-speed signal electrical connection and each low-speed signal electrical connection is less than a first length threshold, and the parallel trace length between each low-speed signal electrical connection is less than a second length threshold, wherein the first length threshold is less than the second length threshold.

[0084] For example, in Figure 4C In the example shown, the parallel trace lengths of the electrical connections between the computing chip 404 and the first memory chip 403a, and between the first ISP chip 402a and the first memory chip 403a, can be set to be less than the parallel trace lengths between the electrical connections between the first ADC chip 401a and the first ISP chip 402a, and between the first ISP chip 402a and the first memory chip 403a.

[0085] To further avoid crosstalk between high-speed and low-speed signals, shielded ground wires can be installed on both sides of the high-speed signal electrical connection.

[0086] According to some embodiments, the first wiring layer further includes: a shielded ground wire disposed on both sides of the high-speed signal electrical connection.

[0087] For example, in such Figure 4C In the example shown, shielded ground wires can be provided on both sides of the electrical connection between the computing chip 404 and the first memory chip 403a.

[0088] According to some embodiments, the plurality of functional chips further include: a second ADC chip disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second ADC chip to be electrically connected to the pixel array; a second ISP chip disposed on a side of the second ADC chip facing the center of the substrate; and a second memory chip disposed along a fourth edge of the substrate opposite to the second edge; wherein the first wiring layer further includes: an electrical connection between the second ADC chip and the second ISP chip; an electrical connection between the second ISP chip and the computing chip; an electrical connection between the second ISP chip and the second memory chip; and an electrical connection between the computing chip and the second memory chip.

[0089] Figure 4D The illustration shows a first layout of multiple functional chips on substrate 410, including a first ADC chip 401a, a first ISP chip 402a, a first memory chip 403a, a second ADC chip 401b, a second ISP chip 402b, a second memory chip 403b, and a computing chip 404.

[0090] like Figure 4DAs shown, the positions and references of the first ADC chip 401a, the first ISP chip 402a, the first memory chip 403a, and the computing chip 404 are... Figure 4B The same configuration is described, but the second ADC chip 401b is disposed along the third edge of the substrate 410 opposite to the first edge, the second ISP chip 402b is disposed on the side of the second ADC chip 401b facing the center of the substrate 410, and the second memory chip 403b is disposed along the fourth edge of the substrate 410 opposite to the second edge. The hybrid bonding of the first wiring layer and the second wiring layer also enables the second ADC chip 401b to be electrically connected to the pixel array.

[0091] The first ADC chip 401a and the second ADC chip 401b receive analog image signals from the pixel array and transmit the converted digital image signals to the first ISP chip 402a and the second ISP chip 402b, respectively. The first ISP chip 402a receives the digital image signals from the first ADC chip 401a and reads data stored in the first storage chip 403a for image processing, and stores the received digital image signals or processed data in the first storage chip 403a. The second ISP chip 402b receives the digital image signals from the second ADC chip 401b and reads data stored in the second storage chip 403b for image processing, and stores the received digital image signals or processed data in the second storage chip 403b. The computing chip 404 receives the processed signals from the first ISP chip 402a and the second ISP chip 402b, and reads data stored in the first storage chip 403a and the second storage chip 403b for further image processing, and stores the data corresponding to the processed signals in the first storage chip 403a and the second storage chip 403b.

[0092] In such Figure 4D In the layout shown, besides the reference Figure 4AThe described method can shorten the length of the electrical connection between the pixel array and the first ADC chip 401a, and the electrical connection between the first ADC chip 401a and the first ISP chip 402a. Setting the second ADC chip 401b along the third edge of the substrate 410 will shorten the length of the electrical connection between the pixel array and the second ADC chip 401b. Since the second ISP chip 402b receives signals from the second ADC chip 401b, setting the second ISP chip 402b to one side of the second ADC chip 401b will shorten the length of the electrical connection between the second ADC chip 401b and the second ISP chip 402b. Since the computing chip 404, which interacts with the first ISP chip 402a, the second ISP chip 402b, the first memory chip 403a, and the second memory chip 403b, is located at the center of the substrate 410, the length of the electrical connection between the computing chip 404 and the first ISP chip 402a, the second ISP chip 402b, the first memory chip 403a, and the second memory chip 403b can be shortened.

[0093] According to other embodiments, the plurality of functional chips further include: a second ADC chip disposed along a fourth edge of the substrate opposite to the second edge, wherein the co-bonding of the first wiring layer and the second wiring layer further enables the second ADC chip to be electrically connected to the pixel array; a second ISP chip disposed on a side of the second ADC chip facing the center of the substrate; and a second memory chip disposed along a third edge of the substrate opposite to the first edge; wherein the first wiring layer further includes: an electrical connection between the second ADC chip and the second ISP chip; an electrical connection between the second ISP chip and the computing chip; an electrical connection between the second ISP chip and the second memory chip; and an electrical connection between the computing chip and the second memory chip.

[0094] Figure 4E The illustration shows a second layout of multiple functional chips on substrate 410, including a first ADC chip 401a, a first ISP chip 402a, a first memory chip 403a, a second ADC chip 401b, a second ISP chip 402b, a second memory chip 403b, and a computing chip 404.

[0095] like Figure 4E As shown, the positions and references of the first ADC chip 401a, the first ISP chip 402a, the first memory chip 403a, and the computing chip 404 are... Figure 4BThe same configuration is described, but the second ADC chip 401b is disposed along the fourth edge of the substrate 410 opposite to the second edge, the second ISP chip 402b is disposed on the side of the second ADC chip 401b facing the center of the substrate 410, and the second memory chip 403b is disposed along the third edge of the substrate 410 opposite to the first edge. The hybrid bonding of the first wiring layer and the second wiring layer also enables the second ADC chip 401b to be electrically connected to the pixel array.

[0096] Among them, the electrical connections and references between multiple functional chips 401a-403a, 401b-403b and 404 Figure 4D The descriptions are the same.

[0097] In such Figure 4E In the layout shown, besides the reference Figure 4A The described method can shorten the length of the electrical connection between the pixel array and the first ADC chip 401a, and the electrical connection between the first ADC chip 401a and the first ISP chip 402a. Setting the second ADC chip 401b along the fourth edge of the substrate 410 will shorten the length of the electrical connection between the pixel array and the second ADC chip 401b. Since the second ISP chip 402b receives signals from the second ADC chip 401b, setting the second ISP chip 402b on both sides of the second ADC chip 401b will shorten the length of the electrical connection between the second ADC chip 401b and the second ISP chip 402b. Since the computing chip 404, which interacts with the first ISP chip 402a, the second ISP chip 402b, the first memory chip 403a, and the second memory chip 403b, is located at the center of the substrate, the length of the electrical connection between the computing chip 404 and the first ISP chip 402a, the second ISP chip 402b, the first memory chip 403a, and the second memory chip 403b can be shortened.

[0098] To avoid crosstalk between high-speed and low-speed signals, the distance between high-speed signal electrical connections and the distance between a high-speed signal electrical connection and each low-speed signal electrical connection can be set to be greater than the distance between low-speed signal electrical connections.

[0099] According to some embodiments, for electrical connections in the first wiring layer, the electrical connection between the computing chip and the first memory chip and the electrical connection between the computing chip and the second memory chip are high-speed signal electrical connections, and the remaining electrical connections in the first wiring layer are low-speed signal electrical connections. The distance between each high-speed signal electrical connection and the distance between each high-speed signal electrical connection and each low-speed signal electrical connection is greater than a first distance threshold, and the distance between each low-speed signal electrical connection is greater than a second distance threshold. The first distance threshold is greater than the second distance threshold.

[0100] In such Figure 4D and Figure 4E In the example shown, the electrical connections between computing chip 404 and the first memory chip 403a and the second memory chip 403b are high-speed signal connections, while the electrical connections between the first ADC chip 401a and the first ISP chip 402a, the first ISP chip 402a and the first memory chip 403a, the first ISP chip 402a and the computing chip 404, the second ADC chip 401b and the second ISP chip 402b, the second ISP chip 402b and the second memory chip 403b, and the second ISP chip 402b and the computing chip 404 are low-speed signal connections.

[0101] For example, in Figure 4D and Figure 4E In the example shown, the distance between the electrical connection between the computing chip 404 and the first memory chip 403a and the electrical connection between the first ISP chip 402a and the first memory chip 403a can be set to be greater than the distance between the electrical connection between the first ADC chip 401a and the first ISP chip 402a and the electrical connection between the first ISP chip 402a and the first memory chip 403a. Similarly, the distance between the electrical connection between the computing chip 404 and the first memory chip 403a and the electrical connection between the computing chip 404 and the second memory chip 403b can be set to be greater than the distance between the electrical connection between the first ADC chip 401a and the first ISP chip 402a and the electrical connection between the first ISP chip 402a and the first memory chip 403a.

[0102] According to some embodiments, the parallel trace length between each high-speed signal electrical connection and the parallel trace length between each high-speed signal electrical connection and each low-speed signal electrical connection are less than a first length threshold, and the parallel trace length between each low-speed signal electrical connection is less than a second length threshold, wherein the first length threshold is less than the second length threshold.

[0103] To further avoid crosstalk between high-speed and low-speed signals, the length of parallel traces between high-speed signals and between high-speed signal electrical connections and each low-speed signal electrical connection can be set to be less than the length of parallel traces between low-speed signal electrical connections.

[0104] For example, in Figure 4D and Figure 4EIn the example shown, the parallel trace lengths between the electrical connections between the computing chip 404 and the first memory chip 403a, and between the first ISP chip 402a and the first memory chip 403a, can be set to be less than the parallel trace lengths between the electrical connections between the first ADC chip 401a and the first ISP chip 402a, and between the first ISP chip 402a and the first memory chip 403a. Furthermore, the parallel trace lengths between the electrical connections between the computing chip 404 and the first memory chip 403a, and between the computing chip 404 and the second memory chip 403b, can be set to be less than the parallel trace lengths between the electrical connections between the first ADC chip 401a and the first ISP chip 402a, and between the first ISP chip 402a and the first memory chip 403a.

[0105] To further avoid crosstalk between high-speed and low-speed signals, shielded ground wires can be installed on both sides of each high-speed signal electrical connection.

[0106] According to some embodiments, the first wiring layer further includes: a shielded ground wire disposed on both sides of each high-speed signal electrical connection.

[0107] For example, in such Figure 4D and Figure 4E In the example shown, shielded ground wires can be provided on both sides of the electrical connection between computing chip 404 and the first memory chip 403a and the electrical connection between computing chip 404 and the second memory chip 403b.

[0108] According to some embodiments, the plurality of functional chips include a first ADC chip, a first ISP chip, and a first memory chip, wherein the first memory chip is disposed at the center of the substrate.

[0109] Figure 5A The illustration shows a configuration on substrate 510 with multiple functional chips including a first ADC chip 501a, a first ISP chip 502a, and a first memory chip 503a, with the first memory chip positioned at the center of the substrate.

[0110] like Figure 5A As shown, the first ADC chip 501a is disposed along the first edge of the substrate 510, the first ISP chip 502a is disposed on the side of the first ADC chip 501a facing the center of the substrate 510, and the first memory chip 503a is disposed at the center of the substrate 510.

[0111] The first ADC chip 501a receives analog image signals from the pixel array and transmits the converted digital image signals to the first ISP chip 502a; the first ISP chip 502a receives digital image signals from the first ADC chip 501a and reads data stored in the first memory chip 503a to perform image processing, and stores the received digital image signals or processed data in the first memory chip 503a.

[0112] In such Figure 5A In the illustrated layout, since the output pins of the pixel array are typically located at the edge of the pixel array, placing the first ADC chip 501a along the first edge of the substrate 510 will shorten the length of the electrical connection between the pixel array and the first ADC chip 501a. Furthermore, since the first ISP chip 502a receives signals from the first ADC chip 501a, placing the first ISP chip 502a on one side of the first ADC chip 501a will shorten the length of the electrical connection between the first ADC chip 501a and the first ISP chip 502a. Shortening the length of the electrical connection helps reduce signal crosstalk and achieves efficient signal transmission.

[0113] According to some embodiments, the first memory chip is disposed at the center of the substrate, and the plurality of functional chips further include: a first computing chip disposed along a second edge of the substrate adjacent to the first edge, wherein the first wiring layer further includes: an electrical connection between the first ISP chip and the first computing chip; and an electrical connection between the first computing chip and the first memory chip.

[0114] Figure 5B The illustration shows a combination of multiple functional chips on substrate 510, including a first ADC chip 501a, a first ISP chip 502a, a first memory chip 503a, and a first computing chip 504a.

[0115] like Figure 5B As shown, the positions and references of the first ADC chip 501a, the first ISP chip 502a, and the first memory chip 503a are... Figure 5A The same as described, except that the first computing chip 504a is disposed along the second edge of the substrate 510 adjacent to the first edge.

[0116] The first ADC chip 501a receives an analog image signal from the pixel array and transmits the converted digital image signal to the first ISP chip 502a. The first ISP chip 502a receives the digital image signal from the first ADC chip 501a and reads the data stored in the first storage chip 503a to perform image processing, and stores the received digital image signal or the processed data in the first storage chip 503a. The first computing chip 504a receives the processed signal from the first ISP chip 502a and reads the data stored in the first storage chip 503a to perform further image processing, and stores the data corresponding to the processed signal in the first storage chip 503a.

[0117] In such Figure 5B In the layout shown, besides the reference Figure 5A The described method can shorten the length of the electrical connection between the pixel array and the first ADC chip 501a and the electrical connection between the first ADC chip 501a and the first ISP chip 502a. Since the first computing chip 504a is placed at the edge of the substrate 510, it is beneficial to dissipate the heat generated by the first computing chip 504a and avoid local overheating of the image sensor, which would affect the imaging uniformity of the pixel array.

[0118] According to some embodiments, the plurality of functional chips further include: a second ADC chip disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second ADC chip to be electrically connected to the pixel array; and a second ISP chip disposed on the side of the second ADC chip facing the center of the substrate, wherein the first wiring layer further includes: an electrical connection between the second ADC chip and the second ISP chip; an electrical connection between the second ISP chip and the first computing chip; and an electrical connection between the second ISP chip and the first memory chip.

[0119] Figure 5C The illustration shows a configuration of multiple functional chips on substrate 510, including a first ADC chip 501a, a first ISP chip 502a, a first memory chip 503a, a second ADC chip 501b, a second ISP chip 502b, and a first computing chip 504a.

[0120] like Figure 5C As shown, the positions and references of the first ADC chip 501a, the first ISP chip 502a, the first memory chip 503a, and the first computing chip 504a are... Figure 5BThe same configuration is described, but the second ADC chip 501b is disposed along the third edge of the substrate 510 opposite to the first edge, and the second ISP chip 502b is disposed on the side of the second ADC chip 501b facing the center of the substrate 510. The hybrid bonding of the first wiring layer and the second wiring layer also enables the second ADC chip 501b to be electrically connected to the pixel array.

[0121] The first ADC chip 501a and the second ADC chip 501b receive analog image signals from the pixel array and transmit the converted digital image signals to the first ISP chip 502a and the second ISP chip 502b, respectively. The first ISP chip 502a receives the digital image signals from the first ADC chip 501a and reads data stored in the first storage chip 503a for image processing, and stores the received digital image signals or processed data in the first storage chip 503a. The second ISP chip 502b receives the digital image signals from the second ADC chip 501b and reads data stored in the first storage chip 503a for image processing, and stores the received digital image signals or processed data in the first storage chip 503a. The first computing chip 504a receives the processed signals from the first ISP chip 502a and the second ISP chip 502b, reads data stored in the first storage chip 503a for further image processing, and stores the data corresponding to the processed signals in the first storage chip 503a.

[0122] In such Figure 5C In the layout shown, besides the reference Figure 5B The described method can shorten the length of the electrical connection between the pixel array and the first ADC chip 501a, and the electrical connection between the first ADC chip 501a and the first ISP chip 502a, and improve the heat dissipation of the first computing chip 504a. Since the output pins of the pixel array are usually located at the edge of the pixel array, placing the second ADC chip 501b along the third edge of the substrate 510 will shorten the length of the electrical connection between the pixel array and the second ADC chip 501b. Since the second ISP chip 502b receives signals from the second ADC chip 501b, placing the second ISP chip 502b on one side of the second ADC chip 501b will shorten the length of the electrical connection between the second ADC chip 501b and the second ISP chip 502b. Since the first memory chip 503a, which interacts with the first ISP chip 502a, the second ISP chip 502b, and the first computing chip 504a, is located at the center of the substrate 510, the length of the electrical connection between the first memory chip 503a and the first ISP chip 502a, the second ISP chip 502b, and the first computing chip 504a can be shortened.

[0123] According to some embodiments, the plurality of functional chips further include: a second ADC chip disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second ADC chip to be electrically connected to the pixel array; a second ISP chip disposed on a side of the second ADC chip facing the center of the substrate; and a second computing chip disposed along a fourth edge of the substrate opposite to the second edge; wherein the first wiring layer further includes: an electrical connection between the second ADC chip and the second ISP chip; an electrical connection between the second ISP chip and the first memory chip; an electrical connection between the second ISP chip and the second computing chip; and an electrical connection between the first memory chip and the second computing chip.

[0124] Figure 5D The illustration shows a first layout of multiple functional chips on substrate 510, including a first ADC chip 501a, a first ISP chip 502a, a first memory chip 503a, a second ADC chip 501b, a second ISP chip 502b, a first computing chip 504a, and a second computing chip 504b.

[0125] like Figure 5D As shown, the positions and references of the first ADC chip 501a, the first ISP chip 502a, the first memory chip 503a, and the first computing chip 504a are... Figure 5B The same configuration is described, but the second ADC chip 501b is disposed along the third edge of the substrate 510 opposite to the first edge, the second ISP chip 502b is disposed on the side of the second ADC chip 501b facing the center of the substrate 510, and the second computing chip 504b is disposed along the fourth edge of the substrate 510 opposite to the second edge. The hybrid bonding of the first wiring layer and the second wiring layer also enables the second ADC chip 501b to be electrically connected to the pixel array.

[0126] The first ADC chip 501a and the second ADC chip 501b receive analog image signals from the pixel array and transmit the converted digital image signals to the first ISP chip 502a and the second ISP chip 502b, respectively. The first ISP chip 502a receives the digital image signals from the first ADC chip 501a and reads data stored in the first memory chip 503a for image processing, and stores the received digital image signals or processed data in the first memory chip 503a. The second ISP chip 502b receives the digital image signals from the second ADC chip 501b and reads data stored in the first memory chip 503a. The first computing chip 504a receives the processed signal from the first ISP chip 502a and reads the data stored in the first storage chip 503a for further image processing, and stores the data corresponding to the processed signal in the first storage chip 503a; the second computing chip 504b receives the processed signal from the second ISP chip 502b and reads the data stored in the first storage chip 503a for further image processing, and stores the data corresponding to the processed signal in the first storage chip 503a.

[0127] In such Figure 5D In the layout shown, besides the reference Figure 5C The described method can shorten the length of the electrical connections between the pixel array and the first ADC chip 501a, the first ADC chip 501a and the first ISP chip 502a, the pixel array and the second ADC chip 501b, and the second ADC chip 501b and the second ISP chip 502b, and improve the heat dissipation of the first computing chip 504a. Since the second computing chip 504b is also disposed at the edge of the substrate 510, the heat dissipation of the second computing chip 504a can be improved. Furthermore, since the first memory chip 503a, which interacts with all four of the first ISP chips 502a, the second ISP chip 502b, the first computing chip 504a, and the second computing chip 504b, is disposed at the center of the substrate 510, the length of the electrical connections between the first memory chip 503a and the first ISP chips 502a, the second ISP chip 502b, the first computing chip 504a, and the second computing chip 504b can be shortened.

[0128] According to some embodiments, the plurality of functional chips further include: a second ADC chip disposed along a fourth edge of the substrate opposite to the second edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second ADC chip to be electrically connected to the pixel array; a second ISP chip disposed on a side of the second ADC chip facing the center of the substrate; and a second computing chip disposed along a third edge of the substrate opposite to the first edge; wherein the first wiring layer further includes: an electrical connection between the second ADC chip and the second ISP chip; an electrical connection between the second ISP chip and the first memory chip; an electrical connection between the second ISP chip and the second computing chip; and an electrical connection between the first memory chip and the second computing chip.

[0129] Figure 5E A second layout is shown when multiple functional chips on substrate 510 include a first ADC chip 501a, a first ISP chip 502a, a first memory chip 503a, a second ADC chip 501b, a second ISP chip 502b, a first computing chip 504a, and a second computing chip 504b.

[0130] like Figure 5E As shown, the positions and references of the first ADC chip 501a, the first ISP chip 502a, the first memory chip 503a, and the first computing chip 504a are... Figure 5B The same configuration is described, but the second ADC chip 501b is disposed along the fourth edge of the substrate 510 opposite to the second edge, the second ISP chip 502b is disposed on the side of the second ADC chip 501b facing the center of the substrate 510, and the second computing chip 504b is disposed along the third edge of the substrate 510 opposite to the first edge. The hybrid bonding of the first wiring layer and the second wiring layer also enables the second ADC chip 501b to be electrically connected to the pixel array.

[0131] Among them, the electrical connections and references between multiple functional chips 501a-504a, 501b-502b and 504b Figure 5D The descriptions are the same.

[0132] In such Figure 5E In the layout shown, compared with the reference Figure 5D Similar descriptions, except as in the reference Figure 5CThe described method can shorten the length of the electrical connections between the pixel array and the first ADC chip 501a, the first ADC chip 501a and the first ISP chip 502a, the pixel array and the second ADC chip 501b, and the second ADC chip 501b and the second ISP chip 502b, and improve the heat dissipation of the first computing chip 504a. Since the second computing chip 504b is also disposed at the edge of the substrate 510, the heat dissipation of the second computing chip 504a can be improved. Furthermore, since the first memory chip 503a, which interacts with all four of the first ISP chips 502a, the second ISP chip 502b, the first computing chip 504a, and the second computing chip 504b, is disposed at the center of the substrate 510, the length of the electrical connections between the first memory chip 503a and the first ISP chips 502a, the second ISP chip 502b, the first computing chip 504a, and the second computing chip 504b can be shortened.

[0133] According to exemplary embodiments of the present disclosure, the present disclosure also provides a semiconductor package including an image sensor as described in the present disclosure.

[0134] Although this disclosure has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration should be considered illustrative and suggestive, not restrictive; this disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure, and the appended claims, those skilled in the art will be able to understand and implement variations of the disclosed embodiments in practice with respect to the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "a plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be beneficial.

Claims

1. An image sensor, comprising: A substrate, the substrate including a plurality of functional chips integrated onto a first surface of the substrate, wherein the plurality of functional chips include: A first analog-to-digital converter chip is disposed along a first edge of the substrate; A first image signal processing chip is disposed on the side of the first analog-to-digital converter chip facing the center of the substrate; The first memory chip; and A computing chip, wherein the first memory chip is disposed along a second edge of the substrate adjacent to the first edge and the computing chip is disposed at the center of the substrate, or the first memory chip is disposed at the center of the substrate and the computing chip is disposed along a second edge of the substrate adjacent to the first edge; A first wiring layer is formed on the plurality of functional chips, wherein the first wiring layer includes: Electrical connection between the first analog-to-digital converter chip and the first image signal processing chip; The electrical connection between the first image signal processing chip and the first memory chip; The electrical connection between the first image signal processing chip and the computing chip; and The electrical connection between the computing chip and the first storage chip; Pixel array; and A second wiring layer is formed on the surface of the pixel array that is away from the light incident surface. The first wiring layer and the second wiring layer are hybrid bonded, so that the first analog-to-digital converter chip is electrically connected to the pixel array.

2. The image sensor as claimed in claim 1, wherein, The first memory chip is disposed along the second edge of the substrate adjacent to the first edge, and the computing chip is disposed at the center of the substrate.

3. The image sensor as described in claim 2, wherein, The plurality of functional chips also include: A second analog-to-digital converter chip is disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second analog-to-digital converter chip to be electrically connected to the pixel array; and The second image signal processing chip is disposed on the side of the second analog-to-digital converter chip facing the center of the substrate. The first wiring layer further includes: Electrical connection between the second analog-to-digital converter chip and the second image signal processing chip; The electrical connection between the second image signal processing chip and the computing chip; and Electrical connection between the second image signal processing chip and the first memory chip.

4. The image sensor as described in any one of claims 2-3, wherein, For the electrical connections in the first wiring layer, the electrical connection between the computing chip and the first memory chip is a high-speed signal electrical connection, while the remaining electrical connections in the first wiring layer are low-speed signal electrical connections. Wherein, the distance between the high-speed signal electrical connection and each low-speed signal electrical connection is greater than a first distance threshold, and the distance between each low-speed signal electrical connection is greater than a second distance threshold, wherein the first distance threshold is greater than the second distance threshold.

5. The image sensor as claimed in claim 4, wherein, The parallel trace length between the high-speed signal electrical connection and each low-speed signal electrical connection is less than a first length threshold, and the parallel trace length between each low-speed signal electrical connection is less than a second length threshold, wherein the first length threshold is less than the second length threshold.

6. The image sensor as claimed in claim 4, wherein, The first wiring layer further includes: shielded ground wires disposed on both sides of the high-speed signal electrical connection.

7. The image sensor as described in claim 2, wherein, The plurality of functional chips also include: A second analog-to-digital converter chip is disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second analog-to-digital converter chip to be electrically connected to the pixel array. The second image signal processing chip is disposed on the side of the second analog-to-digital converter chip facing the center of the substrate. The second memory chip is disposed along the fourth edge of the substrate opposite to the second edge; The first wiring layer further includes: Electrical connection between the second analog-to-digital converter chip and the second image signal processing chip; Electrical connection between the second image signal processing chip and the computing chip; The electrical connection between the second image signal processing chip and the second memory chip; and The electrical connection between the computing chip and the second storage chip.

8. The image sensor as described in claim 2, wherein, The plurality of functional chips also include: A second analog-to-digital converter chip is disposed along a fourth edge of the substrate opposite to the second edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second analog-to-digital converter chip to be electrically connected to the pixel array; The second image signal processing chip is disposed on the side of the second analog-to-digital converter chip facing the center of the substrate. A second memory chip is disposed along a third edge of the substrate opposite to the first edge; The first wiring layer further includes: Electrical connection between the second analog-to-digital converter chip and the second image signal processing chip; Electrical connection between the second image signal processing chip and the computing chip; The electrical connection between the second image signal processing chip and the second memory chip; and The electrical connection between the computing chip and the second storage chip.

9. The image sensor as claimed in any one of claims 7-8, wherein, For the electrical connections in the first wiring layer, the electrical connections between the computing chip and the first memory chip, and between the computing chip and the second memory chip, are high-speed signal connections; the remaining electrical connections in the first wiring layer are low-speed signal connections. Wherein, the distance between each high-speed signal electrical connection and the distance between each high-speed signal electrical connection and each low-speed signal electrical connection are greater than a first distance threshold, and the distance between each low-speed signal electrical connection is greater than a second distance threshold, wherein the first distance threshold is greater than the second distance threshold.

10. The image sensor of claim 9, wherein, The parallel trace lengths between each high-speed signal electrical connection and between each high-speed signal electrical connection and each low-speed signal electrical connection are less than a first length threshold, and the parallel trace lengths between each low-speed signal electrical connection are less than a second length threshold, wherein the first length threshold is less than the second length threshold.

11. The image sensor as claimed in claim 9, wherein, The first wiring layer also includes: a shielded ground wire disposed on both sides of each high-speed signal electrical connection.

12. The image sensor as claimed in any one of claims 2-3 and 7-8, wherein, The computing chip is an artificial intelligence chip and / or an FPGA chip.

13. The image sensor as claimed in claim 1, wherein, The first memory chip is disposed at the center of the substrate, and the computing chip is disposed along a second edge of the substrate adjacent to the first edge, wherein the computing chip is a first computing chip.

14. The image sensor as described in claim 13, wherein, The plurality of functional chips also include: A second analog-to-digital converter chip is disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second analog-to-digital converter chip to be electrically connected to the pixel array; and The second image signal processing chip is disposed on the side of the second analog-to-digital converter chip facing the center of the substrate. The first wiring layer further includes: Electrical connection between the second analog-to-digital converter chip and the second image signal processing chip; The electrical connection between the second image signal processing chip and the first computing chip; and Electrical connection between the second image signal processing chip and the first memory chip.

15. The image sensor as described in claim 13, wherein, The plurality of functional chips also include: A second analog-to-digital converter chip is disposed along a third edge of the substrate opposite to the first edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second analog-to-digital converter chip to be electrically connected to the pixel array. The second image signal processing chip is disposed on the side of the second analog-to-digital converter chip facing the center of the substrate. A second computing chip is disposed along a fourth edge of the substrate opposite to the second edge; The first wiring layer further includes: Electrical connection between the second analog-to-digital converter chip and the second image signal processing chip; Electrical connection between the second image signal processing chip and the first memory chip; The electrical connection between the second image signal processing chip and the second computing chip; and Electrical connection between the first memory chip and the second computing chip.

16. The image sensor as claimed in claim 13, wherein, The plurality of functional chips also include: A second analog-to-digital converter chip is disposed along a fourth edge of the substrate opposite to the second edge, wherein the hybrid bonding of the first wiring layer and the second wiring layer further enables the second analog-to-digital converter chip to be electrically connected to the pixel array; The second image signal processing chip is disposed on the side of the second analog-to-digital converter chip facing the center of the substrate. A second computing chip is disposed along a third edge of the substrate opposite to the first edge; The first wiring layer further includes: Electrical connection between the second analog-to-digital converter chip and the second image signal processing chip; Electrical connection between the second image signal processing chip and the first memory chip; The electrical connection between the second image signal processing chip and the second computing chip; and Electrical connection between the first memory chip and the second computing chip.

17. The image sensor according to any one of claims 1-3, 7-8, and 13-16, wherein, The plurality of functional chips are disposed on the first surface of the substrate, and wherein the substrate further includes: A filler is formed on a first surface of the substrate to fill the gaps between each of the plurality of functional chips and to expose the pads of the plurality of functional chips.

18. The image sensor as claimed in any one of claims 1-3, 7-8, and 13-16, wherein, The image sensor also includes: A color filter is formed above the light incident surface of the pixel array; Microlenses are formed above the color filter.

19. The image sensor according to any one of claims 1-3, 7-8, and 13-16, wherein, The multiple functional chips are chips manufactured using various processes.

20. The image sensor according to any one of claims 1-3, 7-8, and 13-16, wherein, The aforementioned functional chips are verified chips.

21. A semiconductor package comprising an image sensor as claimed in any one of claims 1-20.

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