A bias voltage circuit and gain-enhanced operational amplifier

Abstract

The present invention provides a bias voltage circuit and a gain-enhanced operational amplifier, comprising: a main amplifier circuit and an auxiliary amplifier circuit. The main amplifier circuit comprises: a signal input circuit for receiving an input signal Vip and an input signal Vin; a cascode transistor for increasing output resistance, comprising: a first cascode stage and a second cascode stage; the first cascode stage is connected to the input signal Vip, and the second cascode stage is connected to the input signal Vin; a current mirror circuit for mirroring the current of the first cascode stage to the second cascode stage; a tail current source circuit connected between the signal input circuit and a ground terminal for providing a tail current source for the signal input circuit; a bias circuit for providing a bias voltage for the cascode transistor and the auxiliary amplifier circuit; and the auxiliary amplifier circuit for providing a bias voltage for the second cascode stage to increase the DC gain of the operational amplifier. The present invention is suitable for the field of semiconductor integrated circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a bias voltage circuit and a gain-enhanced operational amplifier. Background Art

[0002] The pipeline ADC has the characteristics of high speed and high precision. Its speed and precision are mainly determined by the operational amplifier set on it, so in the pipeline ADC, the operational amplifier becomes the most important module.

[0003] For a 12-bit precision ADC, the operational amplifier's gain must be at least 80dB, which is difficult to achieve with a single-stage operational amplifier. If a two-stage operational amplifier is used, frequency compensation is required. The operational amplifier's sub-pole is located at the output point, and the ADC sampling capacitor connected to the input point limits the position of the sub-pole, thereby affecting loop stability. If the sub-pole is pushed higher by increasing the transconductance of the second-stage amplifier tube, power consumption will increase, causing the two-stage operational amplifier to compromise between speed and power consumption. However, adding an auxiliary operational amplifier for gain-boosting allows a single-stage amplifier to easily achieve a high gain of more than 100dB while maintaining good stability.

[0004] Pipeline ADCs often use fully differential operational amplifiers (such as Figure 1 ) to provide better common-mode noise suppression performance for the ADC, but the fully differential operational amplifier requires a common-mode feedback circuit to stabilize the output common-mode voltage of the operational amplifier, which increases the circuit complexity; and the sampling and holding circuit of the differential input ADC is also doubled compared to the single-ended structure, which increases the area and complexity of the layout. Summary of the Invention

[0005] In view of the deficiencies in the related art, the technical problem to be solved by the present invention is to provide a bias voltage circuit and a gain-enhanced operational amplifier with a simple circuit structure and high stability.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A bias circuit comprising:

[0008] An input matching circuit, connected to the input signal Vip, for matching the signal input circuit of the operational amplifier;

[0009] A reference current source, used to generate a reference current Iin;

[0010] The bias voltage generating circuit is configured to generate a bias voltage VBN based on the reference current Iin; and to generate a bias voltage VBPC, a bias voltage VBNC, a bias voltage VB11, and a bias voltage VB21 based on the bias voltage VBN.

[0011] Preferably, the bias voltage generating circuit includes:

[0012] A first bias voltage output circuit, configured to generate a bias voltage VBN based on a reference current Iin;

[0013] The second bias voltage output circuit is used to form two current source circuits based on the bias voltage VBN, generate the bias voltage VBPC based on the first current source circuit, and generate the bias voltage VBNC, the bias voltage VB11, and the bias voltage VB21 based on the second current source circuit.

[0014] Preferably, the input matching circuit includes: MOS transistors MN4, MOS transistors MN5, and MOS transistors MN6; the first bias voltage output circuit includes: MOS transistor MN1; the second bias voltage output circuit includes: MOS transistors MN2, MOS transistors MN3, MOS transistors MP4, and MOS transistors MN8;

[0015] The gates of the MOS transistor MN4, MOS transistor MN5 and MOS transistor MN6 are all connected to the input signal Vip;

[0016] The reference current Iin generated by the reference current source is connected to the gate of the MOS transistor MN1, the drain of the MOS transistor MN4 and then to the output end of the bias voltage VBN;

[0017] The bias voltage VBN is connected to the gate of the MOS transistor MN2 and the gate of the MOS transistor MN3. The source of the MOS transistor MN2 is connected in parallel to the source of the MOS transistor MN1 and the source of the MOS transistor MN3 and then grounded.

[0018] The drain of the MOS transistor MN2 is connected to the source of the MOS transistor MN5. The drain of the MOS transistor MN5 is connected in parallel to the gate of the MOS transistor MP6, the gate of the MOS transistor MP5, the gate of the MOS transistor MP4, and one end of the resistor Rc, and then connected to the output end of the bias voltage VBPC. The source of the MOS transistor MP6 is connected to the drain of the MOS transistor MP1. The gate of the MOS transistor MP1 is connected in parallel to the gate of the MOS transistor MP2, the gate of the MOS transistor MP3, the drain of the MOS transistor MP6, and the other end of the resistor Rc, and then connected to the output end of the bias voltage VBP. The source of the MOS transistor MP1 is connected in parallel to the source of the MOS transistor MP2 and the source of the MOS transistor MP3, and then connected to the power supply voltage VDD.

[0019] The drain of the MOS transistor MN3 is connected in parallel to the source of the MOS transistor MN6 and the source of the MOS transistor MN7. The drain of the MOS transistor MN6 is connected to the drain of the MOS transistor MP5. The source of the MOS transistor MP5 is connected to the drain of the MOS transistor MP2.

[0020] The gate of the MOS transistor MN7 is connected in parallel to the gate of the MOS transistor MN8, the drain of the MOS transistor MN8, and the drain of the MOS transistor MP4, and then connected to the output end of the bias voltage VBNC. The drain of the MOS transistor MN7 is connected in parallel to the source of the MOS transistor MN8, and then connected to the output end of the bias voltage VB21.

[0021] The source of the MOS transistor MP4 is connected in parallel to the drain of the MOS transistor MP3 and then to the output end of the bias voltage VB11.

[0022] Accordingly, a gain-boosting operational amplifier comprises: a main amplifying circuit and an auxiliary amplifying circuit (20);

[0023] The main amplifying circuit comprises:

[0024] A signal input circuit, used for receiving an input signal Vip and an input signal Vin;

[0025] A cascode transistor, used to increase output resistance to increase the gain of the main amplifier circuit, comprising: a first cascode stage and a second cascode stage; the first cascode stage is connected to the signal input circuit, and the second cascode stage is connected to the signal input circuit;

[0026] a current mirror circuit for mirroring the current of the first cascode stage to the second cascode stage;

[0027] A tail current source circuit is connected between the signal input circuit and the ground terminal, and is used to provide a tail current source for the signal input circuit;

[0028] A bias circuit, which is the bias circuit described above, is used to provide a bias voltage for the cascode transistor and the auxiliary amplifier circuit;

[0029] The auxiliary amplifier circuit is used to provide a bias voltage for the second cascode stage to increase the DC gain of the operational amplifier.

[0030] Preferably, the signal input circuit includes: a MOS transistor MN11 and a MOS transistor MN12; the first cascode stage includes: a MOS transistor MN9 and a MOS transistor MP7; the second cascode stage includes: a MOS transistor MN10 and a MOS transistor MP8; the current mirror circuit includes: a MOS transistor MP9 and a MOS transistor MP10 that are mirror images of each other; the auxiliary amplifier circuit includes: an auxiliary amplifier AMP1 and an auxiliary amplifier AMP2;

[0031] The gates of the MOS transistor MN11 and the MOS transistor MN12 are connected to the input signal Vip and the input signal Vin, respectively. The drain of the MOS transistor MN11 is connected to the source of the MOS transistor MN9 of the first cascode stage, and the drain of the MOS transistor MN12 is connected to the source of the MOS transistor MN10 of the second cascode stage. The source of the MOS transistor MN11 is connected in parallel to the source of the MOS transistor MN12 and then to the tail current source circuit.

[0032] The drain of the MOS transistor MN9 is connected in parallel to the drain of the MOS transistor MP7 and then to the gate of the MOS transistor MP9 and the gate of the MOS transistor MP10; the source of the MOS transistor MP7 is connected to the drain of the MOS transistor MP9, the gate of the MOS transistor MN9 is connected to the bias voltage VBNC of the bias circuit, and the gate of the MOS transistor MP7 is connected to the bias voltage VBPC of the bias circuit;

[0033] The source of the MOS transistor MP9 is connected in parallel to the source of the MOS transistor MP10 and then connected to the power supply voltage VDD;

[0034] The drain of the MOS transistor MN10 is connected in parallel to the drain of the MOS transistor MP8 and then connected to the single-ended signal output terminal Out of the operational amplifier;

[0035] The source of the MOS transistor MN10 is connected to the inverting input terminal of the auxiliary amplifier AMP2, and the output terminal of the auxiliary amplifier AMP2 is connected to the gate of the MOS transistor MN10. The source of the MOS transistor MP8 is connected in parallel to the drain of the MOS transistor MP10 and then to the inverting input terminal of the auxiliary amplifier AMP1, and the output terminal of the auxiliary amplifier AMP1 is connected to the gate of the MOS transistor MP8.

[0036] The non-inverting input terminal of the auxiliary amplifier AMP1 is connected to the bias voltage VB11 of the auxiliary amplifier AMP1 , and the non-inverting input terminal of the auxiliary amplifier AMP2 is connected to the bias voltage VB21 of the auxiliary amplifier AMP2 .

[0037] Preferably, the bias voltage VB11 of the auxiliary amplifier AMP1 is connected to the source of the MOS transistor MP7 , and the bias voltage VB21 of the auxiliary amplifier AMP2 is connected to the source of the MOS transistor MN9 .

[0038] The beneficial technical effects of the present invention are:

[0039] 1. The bias voltage circuit and gain-enhanced operational amplifier provided by the present invention are single-ended output operational amplifiers. Compared with traditional fully differential operational amplifiers, they reduce the common-mode feedback circuit, simplify the circuit, and are extremely practical.

[0040] 2. The bias circuit proposed in the present invention can bias the non-inverting input terminals of the auxiliary amplifiers AMP1 and AMP2, ensuring the outputs of the auxiliary amplifiers AMP1 and AMP2, and providing a suitable bias voltage for the second cascode stage, thereby enabling the operational amplifier to have greater gain and bandwidth performance.

[0041] 3. In the present invention, the source output voltages of the MOS transistors MP7 and MN9 are used to bias the non-inverting input terminals of the auxiliary amplifiers AMP1 and AMP2. Since the MOS transistors MP7 and MN9 are relatively large, they can be well matched with the MOS transistors MN10 and MP8 in the layout, avoiding deviations caused by the manufacturing process, thereby providing a more stable bias voltage for the operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a schematic diagram of the structure of a fully differential operational amplifier in the prior art;

[0043] Figure 2 is a circuit schematic diagram of a bias circuit provided by the present invention;

[0044] Figure 3 1 is a schematic structural diagram of a gain-boosted operational amplifier provided in the first embodiment of the present invention;

[0045] Figure 4 1 is a schematic structural diagram of a gain-boosted operational amplifier provided in a second embodiment of the present invention;

[0046] Figure 5 1 is a schematic diagram of the power supply rejection ratio (PSRR) simulation results of the two solutions of Example 1 and Example 2;

[0047] In the picture:

[0048] 101 is a signal input circuit, 102 is a common-source common-gate transistor, 103 is a current mirror circuit, 104 is a tail current source circuit, 105 is a bias circuit; 20 is an auxiliary amplifier circuit.

[0049] 1051 is an input matching circuit, 1052 is a reference current source, and 1053 is a bias voltage generating circuit;

[0050] 10531 is a first bias voltage output circuit, and 10532 is a second bias voltage output circuit. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0052] Next, the present invention is described in detail with reference to schematic diagrams. For ease of illustration, when describing embodiments of the present invention, cross-sectional views illustrating device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0053] An embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0054] Example 1

[0055] like Figure 2 As shown, a bias circuit includes:

[0056] An input matching circuit 1051 is connected to the input signal Vip and is used to match the signal input circuit of the operational amplifier;

[0057] A reference current source 1052 for generating a reference current Iin;

[0058] The bias voltage generating circuit 1053 is configured to generate a bias voltage VBN based on the reference current Iin; and to generate a bias voltage VBPC, a bias voltage VBNC, a bias voltage VB11, and a bias voltage VB21 based on the bias voltage VBN.

[0059] In this embodiment, the bias voltage generating circuit 1053 includes:

[0060] A first bias voltage output circuit 10531, configured to generate a bias voltage VBN based on a reference current Iin;

[0061] The second bias voltage output circuit 10532 is used to form two current source circuits based on the bias voltage VBN, generate the bias voltage VBPC based on the first current source circuit, and generate the bias voltage VBNC, the bias voltage VB11, and the bias voltage VB21 based on the second current source circuit.

[0062] Furthermore, the input matching circuit 1051 includes: MOS transistors MN4, MOS transistors MN5, and MOS transistors MN6; the first bias voltage output circuit 10531 includes: MOS transistor MN1; the second bias voltage output circuit 10532 includes: MOS transistors MN2, MOS transistors MN3, MOS transistors MP4, and MOS transistors MN8;

[0063] The gates of the MOS transistor MN4, MOS transistor MN5 and MOS transistor MN6 are all connected to the input signal Vip;

[0064] The reference current Iin generated by the reference current source 1052 is connected to the gate of the MOS transistor MN1, the drain of the MOS transistor MN4 and then to the output end of the bias voltage VBN;

[0065] The bias voltage VBN is connected to the gate of the MOS transistor MN2 and the gate of the MOS transistor MN3. The source of the MOS transistor MN2 is connected in parallel to the source of the MOS transistor MN1 and the source of the MOS transistor MN3 and then grounded.

[0066] The drain of the MOS transistor MN2 is connected to the source of the MOS transistor MN5. The drain of the MOS transistor MN5 is connected in parallel to the gate of the MOS transistor MP6, the gate of the MOS transistor MP5, the gate of the MOS transistor MP4, and one end of the resistor Rc, and then connected to the output end of the bias voltage VBPC. The source of the MOS transistor MP6 is connected to the drain of the MOS transistor MP1. The gate of the MOS transistor MP1 is connected in parallel to the gate of the MOS transistor MP2, the gate of the MOS transistor MP3, the drain of the MOS transistor MP6, and the other end of the resistor Rc, and then connected to the output end of the bias voltage VBP. The source of the MOS transistor MP1 is connected in parallel to the source of the MOS transistor MP2 and the source of the MOS transistor MP3, and then connected to the power supply voltage VDD.

[0067] The drain of the MOS transistor MN3 is connected in parallel to the source of the MOS transistor MN6 and the source of the MOS transistor MN7. The drain of the MOS transistor MN6 is connected to the drain of the MOS transistor MP5. The source of the MOS transistor MP5 is connected to the drain of the MOS transistor MP2.

[0068] The gate of the MOS transistor MN7 is connected in parallel to the gate of the MOS transistor MN8, the drain of the MOS transistor MN8, and the drain of the MOS transistor MP4, and then connected to the output end of the bias voltage VBNC. The drain of the MOS transistor MN7 is connected in parallel to the source of the MOS transistor MN8, and then connected to the output end of the bias voltage VB21.

[0069] The source of the MOS transistor MP4 is connected in parallel to the drain of the MOS transistor MP3 and then to the output end of the bias voltage VB11.

[0070] In this embodiment, the gates of the MOS transistors MN4, MN5, and MN6 of the input matching circuit 1051 are all connected to the input signal Vip, which is the input signal of the operational amplifier, to achieve input matching between the bias circuit and the operational amplifier.

[0071] When in use, the reference current source 1052 generates a reference current Iin, which flows through the diode-connected MOS transistor MN1 to generate a bias voltage VBN;

[0072] The bias voltage VBN is connected to the gate of the MOS transistor MN2 and the gate of the MOS transistor MN3 to bias the MOS transistor MN2 and the MOS transistor MN3 to form two current source circuits;

[0073] The first current source circuit includes: MOS transistor MN2, MOS transistor MP1, and MOS transistor MP6. MOS transistor MN2 provides bias current for MOS transistors MP1 and MP6, generating a bias voltage VBP at the gate terminal of MOS transistor MP1. Resistor Rc is connected in series between the bias voltage VBP and MOS transistor MN5, generating a voltage drop to form bias voltage VBPC.

[0074] The second current source circuit includes: MOS transistors MN2, MOS transistors MN3, MOS transistors MP4, and MOS transistors MN8. A bias voltage VBNC is generated between the drain of MOS transistor MP4 and the gate of MOS transistor MP8, a bias voltage VB11 is generated at the source of MOS transistor MP4, and a bias voltage VB21 is generated at the source of MOS transistor MP8.

[0075] like Figure 3 As shown, the present invention also provides a gain-enhanced operational amplifier, comprising:

[0076] The main amplifier circuit includes:

[0077] The signal input circuit 101 is used to receive an input signal Vip and an input signal Vin;

[0078] The cascode transistor 102 is used to increase the output resistance to increase the gain of the main amplifier circuit, and includes a first cascode stage and a second cascode stage; the first cascode stage is connected to the signal input circuit 101, and the second cascode stage is connected to the signal input circuit 102;

[0079] a current mirror circuit 103 for mirroring the current of the first cascode stage to the second cascode stage;

[0080] The tail current source circuit 104 is connected between the signal input circuit 101 and the ground terminal, and is used to provide a tail current source for the signal input circuit 101;

[0081] The bias circuit 105 is the bias circuit described above, and is used to provide a bias voltage for the cascode transistor 102 and the auxiliary amplifier circuit 20;

[0082] The auxiliary amplifier circuit 20 is used to provide a bias voltage for the second cascode stage to increase the DC gain of the operational amplifier.

[0083] Specifically, the signal input circuit 101 includes: MOS transistors MN11 and MOS transistors MN12; the first cascode stage includes: MOS transistors MN9 and MOS transistors MP7; the second cascode stage includes: MOS transistors MN10 and MOS transistors MP8; the current mirror circuit 103 includes: MOS transistors MP9 and MP10 that are mirror images of each other; the auxiliary amplifier circuit 20 includes: auxiliary amplifiers AMP1 and AMP2;

[0084] The gates of the MOS transistor MN11 and the MOS transistor MN12 are connected to the input signal Vip and the input signal Vin, respectively. The drain of the MOS transistor MN11 is connected to the source of the MOS transistor MN9 of the first cascode stage, and the drain of the MOS transistor MN12 is connected to the source of the MOS transistor MN10 of the second cascode stage. The source of the MOS transistor MN11 is connected in parallel to the source of the MOS transistor MN12 and then to the tail current source circuit 104.

[0085] The drain of the MOS transistor MN9 is connected in parallel to the drain of the MOS transistor MP7 and then to the gate of the MOS transistor MP9 and the gate of the MOS transistor MP10; the source of the MOS transistor MP7 is connected to the drain of the MOS transistor MP9, the gate of the MOS transistor MN9 is connected to the bias voltage VBNC of the bias circuit 105, and the gate of the MOS transistor MP7 is connected to the bias voltage VBPC of the bias circuit 105;

[0086] The source of the MOS transistor MP9 is connected in parallel to the source of the MOS transistor MP10 and then connected to the power supply voltage VDD;

[0087] The drain of the MOS transistor MN10 is connected in parallel to the drain of the MOS transistor MP8 and then connected to the single-ended signal output terminal Out of the operational amplifier;

[0088] The source of the MOS transistor MN10 is connected to the inverting input terminal of the auxiliary amplifier AMP2, and the output terminal of the auxiliary amplifier AMP2 is connected to the gate of the MOS transistor MN10. The source of the MOS transistor MP8 is connected in parallel to the drain of the MOS transistor MP10 and then connected to the inverting input terminal of the auxiliary amplifier AMP1, and the output terminal of the auxiliary amplifier AMP1 is connected to the gate of the MOS transistor MP8. The non-inverting input terminal of the auxiliary amplifier AMP1 is connected to the bias voltage VB11 of the auxiliary amplifier AMP1, and the non-inverting input terminal of the auxiliary amplifier AMP2 is connected to the bias voltage VB21 of the auxiliary amplifier AMP2.

[0089] In this embodiment, MOS transistors MP1 and MP2 form a current mirror, so that the current flowing through MOS transistor MP2 is the same as the current flowing through MOS transistor MP1. After this current flows through MOS transistor MN6, the voltage at point A can be determined. After the voltage at point A is determined, a bias voltage VBNC is generated as the bias voltage of MOS transistor MN9 in the main amplifier circuit of the operational amplifier.

[0090] like Figure 2 、 Figure 3 As shown, due to Figure 2 MOS tube MN6 and Figure 3 The MOS tube MN11 in the circuit has the same Vgs voltage, so Figure 2 The voltage at point A is Figure 3 The voltage at point B is the same or close to that at point A; in this embodiment, the bias circuit can match the input circuit in the operational amplifier, and MN6 is biased by Vip, so that when the input changes or the process angle changes, the voltage at point A can well track the change of the voltage at point B, thereby ensuring the reliability of the bias voltage.

[0091] In the first embodiment, the bias voltage VB1 of the auxiliary amplifier AMP1 is connected to the bias voltage VB11 of the bias circuit 105 , and the bias voltage VB2 of the auxiliary amplifier AMP2 is connected to the bias voltage VB21 of the bias circuit 105 .

[0092] The present invention provides a bias voltage circuit and a gain-enhanced operational amplifier, which are single-ended output operational amplifiers. Compared with conventional fully differential operational amplifiers, they reduce common-mode feedback circuits, simplify the circuit, and are highly practical.

[0093] At the same time, the bias circuit proposed in the present invention can bias the non-inverting input terminals of the auxiliary amplifiers AMP1 and AMP2, ensuring the outputs of the auxiliary amplifiers AMP1 and AMP2, and providing a suitable bias voltage for the second common-source and common-gate stage, thereby enabling the operational amplifier to have greater gain and bandwidth performance.

[0094] Example 2

[0095] The present invention also provides another implementation of a gain-boosting operational amplifier.

[0096] like Figure 4 As shown, the difference from the first embodiment is that the bias voltage VB11 of the auxiliary amplifier AMP1 is connected to the source of the MOS transistor MP7, and the bias voltage VB21 of the auxiliary amplifier AMP2 is connected to the source of the MOS transistor MN9.

[0097] In this embodiment, the non-inverting input terminal of the auxiliary amplifier AMP1 and the non-inverting input terminal of the auxiliary amplifier AMP2 are connected to the source of the MOS transistor MP7 and the source of the MOS transistor MN9 respectively. Compared with the first embodiment:

[0098] In the first embodiment, the MOS transistors MP4 and MN8 of the bias circuit are generally small in size. The small transistor area may cause large deviations during the manufacturing process, thereby causing deviations in the bias voltages VB1 and VB2. As a result, the operational amplifier cannot obtain a suitable operating voltage, resulting in performance degradation or malfunction.

[0099] In the second embodiment, the source output voltages of the MOS transistors MP7 and MN9 are used to bias the non-inverting input terminals of the auxiliary amplifiers AMP1 and AMP2. Since the MOS transistors MP7 and MN9 are relatively large, they can be well matched with the MOS transistors MN10 and MP8 in the layout, avoiding deviations caused by the manufacturing process, thereby providing a more stable bias voltage for the operational amplifier.

[0100] like Figure 5 As shown, by comparing the two solutions, it can be seen that the PSRR of Solution 2 (the operational amplifier provided by Example 2) is 16 dB greater than that of Solution 1 (the operational amplifier provided by Example 1).

[0101] In this embodiment, the two input terminals of the two auxiliary operational amplifiers simultaneously detect the common-mode interference of the two branches of the main amplifier circuit, and cancel them out at the outputs of the auxiliary operational amplifiers, thereby improving the power supply voltage rejection ratio of the main amplifier circuit.

[0102] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0104] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0105] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0106] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bias circuit, characterized in that: include: An input matching circuit (1051), connected to the input signal Vip, for matching the signal input circuit of the operational amplifier; A reference current source (1052) for generating a reference current Iin; A bias voltage generating circuit (1053) is used to generate a bias voltage VBN based on a reference current Iin; and generating a bias voltage VBPC, a bias voltage VBNC, a bias voltage VB11, and a bias voltage VB21 based on the bias voltage VBN; The bias voltage generating circuit (1053) comprises: A first bias voltage output circuit (10531) is configured to generate a bias voltage VBN based on a reference current Iin; A second bias voltage output circuit (10532) is configured to form two current source circuits based on a bias voltage VBN, generate a bias voltage VBPC based on a first current source circuit, and generate a bias voltage VBNC, a bias voltage VB11, and a bias voltage VB21 based on a second current source circuit; The input matching circuit (1051) includes: MOS transistor MN4, MOS transistor MN5, and MOS transistor MN6; the first bias voltage output circuit (10531) includes: MOS transistor MN1; the second bias voltage output circuit (10532) includes: MOS transistor MN2, MOS transistor MN3, MOS transistor MP4, and MOS transistor MN8; The gates of the MOS transistor MN4, MOS transistor MN5 and MOS transistor MN6 are all connected to the input signal Vip; The reference current Iin generated by the reference current source (1052) is connected in parallel to the gate of the MOS transistor MN1, the drain of the MOS transistor MN4, and then to the output end of the bias voltage VBN; The bias voltage VBN is connected to the gate of the MOS transistor MN2 and the gate of the MOS transistor MN3. The source of the MOS transistor MN2 is connected in parallel to the source of the MOS transistor MN1 and the source of the MOS transistor MN3 and then grounded. The drain of the MOS transistor MN2 is connected to the source of the MOS transistor MN5. The drain of the MOS transistor MN5 is connected in parallel to the gate of the MOS transistor MP6, the gate of the MOS transistor MP5, the gate of the MOS transistor MP4, and one end of the resistor Rc, and then connected to the output end of the bias voltage VBPC. The source of the MOS transistor MP6 is connected to the drain of the MOS transistor MP1. The gate of the MOS transistor MP1 is connected in parallel to the gate of the MOS transistor MP2, the gate of the MOS transistor MP3, the drain of the MOS transistor MP6, and the other end of the resistor Rc, and then connected to the output end of the bias voltage VBP. The source of the MOS transistor MP1 is connected in parallel to the source of the MOS transistor MP2 and the source of the MOS transistor MP3, and then connected to the power supply voltage VDD. The drain of the MOS transistor MN3 is connected in parallel to the source of the MOS transistor MN6 and the source of the MOS transistor MN7. The drain of the MOS transistor MN6 is connected to the drain of the MOS transistor MP5. The source of the MOS transistor MP5 is connected to the drain of the MOS transistor MP2. The gate of the MOS transistor MN7 is connected in parallel to the gate of the MOS transistor MN8, the drain of the MOS transistor MN8, and the drain of the MOS transistor MP4, and then connected to the output end of the bias voltage VBNC. The drain of the MOS transistor MN7 is connected in parallel to the source of the MOS transistor MN8, and then connected to the output end of the bias voltage VB21. The source of the MOS transistor MP4 is connected in parallel to the drain of the MOS transistor MP3 and then to the output end of the bias voltage VB11.

2. A gain-boosted operational amplifier, characterized in that: include: A main amplifier circuit and an auxiliary amplifier circuit (20); The main amplifying circuit comprises: A signal input circuit (101) for receiving an input signal Vip and an input signal Vin; The cascode transistor (102) is used to increase the output resistance to increase the gain of the main amplifier circuit, comprising: a first cascode stage and a second cascode stage; the first cascode stage is connected to the signal input circuit (101), and the second cascode stage is connected to the signal input circuit (101); A current mirror circuit (103) for mirroring the current of the first cascode stage to the second cascode stage; A tail current source circuit (104) is connected between the signal input circuit (101) and the ground terminal, and is used to provide a tail current source for the signal input circuit (101); A bias circuit (105), which is the bias circuit according to any one of claims 1, and is used to provide a bias voltage for the cascode transistor (102) and the auxiliary amplifier circuit (20); The auxiliary amplifier circuit (20) is used to provide a bias voltage for the second cascode stage to increase the DC gain of the operational amplifier.

3. The gain-boosted operational amplifier according to claim 2, wherein: The signal input circuit (101) includes: a MOS transistor MN11 and a MOS transistor MN12; the first cascode stage includes: a MOS transistor MN9 and a MOS transistor MP7; the second cascode stage includes: a MOS transistor MN10 and a MOS transistor MP8; the current mirror circuit (103) includes: a MOS transistor MP9 and a MOS transistor MP10 that are mirror images of each other; the auxiliary amplifier circuit (20) includes: an auxiliary amplifier AMP1 and an auxiliary amplifier AMP2; The gate of the MOS transistor MN11 and the gate of the MOS transistor MN12 are connected to the input signal Vip and the input signal Vin respectively; the drain of the MOS transistor MN11 is connected to the source of the MOS transistor MN9 of the first cascode stage, and the drain of the MOS transistor MN12 is connected to the source of the MOS transistor MN10 of the second cascode stage; the source of the MOS transistor MN11 is connected in parallel with the source of the MOS transistor MN12 and then connected to the tail current source circuit (104); The drain of the MOS tube MN9 is connected in parallel to the drain of the MOS tube MP7 and then connected to the gate of the MOS tube MP9 and the gate of the MOS tube MP10; the source of the MOS tube MP7 is connected to the drain of the MOS tube MP9, the gate of the MOS tube MN9 is connected to the bias voltage VBNC of the bias circuit (105), and the gate of the MOS tube MP7 is connected to the bias voltage VBPC of the bias circuit (105); The source of the MOS transistor MP9 is connected in parallel to the source of the MOS transistor MP10 and then connected to the power supply voltage VDD; The drain of the MOS transistor MN10 is connected in parallel to the drain of the MOS transistor MP8 and then connected to the single-ended signal output terminal Out of the operational amplifier; The source of the MOS transistor MN10 is connected to the inverting input terminal of the auxiliary amplifier AMP2, and the output terminal of the auxiliary amplifier AMP2 is connected to the gate of the MOS transistor MN10. The source of the MOS transistor MP8 is connected in parallel to the drain of the MOS transistor MP10 and then to the inverting input terminal of the auxiliary amplifier AMP1, and the output terminal of the auxiliary amplifier AMP1 is connected to the gate of the MOS transistor MP8. The non-inverting input terminal of the auxiliary amplifier AMP1 is connected to the bias voltage VB11 of the auxiliary amplifier AMP1 , and the non-inverting input terminal of the auxiliary amplifier AMP2 is connected to the bias voltage VB21 of the auxiliary amplifier AMP2 .

4. The gain-boosted operational amplifier according to claim 3, wherein: The bias voltage VB11 of the auxiliary amplifier AMP1 is connected to the source of the MOS transistor MP7 , and the bias voltage VB21 of the auxiliary amplifier AMP2 is connected to the source of the MOS transistor MN9 .

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