Package and method of forming the same

Abstract

A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method also includes forming a first through hole extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. The second through hole extends into a second plurality of dielectric layers in the second photonic die. Embodiments of the present application provide a package and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of forming the same. Background Art

[0002] Electrical signals and processing are one of the technologies used for signal transmission and processing. In recent years, optical signals and processing have been used in more and more applications, especially due to applications related to optical fibers for signal transmission.

[0003] Optical signals and processing are often combined with electrical signals and processing to provide sophisticated applications. For example, optical fibers can be used for long-distance signal transmission, and electrical signals can be used for short-distance signal transmission and processing and control. Accordingly, devices integrating optical components and electronic components are formed for conversion between optical and electrical signals, and processing of optical and electrical signals. A package can therefore include both an optical (photonic) die including an optical device and an electronic die including an electronic device. Summary of the invention

[0004] According to some embodiments of the present disclosure, a method of forming a package includes forming a first photonic die, including forming a first silicon waveguide; forming a first nitride waveguide; forming a first through-hole extending into a first plurality of dielectric layers in the first photonic die; bonding a second photonic die to the first photonic die, wherein the second photonic die includes a second nitride waveguide, wherein the first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide; and forming a second through-hole extending into a second plurality of dielectric layers in the second photonic die.

[0005] According to some embodiments of the present disclosure, a package includes a first photonic die, which includes a first silicon waveguide; a first plurality of dielectric layers located below the first silicon waveguide; a first nitride waveguide in one of the first plurality of dielectric layers; and a first through-hole penetrating the first plurality of dielectric layers; a second photonic die located below the first photonic die and bonded to the first photonic die, wherein the second photonic die includes a second plurality of dielectric layers; a second nitride waveguide in one of the second plurality of dielectric layers, wherein the second nitride waveguide is optically coupled to the first silicon waveguide through the first nitride waveguide; and a second through-hole penetrating the second plurality of dielectric layers; a conductive component is located below the second through-hole and electrically connected to the first through-hole through the second through-hole.

[0006] According to some embodiments of the present disclosure, a package includes an electronic die; a plurality of photonic dies stacked to form a die stack, wherein the electronic die is bonded to a top photonic die in the die stack, and wherein each of the plurality of photonic dies includes a plurality of dielectric layers; a conductive path passing through the plurality of dielectric layers; and a nitride waveguide, wherein the nitride waveguides in the plurality of photonic dies are optically coupled and configured to transmit light in a bottom die in the plurality of photonic dies to a top die in the plurality of photonic dies

[0007] Embodiments of the present application provide integrated 3DICs with stacked photonic dies and methods of forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1-Figure 5 , Fig. 6A , Figure 6B and Figure 7-Figure 18 A cross-sectional view of an intermediate stage in the formation of a package including stacked photonic dies is shown in accordance with some embodiments.

[0010] Figure 19-Figure 24 A cross-sectional view of an intermediate stage in the formation and integration of a package including stacked photonic dies and optical devices according to some embodiments is shown.

[0011] Figure 25-Figure 31 A cross-sectional view of an intermediate stage in the formation and integration of a package including stacked photonic dies and optical devices according to some embodiments is shown.

[0012] Figure 32-Figure 43 A cross-sectional view of an intermediate stage in the formation and integration of a package including stacked photonic dies and optical devices is shown according to some embodiments.

[0013] Fig.44 A package employing backside lighting is shown in accordance with some embodiments.

[0014] Fig.45 A package employing front side lighting is shown in accordance with some embodiments.

[0015] Fig.46 A side view of an optical device according to some embodiments is illustrated.

[0016] Fig.47 A process flow for forming a package including stacked photonic dies is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] Provided is a package including stacked photonic dies and a method for forming the same. According to some embodiments of the present disclosure, a plurality of photonic dies are formed and stacked, and bonded to an electronic die. The silicon substrate of some photonic dies may be removed during the packaging process, or may be thinned and used to form optical devices such as silicon waveguides, grating couplers, and the like. Non-silicon waveguides such as silicon nitride waveguides are formed in the stacked photonic dies and used as vertical optical paths for transmitting optical signals. Electrical vias are also formed to conduct electrical signals through the stacked photonic dies. As the photonic dies are stacked, the photonic dies occupy a smaller footprint. In addition, it may not be necessary to use optical fibers to conduct light between the photonic dies. The embodiments discussed herein are intended to provide examples to implement or use the subject matter of the present disclosure, and those of ordinary skill in the art will readily understand the modifications that may be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0020] Figures 1 to 18 1 shows a cross-sectional view of an intermediate stage in the formation of a package including stacked photonic dies according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in FIG. Fig.47 In the process flow 200 shown.

[0021] refer to Figure 1 , a base substrate 20 is provided. According to some embodiments, the base substrate 20 includes a body substrate 20A, a dielectric layer 20B above the body substrate 20A, and a silicon layer 20C (which is a capping layer) above the dielectric layer 20B. The body substrate 20A may be formed of a dielectric material, a semiconductor material, etc., or a combination thereof. According to some embodiments, the body substrate 20A includes a semiconductor substrate such as a silicon substrate. The dielectric layer 20B may be formed of or include a silicon oxide layer, or may be formed of other dielectric materials that are transparent to light (e.g., silicon oxynitride). According to some embodiments, the dielectric layer 20B may have a thickness in a range between about 0.5 μm and about 4 μm. The thickness of the silicon layer 20C may be in a range between about 0.1 μm and about 1.5 μm. The base substrate 20 may be referred to as having a front side or a front side (e.g., Figure 1 the side facing upward) and the dorsal or back side (e.g. Figure 1 The front side of the base substrate 20 is also referred to as the front side of the resulting photonic wafer and photonic die.

[0022] exist Figure 2 In the process, the silicon layer 20C is patterned to form a plurality of photonic devices, which are also referred to as silicon devices. Fig.47 The process flow 200 is shown as process 202. Some examples of photonic devices include optical devices, which may include a waveguide 22, a photonic component 24, and a grating coupler 26. The illustrated waveguide 22, photonic component 24, and grating coupler 26 may represent multiple devices. The silicon layer 20C may be patterned using suitable photolithography and etching techniques, which may involve an etching process using a photoresist to define the pattern. Throughout the specification, components formed by the silicon layer 20C are collectively referred to as photonic layers.

[0023] According to some embodiments, the photonic component 24 is physically and / or optically coupled to the waveguide 22 so as to optically interact with the waveguide 22 via an optical signal. Example photonic components 24 may include, but are not limited to, photodetectors, modulators, and the like. For example, a photodetector may be optically coupled to the waveguide 22 to detect an optical signal within the waveguide 22 and generate an electrical signal corresponding to the optical signal. The modulator may also receive an electrical signal and modulate the optical power within the waveguide 22 to generate a corresponding optical signal. In this manner, the photonic component 24 may input an optical signal from the waveguide 22 or output an optical signal to the waveguide 22. According to other embodiments, the photonic component may include other active or passive components, such as a laser diode, an optical signal splitter, or other types of photonic structures or devices.

[0024] According to some embodiments, one or more grating couplers 26 may be integrated with the waveguide 22, and may be formed by patterning the silicon layer 20C. The grating coupler 26 is a photonic device that allows optical signals and / or optical power to be transmitted between the waveguide 22 and a photonic component such as a subsequently formed optical via, a microlens, etc. The grating coupler 26 may be formed using photolithography and etching processes. The grating coupler 26, the waveguide 22, and the photonic component 24 may share some common etching processes and etching masks.

[0025] See also Figure 3 , a dielectric layer 28 is formed on the waveguide 22, the photonic component 24, the grating coupler 26, and the dielectric layer 20B. The dielectric layer 28 may be formed of or include one or more layers of silicon oxide, silicon nitride, combinations thereof, or the like, and may be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on dielectric formation process, high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. The dielectric layer 28 is transparent to light. According to some embodiments, the dielectric layer 28 is planarized by a planarization process such as a CMP process or a mechanical grinding process. The portion of the dielectric layer 28 on the optical layer may have a thickness in a range between about 10 nm and about 500 nm.

[0026] Due to the different refractive indices of the materials of waveguide 22 and dielectric layer 28, waveguide 22 has a high internal reflection such that light is substantially confined within waveguide 22, depending on the wavelength of the light and the refractive index of the medium of the respective materials. According to some embodiments, the refractive index of the material of waveguide 22 is higher than the refractive index of the material of dielectric layer 28. For example, waveguide 22 may include silicon, and dielectric layer 28 may include silicon oxide.

[0027] See also Figure 3 , through-hole 30 and contact plug 32 are formed in dielectric layer 28. According to some embodiments, through-hole 30 and contact plug 32 are formed by a damascene process, such as single damascene, dual damascene, or the like. For example, through-hole 30 can be formed by forming an opening extending through dielectric layer 28 and filling the opening with a conductive material. The conductive material may include a diffusion barrier layer formed of TiN, TaN, Ti, Ta, etc., and a metal material such as tungsten, copper, cobalt, etc. A planarization process such as a CMP process or a mechanical grinding process may be performed to remove excess conductive material. The remainder of the diffusion barrier layer and the metal material are through-hole 30 and contact plug 32. The contact plug is electrically connected to the optical component.

[0028] According to some embodiments, contact plug 32 extends through dielectric layer 28 and is electrically connected to photonic component 24. Contact plug 32 allows power or electrical signals to be transmitted to and from photonic component 24. In this manner, photonic component 24 may convert electrical signals into optical signals transmitted by waveguide 22 and / or may convert optical signals from waveguide 22 into electrical signals.

[0029] See also Figure 3 , a redistribution structure 34 is formed on the dielectric layer 28. The corresponding process is Fig.47 The process flow 200 is shown as process 204. The redistribution structure 34 includes a dielectric layer 36 and a conductive feature 38 formed in the dielectric layer 36. The conductive feature 38 provides interconnection and circuit routing. The conductive feature 38 is electrically connected to the through hole 30, the contact plug 32 and / or an above device such as an electronic tube die. The dielectric layer 36 can be, for example, an insulating and / or passivation layer, and can include silicon oxide, silicon nitride or other materials. The dielectric layer 36 can be transparent or opaque to light. The dielectric layer 36 can be formed by a damascene process. The conductive pad 40 is formed in the topmost layer of the dielectric layer 36.

[0030] exist Figure 4 and 5 In FIG. 4 , a portion of the redistribution structure 34 is removed and replaced by a dielectric layer 42 . Figure 4 , a portion of the redistribution structure 34 can be removed by etching to form the groove 41. The corresponding process is as follows Fig.47 The removed portion of the redistribution structure 34 may be located directly above the grating coupler 26. Next, as shown in the process flow 200, Figure 5 As shown, a dielectric layer 42 is deposited, and then a planarization process is performed to expose the conductive pad 40. The corresponding process is as shown in FIG. Fig.47 The process flow 200 is shown as process 208 .

[0031] The material of dielectric layer 42 is selected to provide a dielectric layer 42 which provides a dielectric layer 42 between grating coupler 26 and vertically mounted optical fibers (not shown) and / or microlenses (e.g. Figure 8 The invention provides more efficient optical coupling between the microlenses 54 in the redistribution structure 34. For example, the dielectric layer 42 can be more transparent, have lower losses, and be less reflective than the dielectric layer 36. According to some embodiments, the material of the dielectric layer 42 is similar to the material of the dielectric layer 36, but is deposited using a technique that forms a material with better quality (e.g., fewer impurities, dislocations, etc.). In this way, replacing portions of the dielectric layer 36 of the redistribution structure 34 with the dielectric layer 42 can allow for more efficient operation of the resulting photonic package and can reduce optical signal losses. For example, the dielectric layer 42 can be formed of or include silicon oxide.

[0032] According to other embodiments, dielectric layer 36 is not replaced by dielectric layer 42. In these embodiments, some areas of redistribution structure 34 may be substantially free of conductive features 38 and conductive pads 40 to allow optical signals to be transmitted through dielectric layer 36. For example, these metal-free areas may be between grating coupler 26 and microlens 54 ( Figure 8 ), the microlens 54 can be aligned with the vertically mounted optical fiber to allow optical signals to be coupled between the grating coupler 26 and the optical fiber.

[0033] refer to Fig. 6A According to some embodiments, one (or more) electronic dies 44 are bonded to the redistribution structure 34. Fig.47 In the illustrated process flow 200, the corresponding process is shown as process 210. The electronic die 44 may be, for example, a semiconductor device, die, or chip that communicates with the photonic assembly 24 using electrical signals. Fig. 6A An electronic die 44 is shown in FIG. 4 , while according to other embodiments, the resulting photonic package 70 ′( Fig.18 ) may also include two or more electronic dies 44. The electronic die 44 includes a semiconductor substrate 45, an interconnect structure 41 and an electrical connection 46, which may be, for example, a conductive pad, a conductive column, or the like.

[0034] The electronic die 44 may include an integrated circuit for interfacing with the photonic component 24, such as a circuit for controlling the operation of the photonic component 24. For example, the electronic die 44 may include a controller, a driver, an amplifier, etc., or a combination thereof. The electronic die 44 may also include a CPU. According to some embodiments, the electronic die 44 includes a circuit for processing an electrical signal received from the photonic component 24. According to some embodiments, the electronic die 44 may also control the high-frequency signal transmission of the photonic component 24 based on an electrical signal (data or the like) received from another device or die. According to some embodiments, the electronic die 44 may be an electronic integrated circuit (EIC) or the like that provides a serializer / deserializer (SerDes) function. In this way, the electronic die 44 can act as part of an I / O interface between optical signals and electrical signals.

[0035] According to some embodiments, the electronic die 44 is bonded to the redistribution structure 34 by hybrid bonding (including both dielectric-to-dielectric bonding and metal-to-metal bonding), direct metal-to-metal bonding, solder bonding, or the like.

[0036] Figure 6B Shows Fig. 6A An example top view of the structure shown in . According to some embodiments, waveguide 22 extends under electronic die 44. There may be multiple waveguides 22. Also, there may be multiple bond pads 40 and 46.

[0037] refer to Figure 7 , gap filling material 48 is formed on the electronic tube core 44 and the redistribution structure 34. The corresponding process is Fig.47 The process flow 200 shown in FIG. 2 is shown as process 212. The gap filling material 48 may be formed of silicon oxide, silicon nitride, a polymer, etc., or a combination thereof. The gap filling material 48 may be formed by CVD, PVD, ALD, a spin coating process, HDP-CVD, FCVD, etc., or a combination thereof. The gap filling material 48 may be a material (e.g., silicon oxide) that is transparent to light at a wavelength suitable for transmitting an optical signal or optical power therein. According to some embodiments in which light is not projected upward through the gap filling material 48, the gap filling material 48 may include a relatively opaque material, such as a sealant, a molding compound, etc. The gap filling material 48 may be planarized using a planarization process such as a CMP process, a grinding process, etc. According to some embodiments, the planarization process may expose the electronic die 44, wherein the top surface of the electronic die 44 and the gap filling material 48 are coplanar.

[0038] Figure 8 The attachment of the support substrate 50 is shown. Fig.47 The process flow 200 is shown as process 214. According to some embodiments, a silicon-containing dielectric layer 52 (which may include silicon oxide, silicon oxynitride, silicon carbonitride, or the like) is used to bond the support substrate 50 to the semiconductor substrate of the electronic die 44 and to the gap fill material 48. The bonding may be performed by fusion, wherein Si-O-Si bonds are formed. A microlens 54 may be formed in the support substrate 50. According to some embodiments, the support substrate 50 is or includes a silicon substrate.

[0039] Next, the bulk substrate 20A may be removed. The corresponding process is as follows Fig.47 The process flow 200 is shown as process 216. The resulting structure is Fig. 9 . The bulk substrate 20A may be removed using a planarization process (e.g., a CMP or grinding process), an etching process, a combination thereof, or the like. According to some embodiments, the dielectric layer 20B is also thinned. The thinning of the dielectric layer 20B may be part of the removal process of the bulk substrate 20A, or the dielectric layer 20B may be thinned in a separate step. According to some embodiments, after thinning, the dielectric layer 20B may have a thickness in a range of about 0.05 μm to about 0.5 μm.

[0040] According to an alternative embodiment, instead of completely removing the bulk silicon substrate 20A, the bulk silicon substrate 20A is thinned and then patterned to form a silicon component 21, which may include a silicon waveguide, a grating coupler, a photonic component, etc., which are substantially the same as the silicon waveguide 22, the grating coupler 26, and the photonic component 24 discussed above, respectively. The corresponding process is also shown as Fig.47The process 216 in the process flow 200 is shown. Fig. 9 and the resulting package 70'( Fig.18 ), the silicon feature 21 is shown as a dotted line to indicate that the silicon feature 21 may or may not be formed.

[0041] In a subsequent process, nitride waveguides 56 (including 56A and 56B, and possibly more) are formed. Fig.10 , the nitride waveguide 56A is formed on the dielectric layer 20B. The corresponding process is as follows Fig.47 The process flow 200 is shown as process 218. The formation process may include a deposition process followed by a patterning process by etching. The deposition process may include CVD, PECVD, LPCVD, PVD, etc. The nitride waveguide 56A may be formed of or include silicon nitride, silicon oxynitride, etc. Alternatively, a polymer waveguide may be formed instead of forming the nitride waveguide 56A. According to some embodiments, the thickness of the nitride waveguide 56A may be in a range between about 0.2 μm and about 1.0 μm, while other thicknesses are possible.

[0042] According to some embodiments, the nitride waveguide 56A may include a photonic structure, such as a grating coupler, an edge coupler, or a coupler that allows an optical signal to be transmitted or processed (e.g., a mode converter). A waveguide formed of silicon nitride (e.g., nitride waveguide 56A) may have advantages over a waveguide formed of silicon (e.g., waveguide 22). For example, silicon nitride has a higher dielectric constant than silicon, so a nitride waveguide may have greater internal light confinement than a silicon waveguide. This may also allow the performance or leakage of the nitride waveguide to be less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or line width roughness). Reduced process sensitivity may allow nitride waveguides to be processed more easily or at a lower cost than silicon waveguides. These properties may allow nitride waveguides to have lower propagation losses than silicon waveguides. In some cases, the propagation loss (dB / cm) of a nitride waveguide may be between about 0.1% and about 50% of that of a silicon waveguide.

[0043] refer to Fig.11 , a dielectric layer 58A is formed on the nitride waveguide 56A. The corresponding process is Fig.47The process flow 200 is shown as process 220. Dielectric layer 58A may include one or more materials similar to those described above for dielectric layer 28 or dielectric layer 42. For example, dielectric layer 58A may include silicon oxide, spin-on glass, etc. Dielectric layer 58A may be formed using a process similar to that described above for dielectric layer 28 or dielectric layer 42, or may be formed using a different process. For example, dielectric layer 58A may be formed using CVD, PVD, spin coating, etc., while another process may be used. According to some embodiments, a planarization process such as a CMP process or a mechanical grinding process is used to remove excess material of dielectric layer 58A. After planarization, dielectric layer 58A may have a surface (bottom surface shown) that is coplanar with a surface of nitride waveguide 56A. Alternatively, dielectric layer 58A may be thicker than nitride waveguide 56A and may have a portion that overlaps nitride waveguide 56A.

[0044] refer to Fig.12 , more nitride waveguides 56 (including waveguide 56B) and dielectric layers 58 (including dielectric layers 58B and 58C) are formed layer by layer. Fig.47 As shown, the corresponding process is shown as process 222 in process flow 200. Reflector 57 can also be formed of metals such as copper, tungsten, nickel, etc. Additional nitride waveguides 56 and dielectric layer 58 can be formed using materials and processes selected from the same candidate materials and processes used to form waveguide 56A and dielectric layer 58A. According to some embodiments, the additional nitride waveguide 56 is physically separated from its upper nitride waveguide 56 by dielectric layer 58. In addition, at least some or all of the nitride waveguides 56 are completely enclosed in dielectric layer 58. In other words, all surfaces of at least some or all of the nitride waveguides 56 are in contact with dielectric layer 58. Each waveguide 56 can have at least a portion or all of an overlap with a directly covered waveguide 56. In addition, each waveguide 56 can be separated by a small vertical distance from its directly overlying waveguide 56, for example, less than about 1 μm.

[0045] refer to Fig.13 , (conductive) vias 60 and bonding pads 62 are formed in dielectric layer 58 and dielectric layer 20B. The corresponding process is Fig.47 The process flow 200 is shown as process 224. The formation process may include etching through dielectric layer 58 and dielectric layer 20B to form a via opening and expose via 30, filling the via opening with a conductive material (e.g., TiN, TaN, Ti, Ta, Cu, W, Co, etc.), and performing a planarization process. There may or may not be a dielectric liner formed around the conductive material. Bonding pads 62 are also formed, and additional dielectric layer 58D may be formed. Dielectric layer 58D may be formed of a material similar to other dielectric layers 58. Thus, a photonic wafer 64 is formed, which is bonded to electronic die 44.

[0046] refer to Fig.14 , forming a photonic wafer 164. According to some embodiments, the photonic wafer 164 is formed using a process similar to (or a different process from) the process used to form the photonic die wafer 64. The structure of the photonic wafer 164 may be the same, similar, or different from the structure of the photonic wafer 64. According to some embodiments, the components in the photonic wafer 164 are represented using the reference numerals of similar components in the photonic die 64, with the number "1" added as a prefix. Similar components in the photonic wafer 164 may be similar to corresponding components in the photonic wafer 64. For example, the waveguides, photonic components, grating couplers, and nitride waveguides in the photonic wafer 164 are represented using reference numerals 122, 124, 126, and 156, respectively. In addition, a redistribution structure 134, a dielectric layer 128, a dielectric layer 142, vias 130 and 132, a bulk substrate 120A and an oxide layer 120B, and a bonding pad 140 may also be formed.

[0047] According to some embodiments, nitride waveguide 68 is formed in dielectric layer 142. According to alternative embodiments, no nitride waveguide is formed in dielectric layer 142 when redistribution structure 134 is thin, for example, thinner than about 2 μm or about 1 μm.

[0048] Next, if Fig.15 As shown, the photonic wafer 164 is bonded to the photonic wafer 64. The corresponding process is as shown in FIG. Fig.47 This is shown as process 226 in the illustrated process flow 200 . The bonding may be performed by hybrid bonding, where bond pads 140 in photonics wafer 164 are bonded to bond pads 62 in photonics wafer 64 , and dielectric layer 58D is bonded to the surface dielectric layer and dielectric layer 142 in photonics wafer 164 .

[0049] Next, according to some embodiments, the bulk silicon substrate 120A is thinned and then patterned to form silicon components 121, which may include silicon waveguides, grating couplers, photonic components, etc. According to alternative embodiments, after bonding, the bulk silicon substrate 120A is completely removed and the oxide layer 120B may be thinned. The corresponding process is Fig.47 This is shown as process 228 in the process flow 200 shown. Fig.15 , the silicon feature 121 is shown as a dotted line to indicate that the silicon feature 121 may or may not be formed.

[0050] Fig.16 The formation of more nitride waveguides 156 and dielectric layers 158 (including 158A, 158B, 158C and 158D) is shown. The corresponding process is as shown in FIG. Fig.47 This is shown as process 230 in the illustrated process flow 200. The materials and formation processes may be referred to in the formation of the nitride waveguide 56 and the dielectric layer 58.

[0051] According to some embodiments where bulk silicon substrate 120A is completely removed, some nitride waveguides 156 are formed to physically contact oxide layer 120B. Fig.16 , the silicon feature 121 and one nitride waveguide 156 are both shown as dashed lines to indicate that the silicon feature 121 or the nitride waveguide 156 or both may be formed to contact the oxide layer 120B.

[0052] Fig.17 The formation of through-hole 160 and bonding pad 162 is shown. The corresponding process is shown as Fig.47 The process 232 in the process flow 200 is shown. Thus, the photonic wafer 164 is formed. The formation process and materials can refer to the formation process and materials of the dielectric layer 58, the through hole 60, and the pad 62, respectively, and will not be repeated here.

[0053] Fig.18 The formation of an electrical connector 166 is shown, which may be formed on a bonding pad 162 (which may be an under bump metallization). The corresponding process is Fig.47 The process flow 200 is shown as process 234. The resulting structure is referred to as photonic wafer 70. According to some embodiments, in addition to the photonic wafers 64 and 164 shown, there are multiple photonic wafers one or stacked between photonic wafers 64 and 164, and the process for forming and stacking additional photonic wafers is similar to Figures 14 to 17 The process shown. In a subsequent process, a singulation process is performed to saw the photonic wafer 70 apart and form discrete photonic dies 70', which are identical to each other. Each photonic die 70' includes one or more electronic dies 44, and also includes one of the photonic dies 64' in the photonic wafer 64 and one of the photonic dies 164' in the photonic wafer 164. In a subsequent process, the photonic package 70' is further packaged. For example, an optical fiber (not shown) can be attached to the microlens 54 and aligned with the microlens 54.

[0054] In the photon package 70', the electronic die 44 is bonded to the stacked photon die 64', 164', etc. There are multiple electronic conduction paths for conducting current and signals. The electronic conduction paths connect the electronic die 44 and extend to the bottom of the photon package 70'. For example, arrow 71 is drawn to represent one of the conduction paths, which includes the vias 60 and 160 and the corresponding bonding pads, and the redistribution lines in the redistribution structures 34 and 134.

[0055] The photonic package 70' also includes an optical through hole 72, which includes the silicon waveguides 22, 122 and the nitride waveguides 56 and 156, and possibly the silicon waveguides 21, 121, and 68. When the horizontal distances between adjacent silicon waveguides 22, and when the horizontal distances between adjacent silicon waveguides 22, 122 and nitride waveguides 56 are small, when there is an overlap, and when the vertical distances D1 and D2 between the silicon waveguides 22, 122 and the nitride waveguides 56 are small, light can be optically coupled between adjacent silicon waveguides 22, 122 and nitride waveguides 56. Therefore, the light in the bottom nitride waveguide 56 can be coupled to the overlapping silicon waveguides 22, 122 (and possibly the silicon waveguides 21, 121, and 68) and the nitride waveguides 56 and 156 through the optical path marked by arrow 73. Although Fig.18 Silicon waveguides 21 and 121 are shown outside of optical path 73, but silicon waveguides 21 and / or 121 may also be formed in place of corresponding nitride waveguides 56A and / or 156A to form part of optical path 73. Optical vias 72 may also include silicon features 68 when they are formed in optical path 73.

[0056] Light may also be launched by the grating coupler 26 to the microlens 54 and the covering optical fiber (not shown), and the corresponding light is shown as the light beam 75. Thus, the silicon waveguides 22, 122, the nitride waveguides 56 and 156, and possibly the silicon components 21, 121 and / or 68 in the optical path 73 are collectively referred to as optical through-holes 72, which may extend into two or more photonic dies 64' / 164'.

[0057] In order to effectively couple light to each other, the adjacent silicon waveguides 22, 122 and nitride waveguides 56 in the light through hole 72 have a small distance to achieve effective light coupling and low light loss. For example, the vertical distance D1 between the silicon waveguide 22 / 122 and its adjacent nitride waveguide 56 can be less than about 2,000 angstroms, and the vertical distance D2 between adjacent nitride waveguides 56 can be less than about 2 μm. In addition, for efficient light transmission, all materials in the optical path including the dielectric layers 58 and 158 and the oxide layers 20B and 120B, 142, etc. can be light-transmissive and can have a light refractive index less than that of silicon nitride. For example, some or all of these dielectric layers can be formed of or include silicon oxide.

[0058] Figures 19 to 24 1 shows a cross-sectional view of an intermediate stage in the formation of a photonic package and the integration of photonic components according to some embodiments of the present disclosure. Unless otherwise specified, the materials and formation processes of the components in these embodiments are the same as those in the previous Figure 1-Figure 5 , Fig. 6A , Figure 6B and Figure 7-Figure 18 The same components in the illustrated embodiments are denoted by the same reference numerals and are substantially the same. Figure 19-Figure 24 (as well as Figure 25-Figure 31 , Figure 32-Figure 43 , Fig.44 and Fig.45 Details of the formation process and materials of the components shown in the embodiments of FIG. 1 can be found in the discussion of the previous embodiments. The initial steps of these embodiments are similar to Figure 1-Figure 5 , Fig. 6A , Figure 6B and Figure 7-Figure 17 The structure obtained is basically the same as shown in Fig.19 shown.

[0059] Fig. 20 The bonding of the support substrate 74 is shown. According to some embodiments, a silicon-containing dielectric layer 76, which may include silicon oxide, silicon oxynitride, silicon carbonitride, etc., is used to bond the support substrate 74 to the support substrate 50. According to alternative embodiments, the support substrate 50 and the dielectric layer 52 are not used, and the support substrate 74 and the dielectric layer 76 are directly bonded to the electronic tube core 44 and the gap filling material 48. The bonding can be performed by dielectric-dielectric bonding, in which Si-O-Si bonds are formed. The microlens 54 can be formed in the support substrate 74. According to some embodiments, the support substrate 74 is or includes a silicon substrate, a glass substrate, etc.

[0060] refer to Fig.21 , the photon assembly 78 is attached to the support substrate 74 (e.g., to the dielectric layer 76). The bonding can be achieved by welding, adhesive bonding, solder bonding, etc. According to some embodiments, the photon assembly 78 is a photodiode (e.g., a laser diode), which can be formed of or include a III-V semiconductor material. According to some embodiments, the photon assembly 78 is configured to receive an electrical signal and emit a light beam (e.g., a laser beam). The light-emitting region 80 can be horizontally aligned with one of the nitride waveguides 156 (denoted as 156REC), which receives the light beam emitted by the light-emitting region 80 and transmits the light upward along the optical path 73. According to some embodiments, the lateral distance D3 between the light-emitting region 80 and the light-receiving nitride waveguide 156REC is small, for example, less than about 300nm, and can be in the range of about 200nm to about 300nm.

[0061] Fig. 22 and Fig.23 The formation of bonding wires 84 and the filling of optical glue 82 (optical glue 82 is transparent to the light emitted by the photon assembly 78) are shown to fix the photon assembly 78. The order of forming the bonding wires 84 and the filling order of the optical glue 82 can also be reversed. The photon assembly 78 can be electrically connected to one of the bonding pads 162 through the bonding wires 84. Fig.24The formation of electrical connections 166 is shown, thereby forming the photonic wafer 70. In a subsequent process, a singulation process is performed to separate the unconnected photonic packages 70' from each other.

[0062] Figure 25 to Figure 31 The formation of a photonic package and the integration of a photonic component with the photonic package according to an alternative embodiment are shown. Fig.25 , forming a redistribution component 86. The redistribution component 86 includes a substrate 88 and a redistribution structure 87 above the substrate 88. The substrate 88 can be a semiconductor substrate, a dielectric substrate, a glass carrier, etc. The redistribution structure 87 further includes a dielectric layer 90 and a redistribution line 92 in the dielectric layer 90. The redistribution line 92 can be formed by a damascene process or by an electroplating process.

[0063] refer to Fig.26 , the photon package 70' is bonded to the redistribution component 86. The bonding may be performed by hybrid bonding, metal-to-metal direct bonding, etc. Next, refer to Fig. 27 , the photon assembly 78 is bonded to the redistribution element 86. The bonding may be by metal-to-metal direct bonding, solder bonding, etc. The electrode 81 of the photon assembly 78 is electrically connected to and may be physically bonded to a bonding pad, which is part of the redistribution line 92. Thus, the photon assembly 78 may be electrically connected to the electronic die 44 through the redistribution line 92 and the through vias 60 and 160. According to some embodiments, the sidewalls of the photon assembly 78 contact the sidewalls of the photon package 70'. According to an alternative embodiment, there is a gap (similar to Fig. 22 ).

[0064] refer to Fig.28 , the sealant 94 is dispensed and cured. According to some embodiments, the sealant 94 includes a molding compound. According to alternative embodiments, the sealant 94 includes silicon oxide, silicon nitride, etc. In subsequent processes, a planarization process, such as a CMP process or a mechanical polishing process, may be performed, and the resulting structure may be as shown in FIG. Fig.29 shown.

[0065] Fig.29 Further shown is the attachment of a support substrate 74, which may be bonded to the support substrate 50 by fusion bonding with a dielectric layer 76 therebetween. The microlenses 54 may be formed in the support substrate 74.

[0066] In the subsequent process, the substrate 88 is removed by, for example, a CMP process, a mechanical grinding process, an etching process, etc. The obtained structure is as follows: Fig.30 shown. Fig.31 The formation of the electrical connectors 166 is illustrated, thereby forming the photonic wafer 70. Subsequently, a singulation process is performed to saw the unconnected photonic packages 70' from each other.

[0067] Figures 32 to 43 The formation of a photonic package and the integration of a photonic component with the photonic package according to an alternative embodiment are shown. Figures 1 to 5 is the same as that shown in , and the resulting structure is also shown in Fig.32 Next, refer to Fig.33 , bonding the electronic die 44 to the redistribution structure 34. In addition, a heat block 98 having a high thermal conductivity value (e.g., above about 1 Watt / m*K) is attached to the redistribution structure 34. The heat block 98 may be a silicon block, a metal block, etc. According to some embodiments, the attachment is achieved by a thermal interface material (not shown) that adheres the heat block 98 to the metal pad 40'. The metal pad 40' may be connected to one of the bonding pads 40 that will be bonded to the electronic die 44.

[0068] Figures 34 to 38 The subsequent process shown is Figures 7 to 17 The processes shown are basically the same. Therefore, the details of materials and processes will not be discussed in detail here. Fig.34 As shown, gap fill material 48 is formed and planarized. Fig.35 Attachment of a support substrate 50 is shown. Fig.36 The bulk substrate 20A is shown removed, followed by formation of Fig.37 Dielectric layer 58 and nitride waveguide 56 are shown. Fig.38 The formation of a photonics wafer 164 is shown, which includes vias 60 and pads 62 .

[0069] refer to Fig.39 An anisotropic etching process is performed to etch light-transmitting sub-wafer 164, dielectric layer 56, dielectric layer 20B, and dielectric layer 36 in interconnect structure 34. Thus, opening 102 is formed. According to some embodiments, opening 102 stops on metal pad 40' in interconnect structure 34.

[0070] Fig.40 Attachment of the photon assembly 78 to the metal pad 40' is shown, wherein the electrode 81 in the photon assembly 78 is bonded to the metal pad 40' and electrically connected to the metal pad 40'. Fig.41 As shown, a planarization process is performed to remove the portion of the photonic component 78 that extends outside the opening 102. Next, the optical adhesive 82 is dispensed and cured, as shown in FIG. Fig.42 According to some embodiments, Fig.41 and 42 The process shown can be reversed. Fig.43The formation of electrical connections 166 is illustrated, thereby forming the photonic wafer 70. In a subsequent process, a singulation process is performed to separate the unconnected photonic packages 70' from each other. The optical path from the light-emitting region 80 in the photonic assembly 78 to the nitride waveguide 156REC and to the waveguide 22 and the grating coupler 26 is also shown.

[0071] Embodiments of the present application may adopt a front lighting scheme, wherein light may be emitted or received from the front side of the photonic package 70'. For example, Fig.44 A photonic package 70' is shown that uses front side illumination, where the front side refers to the front side of the photonic dies 64 and 164. Fig.44 In FIG. 8 , a package assembly 96 (which may be an interposer, a package assembly, a package, a printed circuit board, etc.) is bonded to the photonic package 70 ′.

[0072] Fig.45 A photon package 70' is shown that employs a backside illumination scheme. With backside illumination, more chip area can be used for sensor illumination (if an image sensor is employed), and the density of the image sensor can be increased. The process flow for packaging the corresponding photon package is similar to that discussed in the previous embodiments, except that wire bonding (via bonding wires 103) is performed to electronically connect the photon package 70' to the underlying package components. Fig.44 In FIG. 7 , a package assembly 96 (which may be an interposer, a package assembly, a package, a printed circuit board, etc.) is attached to the photon package 70 ′.

[0073] In the above embodiments, some processes and components are discussed to form three-dimensional (3D) packages according to some embodiments of the present disclosure. Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, the use of test pads, probes and / or probe cards that allow testing of 3D packages or 3DICs formed in a redistribution layer or on a substrate. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods for intermediate verification of known good dies to increase yield and reduce costs.

[0074] Embodiments of the present disclosure have several advantageous features. By stacking photonic dies with electronic dies, the size of the corresponding photonic package can be reduced. Optical vias including nitride waveguides and silicon waveguides can be used to provide optical communication between photonic dies without the need for optical fibers.

[0075] According to some embodiments of the present disclosure, a method includes forming a first photonic die, including forming a first silicon waveguide; forming a first nitride waveguide; forming a first via in a first plurality of dielectric layers extending into the first photonic die; bonding a second photonic die to the first photonic die, wherein the second photonic die includes a second nitride waveguide, wherein the first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide; and forming a second via in a second plurality of dielectric layers extending into the second photonic die. In one embodiment, the method also includes bonding an electronic die to the first photonic die, wherein the second via is electrically coupled to the electronic die through the first via. In one embodiment, forming the first silicon waveguide includes etching a silicon layer on an oxide layer of a base substrate, and the method also includes forming a redistribution structure above the oxide layer, wherein the redistribution structure includes a third plurality of dielectric layers and a plurality of redistribution lines in the third plurality of dielectric layers. In one embodiment, etching the silicon layer further forms a grating coupler. In one embodiment, the base substrate further comprises a bulk silicon substrate below the oxide layer, and the method further comprises removing the bulk silicon substrate before bonding the second photonic die to the first photonic die. In one embodiment, the base substrate further comprises a bulk silicon substrate below the oxide layer, and the method further comprises: thinning the bulk silicon substrate before bonding the second photonic die to the first photonic die; etching the thinned bulk silicon substrate to form a second silicon waveguide. In one embodiment, the second silicon waveguide optically couples the second nitride waveguide to the first silicon waveguide. In one embodiment, forming the first photonic die further comprises forming a third nitride waveguide, wherein the third nitride waveguide optically couples the second nitride waveguide to the first silicon waveguide. In one embodiment, forming the first photonic die further comprises forming a fourth nitride waveguide, wherein the fourth nitride waveguide optically couples the second nitride waveguide to the first silicon waveguide. In one embodiment, the method further comprises attaching a photonic assembly, wherein the photonic assembly comprises a light-emitting region aligned with the second nitride waveguide, and wherein the second nitride waveguide is configured to receive a light beam emitted from the light-emitting region. In one embodiment, the method further includes attaching a silicon support substrate, wherein the second photonic die and the silicon support substrate are located on opposite sides of the first photonic die.

[0076] According to some embodiments of the present disclosure, a package includes a first photonic die, the first photonic die including a first silicon waveguide; a first plurality of dielectric layers located below the first silicon waveguide; a first nitride waveguide in one of the first plurality of dielectric layers; and a first through-hole penetrating the first plurality of dielectric layers; a second photonic die located below the first photonic die and bonded to the first photonic die, wherein the second photonic die includes a second plurality of dielectric layers; a second nitride waveguide in one of the second plurality of dielectric layers, wherein the second nitride waveguide is optically coupled to the first silicon waveguide through the first nitride waveguide; and a second through-hole penetrating the second plurality of dielectric layers; a conductive component is located below the second through-hole and electrically connected to the first through-hole through the second through-hole. In one embodiment, the package also includes an electronic die above the first photonic die and bonded to the first photonic die, wherein the second through-hole is electrically connected to the electronic die through the first through-hole. In one embodiment, the package further comprises a photonic assembly, wherein the photonic assembly comprises a light-emitting region aligned with the second nitride waveguide, and wherein the second nitride waveguide is configured to receive a light beam emitted from the light-emitting region. In one embodiment, the first photonic die and the second photonic die are configured to optically transmit the light beam to the first silicon waveguide. In one embodiment, the package further comprises a second silicon waveguide in a dielectric layer in the second plurality of dielectric layers.

[0077] According to some embodiments of the present disclosure, a package includes an electronic die; a plurality of photonic dies stacked to form a die stack, wherein the electronic die is bonded to a top photonic die in the die stack, and wherein each of the plurality of photonic dies includes a plurality of dielectric layers; a conductive path passing through the plurality of dielectric layers; and a nitride waveguide, wherein the nitride waveguide in the plurality of photonic dies is optically coupled and configured to transmit light in a bottom die in the plurality of photonic dies to a top die in the plurality of photonic dies. In one embodiment, one of the plurality of photonic dies further includes a silicon waveguide. In one embodiment, the package further includes a laser diode including a light-emitting region aligned with the nitride waveguide in one of the plurality of photonic dies. In one embodiment, the package further includes a photodiode including a light-emitting region aligned with a light-receiving nitride waveguide in one of the plurality of photonic dies, wherein the photodiode and one of the plurality of photonic dies are configured such that the light-receiving nitride waveguide receives a light beam emitted from the light-emitting region.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent configurations do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a package, comprising: forming a first photonic die, comprising: forming a first silicon waveguide; and forming a first plurality of nitride waveguides forming a first optical path through the first photonic die; forming a first via extending into a first plurality of dielectric layers in the first photonic die and a first plurality of conductive features to form a first conductive path through the first photonic die; bonding a second photonic die to the first photonic die, wherein the second photonic die comprises: a second plurality of nitride waveguides, wherein the first silicon waveguide is optically coupled to the second plurality of nitride waveguides through the first plurality of nitride waveguides, the second plurality of nitride waveguides forming a second optical path through the second photonic die, wherein the second optical path is optically coupled to the first optical path for transmission through the first photonic die; forming a second via extending into a second plurality of dielectric layers in the second photonic die and a second plurality of conductive features to form a second conductive path through the second photonic die; and An electronic die is bonded to the first photonic die, wherein the second via is electrically coupled to the electronic die through the first via, and wherein the electronic die includes circuitry for processing electrical signals from a photonic component, wherein the second conductive path is electrically connected to the electronic die through the first conductive path.

2. The method according to claim 1, wherein: The electronic die includes a first bond pad, and the first photonic die includes a second bond pad bonded to the first bond pad.

3. The method of claim 1 , wherein forming the first silicon waveguide comprises etching a silicon layer on an oxide layer of a base substrate, and the method further comprises forming a redistribution structure above the oxide layer, wherein the redistribution structure comprises a third plurality of dielectric layers and a plurality of redistribution lines in the third plurality of dielectric layers. The method of claim 3 , wherein etching the silicon layer further forms a grating coupler.

5. The method according to claim 3, wherein: The base substrate further includes a bulk silicon substrate beneath the oxide layer, and the method further includes removing the bulk silicon substrate before bonding the second photonic die to the first photonic die.

6. The method according to claim 3, wherein: The base substrate further includes a bulk silicon substrate below the oxide layer, and the method further includes, before bonding the second photonic die to the first photonic die: thinning the bulk silicon substrate; and The thinned bulk silicon substrate is etched to form a second silicon waveguide.

7. The method according to claim 6, wherein: The second silicon waveguide optically couples the second plurality of nitride waveguides to the first silicon waveguide.

8. The method according to claim 1, wherein: The first plurality of nitride waveguides include silicon nitride and silicon oxynitride.

9. The method according to claim 8, wherein: The second plurality of nitride waveguides include silicon nitride and silicon oxynitride.

10. The method of claim 1, further comprising attaching a photonic assembly, wherein the photonic assembly comprises a light-emitting region aligned with the second plurality of nitride waveguides, and wherein the second plurality of nitride waveguides are configured to receive light beams emitted from the light-emitting region.

11. The method of claim 1 , further comprising attaching a silicon support substrate, wherein the second photonic die and the silicon support substrate are located on opposite sides of the first photonic die.

12. A package comprising: The first photonic die, comprising: The first silicon waveguide; a first plurality of dielectric layers disposed beneath the first silicon waveguide; a first plurality of nitride waveguides, each of the first plurality of nitride waveguides being in one of the first plurality of dielectric layers, wherein the first plurality of nitride waveguides form a first optical path through the first photonic die; and a first via and a first plurality of conductive features, the first via penetrating the first plurality of dielectric layers and the first via and the first plurality of conductive features forming a first conductive path penetrating the first photonic die; A second photonic die is located below the first photonic die and bonded to the first photonic die, wherein the second photonic die comprises: a second plurality of dielectric layers; a second plurality of nitride waveguides, each of the second plurality of nitride waveguides being located in one of the second plurality of dielectric layers, wherein the second plurality of nitride waveguides are optically coupled to the first silicon waveguide through the first plurality of nitride waveguides, the second plurality of nitride waveguides forming a second optical path through the second photonic die, wherein the second optical path is optically coupled to the first optical path for transmission through the first photonic die; and a second via and a second plurality of conductive features, the second via passing through the second plurality of dielectric layers, and the second via and the second plurality of conductive features forming a second conductive path through the second photonic die; a conductive component located below the second through hole and electrically connected to the first through hole through the second through hole; and An electronic die is located over and bonded to the first photonic die, wherein the second via is electrically connected to the electronic die through the first via, and wherein the second conductive path is electrically connected to the electronic die through the first conductive path.

13. The package according to claim 12, wherein: The electronic die includes a first bond pad, and the first photonic die includes a second bond pad bonded to the first bond pad.

14. The package of claim 12, further comprising a photonic assembly, wherein the photonic assembly comprises a light-emitting region aligned with the second plurality of nitride waveguides, and wherein the second plurality of nitride waveguides are configured to receive light beams emitted from the light-emitting region.

15. The package of claim 14, wherein the first photonic die and the second photonic die are configured to optically transmit the optical beam to the first silicon waveguide.

16. The package of claim 12 further comprising a second silicon waveguide located in a dielectric layer of the second plurality of dielectric layers.

17. A package comprising: Electronic tube die; a plurality of photonic dies stacked to form a die stack, wherein the electronic die is bonded to a top photonic die in the die stack, and wherein each of the plurality of photonic dies comprises: multiple dielectric layers; a conductive path passing through the plurality of dielectric layers, wherein the conductive path comprises a first conductive path passing through a first photonic die among the plurality of photonic die and a second conductive path passing through a second photonic die below the first photonic die, wherein the second conductive path is electrically connected to the electronic die through the first conductive path; and a plurality of nitride waveguides, wherein the plurality of nitride waveguides in the plurality of photonic dies are optically coupled and configured to transmit light in a bottom die in the plurality of photonic dies to a top photonic die in the plurality of photonic dies, wherein the plurality of nitride waveguides form a first optical path penetrating the first photonic die and a second optical path penetrating the second photonic die, wherein the second optical path is optically coupled to the first optical path for transmission through the first photonic die; a laser diode including a light-emitting region aligned with a light-receiving nitride waveguide in one of the plurality of photonic dies, wherein the laser diode and the one of the plurality of photonic dies are configured to allow the light-receiving nitride waveguide to receive a light beam emitted from the light-emitting region; and Optical glue fills the space between the laser diode and the nitride waveguide.

18. The package of claim 17, wherein one of the plurality of photonic dies further comprises a silicon waveguide.

19. The package of claim 17, further comprising a support substrate bonded over the electronic die, wherein: The supporting substrate includes a silicon substrate.

20. The package of claim 19, further comprising a microlens in the silicon substrate.

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