Multi-channel data stream configuration method, circuit architecture, apparatus, medium and terminal

Abstract

The application provides a multi-channel data stream configuration method, a circuit architecture, a device, a medium and a terminal, faces MIPI CSI-2 protocol, aims at the problems of poor flexibility and insufficient configurable capacity in traditional MIPI CSI-2 protocol design, introduces additional read-write control logic and a cache matrix, and adopts the control mode of multiple read pointers, flexibly realizes the segmentation of data streams, and simultaneously well adapts to the change of the number of channels and the transmission demand caused by different data formats, guarantees the continuity and integrity of data transmission; for the buffer register group used in the protocol design, the application builds a data stream package and a circular buffer area, effectively improves the flexibility and configuration function of the MIPI circuit without introducing more storage units, and balances the operation speed and resource consumption; through the pipeline structure, the read-write control module and the circular buffer area, the circuit architecture of the package layer is constructed, the flexibility, continuity and correctness of the read data stream are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit chip design, and in particular to a multi-channel data stream configuration method, circuit architecture, device, medium and terminal. BACKGROUND

[0002] In recent years, with the development of high-tech information technology, the requirements for camera sensor resolution in the fields of artificial intelligence, computer vision, autonomous driving, security monitoring and mobile devices are increasing. The CSI-2 (Camera Serial Interface 2) high-definition camera based on the MIPI (Mobile Industry Processor Interface) protocol solves the contradiction between the high-bandwidth requirement of high-definition image (video) transmission and the low rate of traditional interfaces, and provides a unified standard for the entire industry, thereby shortening the product development cycle and enhancing the compatibility of products from different manufacturers. Today, CSI-2 high-definition cameras are widely used in various embedded image devices, such as smartphones, televisions, wearable devices, virtual reality technology products, ADAS systems, etc. Due to the increasing complexity of application scenarios, the requirements for transmission rate and extremely low power consumption are becoming higher and higher, and the design complexity is continuously increasing, which brings very serious challenges to traditional MIPI CSI-2 interface design and flexible data volume delivery.

[0003] According to the MIPI CSI-2 protocol specification, the MIPI circuit architecture can be basically divided into an application layer, a packetizing layer, a protocol layer and a channel management layer. The MIPI packetizing module completes the reorganization, packaging and sending of high-speed data according to the requirements of the protocol, and plays an important role on the data link. It has very close interaction with other modules, acts as a front end of the MIPI digital module to complete reception and connection, and also generates data that meets the protocol specification by packaging scattered data according to certain protocol requirements. Since the final MIPI output can be a channel or multiple channels, when it is multiple channels, each channel needs to be assigned data in a certain order, and needs to be flexibly adapted when the number of channels changes; in addition, because the number of rows of data transmitted is diverse, there are various data formats, such as four channels, the last transmission can not be an integer multiple of four bytes, and there can be three bytes, two bytes or one byte left, which also needs to adapt to different sending requirements caused by different numbers of data and different channel assignments, so how to skillfully plan and interact with other modules during the design process is a problem that needs to be solved.

[0004] Early MIPI interface implementation based on ASIC and FPGA mainly focuses on the realization of the function level and the improvement of single channel rate, and there is no research on the flexible configuration of the number of channels and the packaging and sending of scattered data flow. Moreover, since the existing mature MIPI CSI-2 IP core supports at most 4-channel data transmission, especially in the case of fewer channels, the channel configuration and scattered data flow problem is not complex, but as the number of channels increases to 8 channels or even 16 channels, the complexity of such problems will be greatly improved, and it is very important to reasonably design the MIPI packaging layer circuit architecture for the entire protocol. SUMMARY

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a multi-channel data flow configuration method, circuit architecture, device, medium and terminal, which solves the technical problem of insufficient flexibility of data channel configuration of the traditional MIPI CSI-2 protocol.

[0006] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a multi-channel data flow configuration method applied to the MIPI CSI-2 protocol, the method comprising: obtaining a data flow to be configured; storing the data flow to be configured in sequence to construct a circular buffer matrix; and reading data in the circular buffer matrix based on the number of current data channels using a plurality of read pointers.

[0007] In some embodiments of the first aspect of the present application, the construction of the circular buffer matrix comprises: controlling the write operation of the data flow to be configured to write the data flow to be configured into a storage unit in sequence to form a buffer matrix; and letting the first bit of the read address point to the first row of the buffer matrix, and sequentially, until the last bit of the read address points to the last row of the buffer matrix, and the last row includes the first storage unit of the first row, to obtain a circular buffer matrix.

[0008] In some embodiments of the first aspect of the present application, the reading mode of the circular buffer matrix comprises: setting the number of read pointers based on the number of data channels, and the address of each read pointer is uniformly set corresponding to the number of data channels and is superimposed synchronously with the reading of data.

[0009] In some embodiments of the first aspect of the present application, the multi-channel data flow configuration method comprises: in the case that the number of current data channels is lower than a preset value, part of the plurality of read pointers functions to control the read operation; and part of the plurality of read pointers does not function to control the read operation.

[0010] To achieve the above object and other related objects, the second aspect of the present application provides a circuit architecture of multi-channel data stream configuration, comprising: a cutting module configured to cut a data stream to be configured; a packing module configured to arrange the cut data stream and deliver it outward; an encapsulating module configured to encapsulate data output by the packing module with corresponding header information and trailer information; and a read-write control module configured to form a cache matrix according to a certain order based on the encapsulated data, and output data based on a current number of data channels.

[0011] In some embodiments of the second aspect of the present application, the read-write control module comprises a write control module, a cache matrix module and a read control module; the write control module writes encapsulated data streams in sequence to a storage unit; the cache matrix module integrates and packs data sent by the write control module, and forms a cache matrix; and the read control module controls reading of data.

[0012] In some embodiments of the second aspect of the present application, the circuit architecture of multi-channel data stream configuration further comprises: a header generation module configured to generate header information and send it to the encapsulating module; a cyclic redundancy check module configured to receive data sent by the packing module, and generate corresponding trailer information and send it to the encapsulating module; the trailer information comprises a cyclic redundancy check sequence for data checking; and a first-in-first-out stack module configured to output pre-stored data streams to the cutting module.

[0013] To achieve the above object and other related objects, the third aspect of the present application provides a multi-channel data stream configuration device, comprising: a data acquisition module configured to acquire a data stream to be configured; a data storage module configured to store the data stream to be configured in sequence to form a circular cache matrix; and a data reading module configured to read data in the circular cache matrix based on a current number of data channels by using multiple read pointers.

[0014] To achieve the above object and other related objects, the fourth aspect of the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the multi-channel data stream configuration method.

[0015] To achieve the above object and other related objects, the fifth aspect of the present application provides an electronic terminal, comprising: a processor and a memory; the memory is configured to store a computer program, and the processor is configured to execute the computer program stored in the memory, so that the terminal executes the multi-channel data stream configuration method.

[0016] The application relates to a multi-channel data stream configuration method, a circuit architecture, a device, a medium and a terminal, and has the following beneficial effects: in view of the poor flexibility and insufficient configurable capacity of a traditional MIPI CSI-2 protocol design, the application introduces additional read-write control logic and a storage matrix, and adopts a control mode of multiple read pointers, thereby flexibly realizing the segmentation of a data stream, well adapting to the transmission requirements caused by the changes of different channel numbers and different data formats, and guaranteeing the continuity and integrity of data transmission; in view of the buffer register group adopted in the protocol design, the application builds a data stream packaging and a loop buffer area, thereby effectively improving the flexibility and configuration function of the MIPI circuit without introducing more storage units, and achieving a balance in operation speed and resource consumption; a packet layer circuit design architecture for the MIPI CSI-2 protocol is provided, and the flexibility, continuity and correctness of read data stream are improved through a pipeline architecture, a read-write control module and a loop buffer area. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A flowchart of a multi-channel data stream configuration method for a MIPI protocol is shown.

[0018] Figure 2 A circuit architecture diagram of a MIPI CSI-2 packet layer is shown.

[0019] Figure 3 A circuit structure diagram of a read-write control module is shown.

[0020] Figure 4 A cache matrix structure diagram is shown.

[0021] Figure 5 A data stream read flowchart is shown.

[0022] Figure 6 A structure diagram of a multi-channel data stream configuration device is shown.

[0023] Figure 7 A structure diagram of an electronic terminal is shown. DETAILED DESCRIPTION

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0025] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the present invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used in the text to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0026] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," and "holding" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0027] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0028] This invention proposes a multi-channel data stream configuration method, circuit architecture, device, medium, and terminal to solve the technical problem of insufficient flexibility in data channel configuration of the traditional MIPI CSI-2 protocol.

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0030] Example 1

[0031] like Figure 1 As shown, this embodiment proposes a multi-channel data stream configuration method for the MIPI protocol to adapt to different transmission requirements under different data lengths or different data channel allocations. The specific steps of this multi-channel data stream configuration method for the MIPI protocol include steps S11 to S13, which can be described as follows:

[0032] Step S11. Obtain the data stream to be configured. A data stream is an ordered sequence of bytes with a start and an end, including input streams, output streams, and buffered streams. It can also be classified as byte streams and character streams according to the type of data it reads and writes. Different data properties and formats require different processing methods for the data stream. This embodiment is oriented towards the MIPI CSI-2 protocol, therefore the data stream to be configured is generally a video data stream (image data stream).

[0033] In a preferred embodiment of this example, the method for obtaining the data stream to be configured includes: preprocessing the original video data to obtain the original FIFO (First-In-First-Out) data stream; dividing the original FIFO data stream into segments; performing Cyclic Redundancy Check (CRC) on the segmented data to generate corresponding packet tail information and generating corresponding packet header information; and encapsulating the segmented data and the corresponding generated packet header and packet tail information to obtain the data stream to be configured.

[0034] Step S12. Store the data stream to be configured sequentially to construct a circular cache matrix. The order generally refers to the temporal order of the data stream, determined by the continuous transmission characteristics of the data stream itself. Specifically, control the write operation of the data stream to be configured to write the data stream to be configured sequentially into storage units to form a cache matrix; and set the first bit of the read address to point to the first row of the cache matrix, and so on, until the last bit of the read address points to the last row of the cache matrix, and the last row includes the first storage unit of the first row, to obtain a circular cache matrix. Preferably, the circular buffer is contiguous and has a fixed size to avoid unnecessary space waste and information redundancy caused by repeated data storage.

[0035] Step S13. Reading data in the circular buffer matrix based on the number of current data channels using multiple read pointers. Specifically, the read operation of data is controlled by a read enable signal and a read address, the read pointers are set to adapt to the number of data channels, and the address of each read pointer is uniformly set according to the number of data channels and is superimposed and synchronized with the reading of data.

[0036] In the preferred embodiment of the present embodiment, the pointers are flexibly adjusted according to the number of current data channels. When the number of current data channels is less than a preset value, part of the multiple read pointers function to control the read operation; part of the multiple read pointers do not function to control the read operation, thereby adapting to the number of current data channels and flexibly controlling the reading and output of data.

[0037] For example, when there are eight data channels, two read pointers (read pointer 1 and read pointer 2) can be set; when there are sixteen data channels, four read pointers can be set. For another example, when eight data channels read eight bits of data at a time, the address of read pointer 2 is read pointer 1 plus four, and every time one data is read, the two read pointers increase by four at a time, and two groups of data, i.e., two groups of four buffer register data, are read, and the two highest Byte data correspond to channel eight and channel four, respectively, and then decrease in turn; when four channels read four Bytes at a time or two channels read two Bytes at a time, read pointer 2 no longer functions, and only read pointer 1 controls the read operation, and when there are two channels, the read pointer increases by two at a time, and when there are four channels, the read pointer increases by four at a time.

[0038] In some embodiments, the method can be applied to a controller, such as an ARM (Advanced RISC Machines) controller, an FPGA (Field Programmable Gate Array) controller, a SoC (System on Chip) controller, a DSP (Digital Signal Processing) controller, or an MCU (Microcontroller Unit) controller, etc. In some embodiments, the method can also be applied to a computer including components such as memory, a memory controller, one or more processing units (CPUs), peripheral interfaces, RF circuitry, audio circuitry, speakers, microphones, input / output (I / O) subsystems, displays, other output or control devices, and external ports; the computer includes, but is not limited to, personal computers such as desktop computers, laptops, tablets, smartphones, smart TVs, and personal digital assistants (PDAs). In other embodiments, the method can also be applied to a server, which can be deployed on one or more physical servers based on factors such as function and load, or can be composed of distributed or centralized server clusters.

[0039] Example 2

[0040] like Figure 2 As shown in the diagram, this embodiment proposes a schematic diagram of the overall circuit architecture of the MIPI CSI-2 packet layer based on a pipeline structure. The solid lines represent the internal modules of the packet layer; the solid arrows represent the data paths; and the dashed lines represent the modules that interact with the packet layer, such as the header module (packet header generation module), the cyclic redundancy check (CRC) module, and the first-in-first-out (FIFO) stack module. The header module is used to generate packet header information for the protocol module, the cyclic redundancy check module is used to receive the data sent by the packet module and generate a CRC sequence appended to the packet tail for data verification, and the FIFO module is mainly used to output the data stream processed by the front-end modules.

[0041] The group package layer includes four functional modules: a slicing module, a packet module, a packaging module and a read-write control module (W / R_CTL), wherein the slicing module is used to cut the asynchronous FIFO data stream input by the FIFO module; the packet module is used to arrange the cut data stream and deliver it to other modules, for example, for 10bit pixel data stream in YUV format, the original 40bit data needs to be divided into four parts, and each part takes the lower two bits to synthesize an 8bit data, and each part of the remaining 8bit data is a part; the packaging module combines the received header information, tail information and the data arranged by the packet module; the W / R_CTL module is the most important part, which forms a circular buffer matrix according to a certain order for the data added with the header information and the tail information by the packaging module, and fully considers the influence of different number of rows and different number of channels on data reading to read the data.

[0042] As shown in Figure 3 , the embodiment proposes a circuit structure diagram of a read-write control module, which includes a write control module (Wr_ctrl), a buffer matrix module and a read control module (Rd_ctrl), and the specific working process is as follows:

[0043] The Wr_ctrl module is controlled by a write enable signal Wr_en and a write address signal Wr_addr, and writes the packaged continuous data stream (such as byte0, byte1, byte2, byte3, byte4) into a storage unit (such as f0-f31, thirty-two eight-bit storage units) according to a certain order.

[0044] The buffer matrix module integrates and packages the data sent by the Wr_ctrl module through the Package, and constructs a circular buffer matrix. As shown in Figure 4 , the embodiment takes the data stored in the thirty-two eight-bit storage units f0-f31 as an example to give a buffer matrix structure diagram, wherein the first bit 5’d0 of the read address signal (Read_addr) rd_dat points to the four eight-bit buffers f0-f3, and the last bit 5’d31 of the read address signal (Read_addr) rd_dat points to the four eight-bit buffers f31-f2, thereby constructing a cycle and realizing the function similar to the ring buffer. When constructing the buffer matrix, each eight-bit data does not need to be repeatedly stored four times, the ring buffer is connected at the head and tail and has a fixed size, and only a read pointer needs to be additionally introduced to control the range of reading data.

[0045] The Rd_ctrl module: To accommodate different data formats, lengths, and channel numbers, the Rd_ctrl module is controlled by the enable signal Rd_en and the read address signal Read_addr, and uses two read pointers (first read pointer A1 and second read pointer A2) to control data reading. For example... Figure 5 As shown in the figure, this embodiment provides a schematic diagram of a data stream reading process, to Figure 3 Taking the constructed cache matrix as an example, when eight channels (Data_lane0, Data_lane1, ..., Data_lane6, Data_lane7) read eight bits of data at a time, the address of the second read pointer A2 is the first read pointer A1 plus four. Each time data is read, both read pointers increment by four, resulting in two sets of data (two sets of four buffer register data). The two highest-order bits correspond to channels 8 and 4 respectively, and then the values ​​decrease sequentially to correspond to channels 7, 6, 5 or 3, 2, 1. When four channels read four bits at a time, or two channels read two bits at a time, the second read pointer A2 no longer functions; only the first read pointer A1 controls the read operation. With two channels, the first read pointer A1 increments by two after each data read; with four channels, the first read pointer A1 increments by four after each data read. Subsequent data modules also process the data according to the activation status of the eight channels.

[0046] In summary, in this embodiment, the read / write control module writes a loosely distributed data stream into multiple buffer registers in a specific order to accommodate changes in the number of data channels. Finally, it reads the data according to these changes, pointing to a preset group of buffer registers each time it reads. Each group of read data corresponds one-to-one with each current data channel, thus achieving flexible, continuous, and accurate data reading, and enabling flexible configuration of multi-channel data streams.

[0047] Example 3

[0048] like Figure 6 As shown, this embodiment proposes a multi-channel data stream configuration device, including: a data acquisition module 61, used to acquire the data stream to be configured; a data storage module 62, used to store the data stream to be configured in sequence to construct a circular cache matrix; and a data reading module 63, used to read the data in the circular cache matrix using multiple read pointers based on the current number of data channels.

[0049] It should be noted that the modules provided in the embodiments are similar to the methods and embodiments provided in the foregoing, and thus will not be described again. In addition, it should be understood that the division of each module of the above device is only a logical division of functions, and all or part of the modules can be integrated into one physical entity, or can be physically separated. The modules can all be implemented in the form of software invoked by a processing element, or all be implemented in the form of hardware, or part of the modules are implemented in the form of software invoked by a processing element, and part of the modules are implemented in the form of hardware. For example, the data reading module can be a separately established processing element, or can be integrated in a chip of the above device, and in addition, the data reading module can be stored in the form of program code in the memory of the above device, and the function of the data reading module is invoked and executed by a processing element of the above device. The implementation of other modules is similar. In addition, all or part of the modules can be integrated together, or can be independently implemented. The processing element described herein can be an integrated circuit having a signal processing capability. In the implementation process, each step of the above method or each module can be completed by an integrated logic circuit of hardware in the processing element or an instruction in the form of software.

[0050] For example, the modules can be one or more integrated circuits configured to implement the above method, such as one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), etc. For another example, when a certain module is implemented in the form of program code invoked by a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of invoking program code. For another example, the modules can be integrated together to implement a system-on-a-chip (SOC).

[0051] Embodiment Four

[0052] The embodiment provides a computer readable storage medium, and a computer program is stored in the computer readable storage medium. The computer program is executed by a processor to implement the multi-channel data stream configuration method.

[0053] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by the hardware related to the computer program. The foregoing computer program can be stored in a computer readable storage medium. The program executes the steps of the above-mentioned method embodiments when executed; and the foregoing storage medium includes ROM, RAM, magnetic disk or optical disk and various media that can store program codes.

[0054] Embodiment five

[0055] As Figure 7 shown, the embodiment of the present application provides a structural schematic diagram of an electronic terminal. The electronic terminal provided by the embodiment includes a processor 71, a memory 72 and a communicator 73. The memory 72 is connected with the processor 71 and the communicator 73 through a system bus and completes the communication between each other. The memory 72 is used for storing a computer program. The communicator 73 is used for communicating with other devices. The processor 71 is used for running the computer program, so that the electronic terminal executes each step of the above multi-channel data stream configuration method.

[0056] The system bus mentioned above can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The system bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus. The communication interface is used for realizing the communication between the database access device and other devices (for example, a client, a read-write library and a read-only library). The memory can include a random access memory (RAM), and can also include a non-volatile memory, for example, at least one disk memory.

[0057] The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0058] In summary, the present application provides a multi-channel data stream configuration method, a circuit architecture, a device, a medium and a terminal. In view of the poor flexibility and insufficient configurable capacity in the conventional MIPI CSI-2 protocol design, the present application introduces additional read-write control logic and a storage matrix, and adopts a control mode of two read pointers, thereby flexibly realizing the segmentation of data streams, and well adapting to the transmission requirements caused by the changes in the number of channels and different data formats, and ensuring the continuity and integrity of data transmission. In view of the buffer register group used in the protocol design, the present application builds a data stream packaging and a circular buffer area, thereby effectively improving the flexibility and configuration function of the MIPI circuit without introducing more storage units, and achieving a balance in the operation speed and resource consumption. A packet layer circuit design architecture for the MIPI CSI-2 protocol is proposed, and through the pipeline architecture, the read-write control module and the circular buffer area, the flexibility, continuity and correctness of the read data stream are improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0059] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of configuring a multi-lane data stream, the method comprising: The method is applied to the MIPI CSI-2 protocol, and the method comprises the following steps: Obtaining a data stream to be configured; Storing the data stream to be configured in sequence to construct a circular buffer matrix; Reading data in the circular buffer matrix by using a plurality of read pointers based on the number of current data channels; The construction mode of the circular buffer matrix comprises: controlling the write operation of the data stream to be configured to write the data stream to be configured in sequence into a storage unit to form a buffer matrix; and the first bit of the read address points to the first row of the buffer matrix, and the last bit of the read address points to the last row of the buffer matrix, and the last row comprises the first storage unit of the first row, so as to obtain a circular buffer matrix; The reading mode of the circular buffer matrix comprises: setting the number of read pointers based on the number of data channels, and the addresses of the read pointers are uniformly set corresponding to the number of data channels and are synchronously superimposed with the reading of data.

2. The method of claim 1, wherein, Comprise: In the case that the number of current data channels is lower than a preset value, part of the plurality of read pointers functions to control the read operation; Part of the plurality of read pointers does not function to control the read operation.

3. A circuit architecture for a multi-lane data stream configuration, the circuit architecture comprising: Comprise: A cutting module for cutting the data stream to be configured; A packaging module for arranging the cut data stream and delivering it outward; An encapsulation module for encapsulating the data output by the packaging module with the corresponding header information and trailer information thereof; A read-write control module for constructing a circular buffer matrix from the encapsulated data of the encapsulation module in a certain order, reading data in the circular buffer matrix by using a plurality of read pointers based on the number of current data channels, and outputting the data; The construction mode of the circular buffer matrix comprises: controlling the write operation of the data stream to be configured to write the data stream to be configured in sequence into a storage unit to form a buffer matrix; and the first bit of the read address points to the first row of the buffer matrix, and the last bit of the read address points to the last row of the buffer matrix, and the last row comprises the first storage unit of the first row, so as to obtain a circular buffer matrix; The reading mode of the circular buffer matrix comprises: setting the number of read pointers based on the number of data channels, and the addresses of the read pointers are uniformly set corresponding to the number of data channels and are synchronously superimposed with the reading of data.

4. The circuit architecture of claim 3, wherein, The read-write control module comprises a write control module, a buffer matrix module and a read control module; wherein the write control module writes the encapsulated data stream in sequence into a storage unit; the buffer matrix module integrates and packages the data sent by the write control module, and constructs a circular buffer matrix; and the read control module controls the reading of data.

5. The circuit architecture of claim 3, wherein, Further comprise: A header generation module for generating header information and sending it to the encapsulation module; A cyclic redundancy check module for receiving the data sent by the packaging module, generating corresponding trailer information and sending it to the encapsulation module; the trailer information comprises a cyclic redundancy check sequence for data verification; A first-in first-out stack module for outputting the pre-stored data stream to the cutting module.

6. A multi-lane data stream configuration apparatus, characterized by comprising: Comprise: A data acquisition module for acquiring a data stream to be configured; a data storage module, configured to store the to-be-configured data stream in sequence to build a circular buffer matrix; a data reading module, configured to read data in the circular buffer matrix by using a plurality of reading pointers based on a number of current data channels; the circular buffer matrix is built in the following manner: a write operation of the to-be-configured data stream is controlled to write the to-be-configured data stream in sequence into a storage unit to form a buffer matrix; and a first bit of a reading address points to a first row of the buffer matrix, and a last bit of the reading address points to a last row of the buffer matrix, and the last row includes a first storage unit of the first row, so as to obtain the circular buffer matrix; the circular buffer matrix is read in the following manner: a number of the reading pointers is set based on a number of data channels, and addresses of the reading pointers are uniformly set according to the number of the data channels and are synchronously superimposed along with reading of data.

7. A computer-readable storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the multi-channel data stream configuration method of claim 1 or 2.

8. An electronic terminal, characterized in that comprise: a processor and a memory; the memory is configured to store a computer program, and the processor is configured to execute the computer program stored in the memory, so that the terminal executes the multi-channel data stream configuration method of claim 1 or 2.

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