Graphics unit structure and graphics array structure

Abstract

The present invention discloses a graphic unit structure and a graphic array structure. The graphic unit structure comprises: a first graphic comprises a first part and a second part which are perpendicular to each other, the end of the first part of the first graphic is connected to the beginning of the second part of the first graphic; the orthographic projection of the first interconnection structure on the first graphic is located in the second part of the first graphic; the second graphic comprises a first part and a second part which are perpendicular to each other, the end of the first part of the second graphic is connected to the beginning of the second part of the second graphic; the orthographic projection of the second interconnection structure on the second part of the second graphic is located in the second part of the second graphic; the third graphic is located between the first graphic and the second graphic. When reliability testing is performed after wafer preparation is completed, a smaller spacing can avoid the occurrence of voids that cause the interconnection structure to fall off and the upper metal film layer to be lifted up after the interconnection structure falls off, thereby improving the reliability and life of the wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a graphic unit structure and a graphic array structure. Background Art

[0002] With the rapid development of semiconductor storage technology, the market has put forward higher requirements on the storage capacity of semiconductor storage products. For dynamic random access memory (DRAM), in the back end of line (BEOL) process, the upper and lower adjacent multi-layer metal layers are electrically connected through the interconnection structure to complete the preparation of the wafer.

[0003] However, the spacing between the graphic structures of the traditional BEOL layout with interconnected structures is too wide. After the BEOL layout is completed, the passivation layer is deposited to complete the wafer preparation. When conducting reliability tests, such as the Unbiased High Accelerated Stress Test (UHAST) under high temperature and high humidity conditions, the wide spacing area will cause voids in the passivation layer, and the voids will cause the interconnected structure to fall off, causing the prepared wafer to age severely and fail the reliability test. Summary of the invention

[0004] Based on this, it is necessary to provide a graphic unit structure and a graphic array structure to address the problems in the above-mentioned background technology, solve the problem of voids in the passivation layer caused by excessively wide spacing areas, causing the interconnection structure to fall off, and improve the wafer life.

[0005] In order to solve the above technical problems, the first aspect of the present application proposes a graphic unit structure, comprising:

[0006] A first figure, wherein the first figure includes a first part and a second part that are perpendicular to each other, an end of the first part of the first figure is connected to a beginning of the second part of the first figure, and the second part of the first figure extends along a first direction; an orthographic projection of the first interconnection structure on the first figure is located in the second part of the first figure;

[0007] a second figure, wherein the second figure includes a first part and a second part that are perpendicular to each other, the end of the first part of the second figure is connected to the beginning of the second part of the second figure, the first part of the second figure is arranged in parallel with the first part of the first figure, and the second part of the second figure extends along a second direction, which is opposite to the first direction; and the orthographic projection of the second interconnection structure on the second figure is located in the second part of the second figure;

[0008] The third graphic is located between the first graphic and the second graphic.

[0009] In the graphic unit structure provided in the above embodiment, the first part and the second part of the first graphic are perpendicular to each other, the end of the first part of the first graphic is connected to the beginning of the second part of the first graphic, the second part of the first graphic extends along the first direction, and the orthographic projection of the first interconnection structure on the first graphic is located in the second part of the first graphic; the first part and the second part of the second graphic are perpendicular to each other, the end of the first part of the second graphic is connected to the beginning of the second part of the second graphic, the second part of the second graphic extends along the second direction, the first direction is opposite to the second direction, and the orthographic projection of the second interconnection structure of the second graphic on the second graphic is located in the second part of the second graphic; the third graphic is located between the first graphic and the second graphic. Compared with the traditional graphic layout structure, the layout method of the graphic unit structure of the present application makes the spacing between each graphic smaller. The smaller spacing avoids the occurrence of voids that cause the interconnection structure to fall off and the upper metal film layer to be lifted up after the interconnection structure falls off when the reliability test is performed after the wafer preparation is completed, thereby improving the reliability and life of the wafer.

[0010] In one embodiment, the third figure includes a first part and a second part that are perpendicular to each other, the first part of the third figure is vertically connected to the second part of the third figure, the first part of the third figure is parallel to the first part of the first figure and the first part of the second figure, and the second part of the third figure is parallel to the second part of the first figure and the second part of the second figure.

[0011] In one embodiment, the orthographic projection of the third interconnect structure on the third figure is located in the second portion of the third figure and is symmetrically located on both sides of the center line of the first portion of the third figure.

[0012] In one embodiment, the first interconnection structure, the second interconnection structure and the third interconnection structure are all multiple, the multiple first interconnection structures are arranged at intervals along the length direction of the second part of the first figure, the multiple second interconnection structures are arranged at intervals along the length direction of the second part of the second figure, and the multiple third interconnection structures are arranged at intervals along the length direction of the second part of the third figure.

[0013] In one embodiment, the length of the second portion of the third figure is greater than the width of the first portion of the third figure.

[0014] In one embodiment, the center line of the first part of the third figure coincides with the center line of the second part of the third figure; the first figure and the second figure are symmetrically distributed with respect to the center line of the third figure; the projections of the second part of the first figure and the second part of the second figure in the length direction of the second part of the third figure partially coincide with the second part of the third figure.

[0015] In one embodiment, there is a first spacing between the end of the second portion of the first figure and the end of the second portion of the second figure, there is a second spacing between the second portion of the first figure and the second portion of the second figure and the second portion of the third figure, and the ratio of the first spacing to the second spacing is 0.9-1.1;

[0016] There is a third spacing between the first portion of the first figure, the first portion of the second figure, and the second portion of the third figure, and a ratio of the first spacing to the third spacing is 0.9-1.1.

[0017] In one embodiment, the third figure is in a straight line shape, and the third figure is arranged parallel to the first part of the first figure and the first part of the second figure.

[0018] In one embodiment, an orthographic projection of the third interconnect structure on the third figure is located within the third figure.

[0019] In one embodiment, the first interconnection structure, the second interconnection structure and the third interconnection structure are all multiple, the multiple first interconnection structures are arranged at intervals along the length direction of the second part of the first figure, the multiple second interconnection structures are arranged at intervals along the length direction of the second part of the second figure, and the multiple third interconnection structures are arranged at intervals along the length direction of the third figure.

[0020] In one embodiment, the second portion of the second figure and the second portion of the first figure overlap in the projection portion of the second portion of the first figure in the length direction; the third figure, the second portion of the first figure and the second portion of the second figure overlap in the projection portion of the second portion of the second figure in the length direction.

[0021] In one embodiment, the second portion of the first graphic is located between the second portion of the second graphic and the third graphic.

[0022] In one embodiment, there is a fourth spacing between the second portion of the first figure and the third figure, there is a fifth spacing between the second portion of the second figure and the second portion of the first figure, and a ratio of the fourth spacing to the fifth spacing is 0.9-1.1.

[0023] In one embodiment, the first pattern, the second pattern and the third pattern are located in the same metal layer.

[0024] In one embodiment, the graphic unit structure includes multiple layers of the first graphics arranged in parallel and spaced apart, multiple layers of the second graphics arranged in parallel and spaced apart, and multiple layers of the third graphics arranged in parallel and spaced apart; the first interconnection structure is located between adjacent first graphics, and the second interconnection structure is located between adjacent second graphics.

[0025] In one embodiment, a dielectric layer is disposed between adjacent first graphics, between adjacent second graphics, and between adjacent third graphics, and the first interconnect structure and the second interconnect structure are both located in the dielectric layer.

[0026] A second aspect of the present application provides a graphic array structure, comprising: a plurality of graphic unit structures as described above, wherein the plurality of graphic unit structures are arranged in an array.

[0027] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 A schematic diagram of a graphic unit structure provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of a graphic unit structure provided in another embodiment of the present application;

[0031] Figure 3 A schematic diagram of a graphic unit structure provided in yet another embodiment of the present application;

[0032] Figure 4 Schematic diagram of a graphic array structure provided in one embodiment of the present application.

[0033] Description of reference numerals: 10 - first graphic, 11 - first portion of first graphic, 12 - second portion of first image graphic, 13 - first interconnection structure;

[0034] 20 - a second graphic, 21 - a first portion of a second graphic, 22 - a second portion of a second graphic, 23 - a second interconnection structure;

[0035] 30 - a third graphic, 31 - a first portion of a third graphic, 32 - a second portion of a third graphic, 33 - a third interconnection structure. DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0039] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing, and the zones shown in the figures are schematic in nature, and their shapes are not intended to display the actual shapes of the zones of the device and are not intended to limit the scope of the application.

[0042] In the BEOL process, the layout of the graphic structure prepared by the prior art will make the spacing between the graphics too wide. The too wide spacing will easily cause voids to appear in the passivation layer after the deposited passivation layer and the overall wafer packaging. Larger voids will cause the nearby interconnection structure to fall off. The falling of the interconnection structure will easily lift up the metal layer on the upper surface of the silicon oxide film layer, causing the metal layer to warp. The metal layers on the upper and lower surfaces of the silicon oxide film layer cannot complete electrical connection, and a large number of gaps will appear near the warped metal layer. Even if the wafer is packaged, it still cannot work normally under harsh high temperature and high humidity environmental conditions.

[0043] See also Figure 1-Figure 4It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0044] In one embodiment of the present application, Figure 1 As shown, a graphic unit structure is proposed, including: a first graphic 10, a second graphic 20 and a third graphic 30. The first graphic 10 includes a first part 11 and a second part 12 which are perpendicular to each other, the end of the first part 11 of the first graphic is connected to the beginning of the second part 12 of the first graphic, and the second part 12 of the first graphic extends along a first direction A; the orthographic projection of the first interconnection structure 13 on the first graphic 10 is located in the second part 12 of the first graphic; the second graphic 20 includes a first part 21 and a second part 22 which are perpendicular to each other, the end of the first part 21 of the second graphic is connected to the beginning of the second part 22 of the second graphic, the first part 21 of the second graphic is arranged parallel to the first part of the first graphic, and the second part 22 of the second graphic extends along a second direction A', which is opposite to the first direction A; the orthographic projection of the second interconnection structure 23 on the second graphic 20 is located in the second part 22 of the second graphic; the third graphic 30 is located between the first graphic 10 and the second graphic 20.

[0045] In the graphic unit structure provided in the above embodiment, the first part and the second part of the first graphic are perpendicular to each other, the end of the first part of the first graphic is connected to the beginning of the second part of the first graphic, the second part of the first graphic extends along the first direction, and the orthographic projection of the first interconnection structure on the first graphic is located in the second part of the first graphic; the first part and the second part of the second graphic are perpendicular to each other, the end of the first part of the second graphic is connected to the beginning of the second part of the second graphic, the second part of the second graphic extends along the second direction, the first direction is opposite to the second direction, and the orthographic projection of the second interconnection structure of the second graphic on the second graphic is located in the second part of the second graphic; the third graphic is located between the first graphic and the second graphic. Compared with the traditional graphic layout structure, the layout method of the graphic unit structure of the present application makes the spacing between each graphic smaller. The smaller spacing can avoid the occurrence of voids that cause the interconnection structure to fall off and the upper metal film layer to be lifted up after the interconnection structure falls off when performing reliability testing after the wafer preparation is completed, thereby improving the reliability and life of the wafer.

[0046] As an example, the first graphic 10 and the second graphic 20 are both in an inverted L shape, so that the first graphic and the second graphic are close to each other, and the distance between the first graphic 10 and the second graphic is reduced. The width of the second part 12 of the first graphic can be the same as the width of the first part 11 of the first graphic, and the width of the second part 22 of the second graphic can be the same as the width of the first part 21 of the second graphic. Compared with the graphic structure of the first part 11 of the first graphic, the second part 12 of the first graphic is rotated 90 degrees to connect the end of the first part 11 of the first graphic to the beginning of the second part 12 of the first graphic, thereby improving the spacing area between the graphics to avoid the problem of the detachment of each interconnection structure.

[0047] In one embodiment, the first graphic 10, the second graphic 20 and the third graphic 30 are located in the same metal layer. The graphic unit structure also includes a plurality of first graphics 10 vertically stacked in parallel and spaced arrangement, a plurality of second graphics 20 parallel and spaced arrangement and a plurality of third graphics 30 parallel and spaced arrangement; the first interconnection structure 13 is located between adjacent first graphics 10, and the second interconnection structure 23 is located between adjacent second graphics 10. Specifically, the first interconnection structure 13 is formed below or above the second portion 12 of the first graphic, and the second interconnection structure 23 is formed below or above the second portion 22 of the second graphic.

[0048] In one embodiment, a dielectric layer (not shown) is disposed between adjacent first graphics 10 , between adjacent second graphics 20 , and between adjacent third graphics 30 , and the first interconnection structure 13 and the second interconnection structure 23 are both located in the dielectric layer.

[0049] As an example, the dielectric layer may include a first metal layer, a silicon oxide layer, and a second metal layer stacked in sequence from bottom to top, the first interconnect structure and the second interconnect structure penetrate the silicon oxide layer in the thickness direction, the top of the first interconnect structure and the top of the second interconnect structure are in contact with the second metal layer, the bottom of the first interconnect structure and the bottom of the second interconnect structure are in contact with the first metal layer, and the second metal layer is electrically connected to the first metal layer through the first interconnect structure and the second interconnect structure. The material of the first metal layer may include but is not limited to an alloy material of one of tungsten, copper, or aluminum or any combination thereof; the material of the second metal layer may include but is not limited to an alloy material of one of tungsten, copper, or aluminum or any combination thereof; the material of the first interconnect structure may include but is not limited to an alloy material of one of tungsten, copper, or aluminum or any combination thereof; the material of the second interconnect structure may include but is not limited to an alloy material of one of tungsten, copper, or aluminum or any combination thereof.

[0050] In one embodiment, Figure 2As shown, the third figure 30 is T-shaped, and the third figure 30 includes a first part 31 and a second part 32 that are perpendicular to each other. The first part 31 of the third figure is vertically connected to the second part 32 of the third figure. The first part 31 of the third figure is parallel to the first part 11 of the first figure and the first part 21 of the second figure. The second part 32 of the third figure is parallel to the second part 32 of the first figure and the second part 22 of the second figure.

[0051] Specifically, the third figure 30 further includes a third interconnection structure 33, the orthographic projection of the third interconnection structure 33 on the third figure 30 is located in the second portion 32 of the third figure and symmetrically located on both sides of the center line of the first portion 31 of the third figure.

[0052] Further, the first interconnection structure 13, the second interconnection structure 23 and the third interconnection structure 33 are all multiple, the multiple first interconnection structures 13 are arranged at intervals along the length direction of the second part 12 of the first figure, the multiple second interconnection structures 23 are arranged at intervals along the length direction of the second part 22 of the second figure, and the multiple third interconnection structures 33 are arranged at intervals along the length direction of the second part 32 of the third figure; wherein the length direction of the second part 12 of the first figure is the first direction A, the length direction of the second part 22 of the second figure is the second direction A', and the length direction of the second part 32 of the third figure is the first direction A and the second direction A'. As an example, each interconnection structure can be arranged at equal intervals along the length direction.

[0053] In one embodiment, the length of the second portion 32 of the third figure is greater than the width of the first portion 31 of the third figure, so that the distance from the second portion 32 of the third figure to the first portion 11 of the first figure is smaller than the distance from the first portion 31 of the third figure to the first portion 11 of the first figure.

[0054] In one embodiment, the center line of the first part 31 of the third figure coincides with the center line of the second part 32 of the third figure; the first figure 10 and the second figure 20 are symmetrically distributed with respect to the center line of the third figure 30; the projections of the second part 12 of the first figure and the second part 22 of the second figure in the length direction of the second part 32 of the third figure partially coincide with the second part 32 of the third figure respectively; specifically, the projection point of the end of the second part 12 of the first figure in the first direction A is located on the second part 32 of the third figure, and the projection point of the end of the second part 22 of the second figure in the second direction A' is located on the second part 32 of the third figure.

[0055] In one embodiment, please continue to refer to Figure 2, a first spacing D1 is formed between the end of the second portion 12 of the first figure and the end of the second portion 22 of the second figure, a second spacing D2 is formed between the second portion 12 of the first figure and the second portion 22 of the second figure and the second portion 32 of the third figure, and a ratio of the first spacing D1 to the second spacing D2 is 0.9-1.1; specifically, D1 / D2 is 0.9, 0.95, 1.0 or 1.1, etc. A third spacing D3 is formed between the first portion 11 of the first figure and the first portion 21 of the second figure and the second portion 32 of the third figure, and a ratio of the first spacing D1 to the third spacing D3 is 0.9-1.1. Specifically, D1 / D3 is 0.9, 0.95, 1.0 or 1.1, etc.

[0056] In one embodiment, Figure 3 As shown, the third figure 30 is in a straight line, and the third figure 30 is arranged parallel to the first portion 11 of the first figure and the first portion 21 of the second figure.

[0057] As an example, the width of the second part 12 of the first figure is the same as the width of the first part 11 of the first figure and the width of the third figure 30, and the width of the second part 22 of the second figure is the same as the width of the first part 21 of the second figure and the width of the third figure 30.

[0058] In one embodiment, the third figure 30 further includes a third interconnecting structure 33, and the orthographic projection of the third interconnecting structure 33 on the third figure 30 is located in the third figure 30. The first interconnecting structure 13, the second interconnecting structure 23, and the third interconnecting structure 33 are all multiple, and the multiple first interconnecting structures 13 are arranged at intervals along the length direction of the second portion 12 of the first figure, the multiple second interconnecting structures 23 are arranged at intervals along the length direction of the second portion 22 of the second figure, and the multiple third interconnecting structures 33 are arranged at intervals along the length direction of the third figure 30. As an example, each interconnecting structure can be arranged at equal intervals along the length direction.

[0059] In one embodiment, the second portion 22 of the second figure and the second portion 12 of the first figure overlap in the projection portion of the second portion 12 of the first figure in the length direction; the third figure 30, the second portion 12 of the first figure and the second portion 22 of the second figure overlap in the projection portion of the second portion 22 of the second figure in the length direction.

[0060] As an example, the projection point of the end of the second portion 12 of the first figure in the first direction A is located on the third figure 30, and the projection point of the end of the second portion 22 of the second figure in the second direction A′ is located on the second portion 12 of the first figure.

[0061] In one embodiment, the second portion 12 of the first figure is located between the second portion 22 of the second figure and the third figure 30. Specifically, the fourth spacing D4 is between the second portion 12 of the first figure and the third figure 30, the fifth spacing D5 is between the second portion 22 of the second figure and the second portion 12 of the first figure, and the ratio of the fourth spacing D4 to the fifth spacing D5 is 0.9-1.1. Specifically, D4 / D5 is 0.9, 0.95, 1.0 or 1.1, etc. The third figure 30 is respectively spaced from the first portion 11 of the first figure and the first portion 21 of the second figure 20 by a sixth spacing (not shown in the figure), and the ratio of the sixth spacing to the fourth spacing D4 and the fifth spacing D5 is 0.9-1.1. By setting each figure to a similar spacing, after the metal layers and interconnect structures stacked in sequence are formed based on each figure, the appearance of voids in the subsequently deposited passivation layer can be avoided.

[0062] As an example, the blank areas of the first pattern 10 , the second pattern 20 , and the third pattern 30 form an S-shaped space, which can improve the spacing area between the patterns to avoid the problem of the interconnection structures falling off.

[0063] In one embodiment of the present application, a graphic array structure is further proposed, comprising: a plurality of graphic unit structures as described above, wherein the plurality of graphic unit structures are arranged in an array, that is, the graphic unit structures composed of the first graphic, the second graphic, and the third graphic are arranged in sequence along the first direction or the second direction as units, such as Figure 4 The above is not limited to the above and is only presented as an example.

[0064] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0065] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0066] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A graphic unit structure, characterized in that: include: A first figure, wherein the first figure includes a first portion and a second portion that are perpendicular to each other, wherein an end of the first portion of the first figure is connected to a beginning of the second portion of the first figure, and the second portion of the first figure extends along a first direction; The orthographic projection of the first interconnection structure on the first figure is located within the second portion of the first figure; a second figure, the second figure comprising a first part and a second part perpendicular to each other, the end of the first part of the second figure being connected to the beginning of the second part of the second figure, the first part of the second figure being arranged parallel to the first part of the first figure, the second part of the second figure extending along a second direction, the second direction being opposite to the first direction; The orthographic projection of the second interconnect structure on the second figure is located within the second portion of the second figure; A third figure is located between the first figure and the second figure; the third figure includes a first part and a second part perpendicular to each other, the first part of the third figure is perpendicularly connected to the second part of the third figure, the first part of the third figure is parallel to the first part of the first figure and the first part of the second figure, the second part of the third figure is parallel to the second part of the first figure and the second part of the second figure, and the first part of the third figure extends along a third direction, which is perpendicular to the first direction and the second direction; The third graphic is a single conductive structure pattern; The center line of the first part of the third figure coincides with the center line of the second part of the third figure; The first figure and the second figure are symmetrically distributed with respect to the center line of the third figure; the projections of the second part of the first figure and the second part of the second figure in the third direction partially overlap with the second part of the third figure, and the projection of the second part of the first figure in the third direction does not exceed the boundary of the first part of the third figure close to the first part of the first figure, and the projection of the second part of the second figure in the third direction does not exceed the boundary of the first part of the third figure close to the first part of the second figure; There is a first spacing between the end of the second part of the first figure and the end of the second part of the second figure, there is a second spacing between the second part of the first figure and the second part of the second figure and the second part of the third figure, and the ratio of the first spacing to the second spacing is 0.9-1.1; There is a third spacing between the first portion of the first figure, the first portion of the second figure, and the second portion of the third figure, and a ratio of the first spacing to the third spacing is 0.9-1.

1.

2. The graphic unit structure according to claim 1, characterized in that: The orthographic projection of the third interconnection structure on the third figure is located in the second portion of the third figure and is symmetrically located on both sides of the center line of the first portion of the third figure.

3. The graphic unit structure according to claim 2, characterized in that: The first interconnection structure, the second interconnection structure and the third interconnection structure are all multiple, the multiple first interconnection structures are arranged at intervals along the length direction of the second part of the first figure, the multiple second interconnection structures are arranged at intervals along the length direction of the second part of the second figure, and the multiple third interconnection structures are arranged at intervals along the length direction of the second part of the third figure.

4. The graphic unit structure according to claim 2, characterized in that: The length of the second portion of the third figure is greater than the width of the first portion of the third figure.

5. A graphic unit structure, characterized in that: include: A first figure, wherein the first figure includes a first portion and a second portion that are perpendicular to each other, wherein an end of the first portion of the first figure is connected to a beginning of the second portion of the first figure, and the second portion of the first figure extends along a first direction; The orthographic projection of the first interconnection structure on the first figure is located within the second portion of the first figure; a second figure, the second figure comprising a first part and a second part perpendicular to each other, the end of the first part of the second figure being connected to the beginning of the second part of the second figure, the first part of the second figure being arranged parallel to the first part of the first figure, the second part of the second figure extending along a second direction, the second direction being opposite to the first direction; The orthographic projection of the second interconnect structure on the second figure is located within the second portion of the second figure; A third graphic, located between the first graphic and the second graphic; The third figure is in a straight line shape, the third figure is arranged parallel to the first part of the first figure and the first part of the second figure, and the third figure extends along a third direction, and the third direction is perpendicular to the first direction and the second direction; The third graphic is a single conductive structure pattern; The second part of the second figure and the projection part of the second part of the first figure in the length direction of the second part of the first figure overlap; The projections of the third figure, the second part of the first figure, and the second part of the second figure in the third direction partially overlap, and the projection of the third figure in the third direction does not completely fall into the projection of the second part of the first figure, and the projection of the third figure in the third direction does not completely fall into the projection of the second part of the second figure; The second portion of the first figure is located between the second portion of the second figure and the third figure; There is a fourth distance between the second part of the first figure and the third figure, there is a fifth distance between the second part of the second figure and the second part of the first figure, and a ratio of the fourth distance to the fifth distance is 0.9-1.1; There is a sixth spacing between the third figure and the first portion of the first figure and the first portion of the second figure, respectively. The ratio of the sixth spacing to the fourth spacing and the fifth spacing is 0.9-1.

1.

6. The graphic unit structure according to claim 5, characterized in that: The orthographic projection of the third interconnection structure on the third figure is located within the third figure.

7. The graphic unit structure according to claim 6, characterized in that: The first interconnection structure, the second interconnection structure and the third interconnection structure are all multiple, the multiple first interconnection structures are arranged at intervals along the length direction of the second part of the first figure, the multiple second interconnection structures are arranged at intervals along the length direction of the second part of the second figure, and the multiple third interconnection structures are arranged at intervals along the length direction of the third figure.

8. The graphic unit structure according to claim 1, characterized in that: The first pattern, the second pattern and the third pattern are located in the same metal layer.

9. The graphic unit structure according to claim 1, characterized in that: The graphic unit structure includes multiple layers of the first graphics arranged in parallel and spaced apart, multiple layers of the second graphics arranged in parallel and spaced apart, and multiple layers of the third graphics arranged in parallel and spaced apart; the first interconnection structure is located between adjacent first graphics, and the second interconnection structure is located between adjacent second graphics.

10. The graphic unit structure according to claim 9, characterized in that: A dielectric layer is disposed between adjacent first graphics, between adjacent second graphics, and between adjacent third graphics, and the first interconnection structure and the second interconnection structure are both located in the dielectric layer.

11. A graphic array structure, characterized in that: include: A plurality of graphic unit structures as claimed in any one of claims 1 to 4 and 8 to 10, wherein the plurality of graphic unit structures are arranged in an array.

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