Semiconductor test structure and method of manufacturing, testing and semiconductor device

Abstract

This application provides a semiconductor test structure, its manufacturing method, a testing method, and a semiconductor device. The semiconductor test structure includes: at least one structure under test formed on a first substrate, the structure under test including a first transistor and a second transistor connected in series; a first test section electrically connected to the source of the first transistor; a second test section electrically connected to the drain of the second transistor; and a third test section and a fourth test section electrically connected to the gates of the first transistor and the second transistor, respectively.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to semiconductor test structures, their manufacturing methods, testing methods, and semiconductor devices. Background Technology

[0002] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in Dynamic Random Access Memory (DRAM) to control the capacitance in each memory cell, and transistor arrays consisting of multiple transistors can be used in semiconductor memory devices. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor test structure and its manufacturing method, test method, and semiconductor device to solve at least one technical problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a semiconductor test structure, the semiconductor test structure comprising:

[0006] At least one structure under test is formed on a first substrate, the structure under test comprising a first transistor and a second transistor connected in series;

[0007] A first test section electrically connected to the source of the first transistor;

[0008] A second test section electrically connected to the drain of the second transistor;

[0009] A third test section and a fourth test section are respectively electrically connected to the gates of the first transistor and the second transistor.

[0010] In some embodiments, the first substrate is an unthinned substrate.

[0011] In some embodiments, the first substrate includes a device region and a dicing region located around the device region; wherein the structure under test is formed within the dicing region.

[0012] In some embodiments, the first transistor has a first channel, the extension direction of the first channel being perpendicular to the first substrate;

[0013] The second transistor has a second channel that extends perpendicularly to the first substrate.

[0014] In some embodiments, the source of the first transistor is provided at the end of the first channel away from the first substrate;

[0015] The drain of the second transistor is provided at the end of the second channel away from the first substrate.

[0016] In some embodiments, a doped region is formed in the first substrate; the portion of the doped region connected to the first channel constitutes the drain of the first transistor; and the portion of the doped region connected to the second channel constitutes the source of the second transistor.

[0017] In some embodiments, the first channel, the doped region, and the second channel form a U-shaped structure.

[0018] In some embodiments, the gate of the first transistor is provided on at least one sidewall of the first channel;

[0019] The gate of the second transistor is provided on at least one sidewall of the second channel.

[0020] Secondly, embodiments of this application provide a method for manufacturing a semiconductor test structure, the method comprising:

[0021] A first substrate is provided, on which at least one structure under test is formed, the structure under test including a first transistor and a second transistor connected in series;

[0022] A first test section is formed that is electrically connected to the source of the first transistor;

[0023] A second test section is formed that is electrically connected to the drain of the second transistor;

[0024] A third test section and a fourth test section are respectively formed to be electrically connected to the gates of the first transistor and the second transistor.

[0025] In some embodiments, providing the first substrate includes:

[0026] Provide a first substrate;

[0027] The first substrate is doped to form a doped region;

[0028] At least one structure to be tested is formed on the first substrate.

[0029] In some embodiments, the first substrate is an unthinned substrate.

[0030] In some embodiments, the first substrate includes a device region and a dicing region located around the device region; forming at least one structure to be tested on the first substrate includes:

[0031] At least one structure to be tested is formed within the diced area of ​​the first substrate.

[0032] In some embodiments, the first transistor has a first channel, the extension direction of the first channel being perpendicular to the first substrate;

[0033] The second transistor has a second channel, the extension direction of which is perpendicular to the first substrate;

[0034] The portion of the doped region connected to the first channel of the first transistor constitutes the drain of the first transistor; the portion of the doped region connected to the second channel of the second transistor constitutes the source of the second transistor.

[0035] Thirdly, embodiments of this application provide a testing method for testing the semiconductor test structure described in the above technical solutions; the testing method includes:

[0036] For each structure under test: electrical signals are applied to the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor through the first test section, the second test section, the third test section, and the fourth test section, respectively;

[0037] If the first and second transistors connected in series are turned on, it is determined that the structure under test has no defects.

[0038] If the first and second transistors connected in series are not conducting, then the structure under test is determined to have a defect.

[0039] Fourthly, embodiments of this application provide a semiconductor device, the semiconductor device comprising:

[0040] First substrate;

[0041] A device region is located on the first substrate and a dicing region is located around the device region, wherein a semiconductor test structure is formed in the dicing region; wherein the semiconductor test structure includes at least one structure under test, and the structure under test includes a first transistor and a second transistor connected in series;

[0042] A first test section electrically connected to the source of the first transistor;

[0043] A first test section electrically connected to the drain of the first transistor;

[0044] A third test section and a fourth test section are respectively electrically connected to the gates of the first transistor and the second transistor.

[0045] This application provides a semiconductor test structure, its manufacturing method, a testing method, and a semiconductor device. The semiconductor test structure includes: at least one structure under test (DUT) formed on a first substrate, each DUT including a first transistor and a second transistor connected in series; a first test section electrically connected to the source of the first transistor; a second test section electrically connected to the drain of the second transistor; and a third test section and a fourth test section electrically connected to the gates of the first transistor and the second transistor, respectively. The semiconductor test structure provided in this application includes at least one DUT formed on a first substrate, each DUT including a first transistor and a second transistor connected in series. Thus, electrical tests can be performed on the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor using the first, second, third, and fourth test sections respectively. Electrical monitoring of the front-side process of the first substrate can be achieved by performing electrical tests on the first and second transistors connected in series. Attached Figure Description

[0046] Figure 1 A schematic flowchart illustrating the manufacturing method of the semiconductor test structure provided in this application embodiment;

[0047] Figures 2A to 2K This is a schematic diagram illustrating the process of manufacturing a semiconductor test structure provided in an embodiment of this application;

[0048] Figure 3 This is a three-dimensional schematic diagram of the structure under test in the semiconductor test structure provided in the embodiments of this application;

[0049] Figure 4A This is a top view of the solder pad formation provided in an embodiment of this application;

[0050] Figure 4B A cross-sectional view of an optional structure of the first pad provided in an embodiment of this application;

[0051] The figure includes: 201, first substrate; 201a, front side of the first substrate; 201b, back side of the first substrate; 202, active region; 202a, doped active region; 203, first trench; 204, first isolation layer; 204a, doped first isolation layer; 205, doped region; 206, second trench; 207, gate oxide layer; 208a, first gate; 208b, second gate; 209, second isolation layer; 210, third trench. ; 211, Third isolation layer; 212a, First channel; 212b, Second channel; 213a, First source; 213b, Second source; 214a, First drain; 214b, Second drain; 215, First test section; 216, Second test section; 217, Third test section; 218, Fourth test section; 219, First solder pad; 220, Second solder pad; 221, Third solder pad; 222, Fourth solder pad; 223, Conductive via. Detailed Implementation

[0052] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0053] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0054] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0059] Mainstream memory transistor arrays include planar transistor arrays and buried channel array transistors (BCATs). However, regardless of whether it's a planar transistor array or a buried channel transistor array, the source and drain are located on opposite sides of the gate, parallel to the substrate. In this structure, the source and drain occupy different locations, resulting in a relatively large area for both planar and buried channel transistor arrays.

[0060] To further reduce the size of the transistor array, the transistor array of the memory can include a Vertical Gate Transistor (VGT). In this structure, each transistor in the transistor array has a channel, wherein the channels of the transistor array are distributed along a first direction and a second direction, and the extension direction of the channels is perpendicular to the plane formed by the first and second directions. At least one side of each channel of the transistor array can form a gate oxide layer and a gate, and the two ends of the extension direction of each channel of the transistor array have a source and a drain, respectively. The substrate needs to be thinned on the back side to expose each channel of the transistor array, and the exposed channels are doped to form the drain of each transistor, which is subsequently used to connect to the bit line (BL).

[0061] Here, the vertical gate transistor array allows the source and drain to be formed at opposite ends of the channel, avoiding the problem of a large transistor array area caused by forming them on both sides of the gate. This provides a smaller transistor array structure and improves the device's storage density. However, through further research and analysis of the above-mentioned vertical gate transistor array, the inventors discovered that the front-side process of the substrate (e.g., the transistor formation process) is a critical process step in manufacturing the vertical gate transistor array. If the device structure is found to be damaged after the bit lines are led out, or even if the transistors fail to conduct, it is impossible to determine whether the defect lies in the front-side process of the substrate (e.g., the transistor formation process) or in the bit line leading-out process.

[0062] In view of this, embodiments of this application provide a semiconductor test structure and its manufacturing method, test method, and semiconductor device.

[0063] refer to Figure 1 , Figure 1This is a schematic flowchart illustrating a method for manufacturing a semiconductor test structure provided in an embodiment of this application. Figure 1 As shown in the figure, this application provides a method for manufacturing a semiconductor test structure, the method comprising:

[0064] Step S101: Provide a first substrate, on which at least one structure to be tested is formed, the structure to be tested including a first transistor and a second transistor connected in series;

[0065] Step S102: Form a first test section that is electrically connected to the source of the first transistor;

[0066] Step S103: Form a second test section that is electrically connected to the drain of the second transistor;

[0067] Step S104: Form a third test section and a fourth test section that are electrically connected to the gates of the first transistor and the second transistor, respectively.

[0068] In this embodiment, the first substrate may be a single-crystal silicon material used for fabricating semiconductor devices. The first substrate has two opposing surfaces, one of which is the front surface of the first substrate, and the other surface is the back surface of the first substrate. Typically, the front surface of the first substrate can be used to form a transistor pillar, the transistor pillar extending perpendicular to the first substrate. The transistor pillar has two ends along the extending direction, namely a first end and a second end. After doping the first end of the transistor pillar, a source electrode can be formed. After thinning the back surface of the first substrate, the second end of the transistor pillar is exposed. After doping the second end of the transistor pillar, a drain electrode can be formed, and signals can be led out from the back surface of the first substrate.

[0069] In this embodiment of the application, the first substrate is a substrate that has not undergone thinning treatment.

[0070] Here, the semiconductor test structure manufacturing method provided in this application embodiment can perform electrical tests on the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor by forming a first test section, a second test section, a third test section, and a fourth test section, respectively. Without the need to perform back-side thinning of the first substrate to extract electrical signals, the electrical monitoring of the front-side process of the first substrate can be realized.

[0071] Next reference Figures 2A to 2K The manufacturing process of the semiconductor test structure provided in the embodiments of this application will be further described in detail.

[0072] It should be noted that the thickness direction of the first substrate is defined as the Z-direction. Intersecting X and Y directions are defined on the top or bottom surface of the first substrate perpendicular to the Z-direction. Based on the X and Y directions, the top or bottom surface of the first substrate perpendicular to the Z-direction can be determined. For example, the X and Y directions may have a certain angle. Alternatively, the X and Y directions may be perpendicular to each other. Thus, the X, Y, and Z directions are all mutually perpendicular. Here, the X-direction is the row direction, and the Y-direction is the column direction.

[0073] In some embodiments, providing the first substrate includes:

[0074] Provide a first substrate;

[0075] The first substrate is doped to form a doped region;

[0076] At least one structure to be tested is formed on the first substrate.

[0077] In some embodiments, the first substrate includes a device region and a dicing region located around the device region; forming at least one structure to be tested on the first substrate includes:

[0078] At least one structure under test is formed within the dicing region of the first substrate. In this embodiment, the structure under test may be located within the dicing region of the first substrate. Here, the structure within the dicing region may be the same as or different from the structure within the device region.

[0079] refer to Figure 2A and Figure 2B , Figure 2A and Figure 2B These are partial top views and partial cross-sectional views, respectively, of the process of forming the active region and the first groove provided in the embodiments of this application. Figure 2A and Figure 2B As shown, the first substrate 201 has two opposing surfaces, including a front surface 201a and a back surface 201b. Along the thickness direction of the substrate (i.e., the Z direction), the front surface of the first substrate 201 is etched to form a plurality of active regions 202 parallel to the Y direction, and a first groove 203 located between adjacent active regions 202. The first groove exposes the Y-direction-parallel sidewalls of the active regions, which are subsequently used to form the first channel of the first transistor and the second channel of the second transistor in the structure under test.

[0080] In this embodiment, a dry etching process, such as plasma etching or reactive ion etching, can be used to etch the first substrate. It is worth noting that in this embodiment, the etching of the first substrate is a partial etching along its thickness direction; that is, the etching process does not etch through the first substrate.

[0081] In this embodiment, by etching the entire surface of the first substrate to simultaneously form the active region and a first groove with substantially the same depth, the manufacturing process can be simplified and efficiency improved. In actual processes, due to process errors, the depth of the etched first grooves may be the same or meet the error range requirements.

[0082] refer to Figure 2C and Figure 2D , Figure 2C and 2D These are partial top views and partial cross-sectional views, respectively, of the process for forming the first isolation layer provided in the embodiments of this application. Figure 2C and 2D As shown, insulating material is deposited in the first groove to form a first isolation layer 204 located between adjacent active regions. The first isolation layer covers the sidewall of each active region parallel to the Y direction.

[0083] In the embodiments of this application, the deposition process may include, but is not limited to, the following: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0084] In this embodiment, the insulating material forming the first isolation layer may include, but is not limited to, silicon nitride, silicon oxynitride, or silicon dioxide. In a specific example, silicon dioxide may be deposited first in the first groove, followed by silicon nitride, to form the first isolation layer located between adjacent active regions.

[0085] It should be noted that during the actual deposition of insulating material, the insulating material will cover the top surface of the active region. Typically, after deposition, in some embodiments, a chemical mechanical polishing (CMP) process can be used to grind away excess insulating material to expose the top surface of the active region.

[0086] refer to Figure 2E , Figure 2E This is a partial cross-sectional view of the process for forming the doped region provided in an embodiment of this application. Figure 2EAs shown, the first substrate 201 is doped to form a doped region 205. At this time, the back side 201b of the first substrate does not expose the doped region 205. During the doping process of the first substrate, a portion of the active region is also doped simultaneously.

[0087] Here, the process of forming the doped region in the first substrate can be compatible with the process itself. For example, in the embodiments of this application, an N-type doped epitaxial substrate (N-type EPI wafer) can be used directly, which is equivalent to forming the doped region in the first substrate.

[0088] Here, the process of forming the doped region within the first substrate can also employ a multi-step ion implantation process. Particles to be doped are introduced into the first substrate via an ion beam. Through a series of physicochemical interactions, the doped particles gradually lose energy and remain within the substrate, forming the doped region. At this stage, the back side of the first substrate is not exposed to the doped region. By adjusting the ion implantation parameters, such as the ion implantation dose and energy, the depth and concentration distribution of the doped region within the first substrate can be controlled, ensuring that the back side of the first substrate is not exposed to the doped region and that some active regions are simultaneously doped during the doping process of the first substrate.

[0089] In this embodiment, ion implantation is used to dope the first substrate to form a doped region. There are no special restrictions on the direction of ion beam implantation. For example, the ion beam can be implanted from the front side of the first substrate, or it can be implanted from the back side of the first substrate. It should be noted that those skilled in the art can consider the influence of the thickness of the first substrate and the direction of ion implantation on the process difficulty to determine the direction of ion implantation when forming a doped region in the first substrate.

[0090] In the above process steps, after forming an active region on the front side of the first substrate, the back side of the first substrate can be doped to form a doped region. Alternatively, the back side of the first substrate can be doped to form a doped region before forming the active region on the front side. In this embodiment, there are no special restrictions on the process order of forming the active region and forming the doped region.

[0091] In one specific embodiment, the doped region can be an N-type doped region.

[0092] refer to Figure 2F , Figure 2F This is a partial cross-sectional view of the process for doping the active region provided in an embodiment of this application. Figure 2F As shown, ion implantation can be used to simultaneously dope the active region 202 and the first isolation layer 204 to form a doped active region 202a and a doped first isolation layer 204a, respectively. Figure 2F(As shown in the dashed box). The upper surface of the doped active region 202a is flush with the upper surface of the doped first isolation layer 204a. The upper surface of the doped active region 202a is lower than the upper surface of the active region 202, meaning that only a portion of the active region is doped, and the side of the active region furthest from the substrate remains undoped. The doped active region exhibits good conductivity, and the doped first isolation layer exhibits good insulation properties. Using ion implantation to simultaneously dope both the active region and the first isolation layer simplifies process control.

[0093] Alternatively, by adjusting the ion implantation process parameters, the ion implantation process can be used to dope only the active region. The particles to be doped are incident on the active region using an ion beam. Through a series of physicochemical interactions, the doped particles gradually lose energy and remain within the region, forming a doped active region. In this process, the doped active regions are in contact with each other.

[0094] In one specific embodiment, the doped active region can be a P-type doped active region.

[0095] Still referencing Figure 2F As shown in the dashed circle, along the thickness direction of the first substrate (i.e., the Z direction), the active region comprises three parts: an undoped active region, a doped active region, and a doped region. In one specific embodiment, along the direction pointing towards the first substrate, the active region sequentially includes an undoped active region, a P-type doped active region, and an N-type doped region.

[0096] refer to Figure 2G , Figure 2G This is a partial top view of the process of forming the second groove provided in an embodiment of this application. Figure 2G As shown, the front side of the first substrate is etched along its thickness direction (i.e., the Z direction) to form multiple second grooves 206 parallel to the X direction. The second grooves 206 expose the sidewalls of the active regions 202 parallel to the X direction. The second grooves divide each of the multiple active regions parallel to the Y direction into several parts, and the sidewalls of the active regions parallel to the X direction are the sidewalls for the subsequent formation of the gate.

[0097] refer to Figure 2H , Figure 2H A partial top view of the process for forming the first gate and the second gate, provided for embodiments of this application. (See attached image.) Figure 2H As shown, an insulating material is deposited in the second groove to form a gate oxide layer 207 that covers the sidewalls of the active region 202 parallel to the X direction. A conductive material is deposited in the second groove to form a gate that covers the sidewalls of the gate oxide layer 207. An insulating material is further deposited in the second groove to form a second isolation layer 209.

[0098] Here, the gate includes a first gate 208a and a second gate 208b. As described above, the second groove divides each of the plurality of active regions parallel to the Y direction into several parts, and the second groove exposes the sidewalls of the active regions parallel to the X direction. For example, the two sidewalls of the active region exposed by one second groove parallel to the X direction can both be used to form the first gate, and the two sidewalls of the active region exposed by another second groove parallel to the X direction can both be used to form the second gate. Alternatively, the two sidewalls of the active region exposed by the same second groove parallel to the X direction can be used to form the first gate and the second gate, respectively.

[0099] In this embodiment, both the first gate 208a and the second gate 208b are conductive materials, which may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other conductive materials. In a preferred embodiment, the conductive material is tungsten. Here, the gates of the same row of channels are connected to form a word line parallel to the X direction. The word line is used to provide a word line voltage and to control the transistor to turn on or off.

[0100] In this embodiment, the gate oxide layer 207 is an insulating material, such as silicon dioxide. Here, the gate oxide layer is located between the channel and the first gate, or between the channel and the second gate, for electrical isolation to prevent direct contact between the first gate or the second gate and the channel, thus avoiding charge leakage.

[0101] In this embodiment of the application, the insulating material forming the second isolation layer 209 may include, but is not limited to, silicon nitride, silicon oxynitride, or silicon dioxide.

[0102] In this embodiment, a gate oxide layer, a first gate, a second gate, and a second isolation layer can be sequentially formed in the second groove using CVD, PVD, or ALD processes.

[0103] refer to Figure 2I , Figure 2I This is a partial top view of the process of forming the third groove provided in an embodiment of this application. Figure 2I As shown, the front side of the first substrate is etched along the thickness direction of the first substrate to form multiple third grooves 210 parallel to the X direction. Among them, the third grooves 210 expose the sidewalls of the active region parallel to the X direction, that is, the third grooves 210 expose the sidewalls of the channel.

[0104] refer to Figure 2J , Figure 2J This is a partial top view of the process for forming the third isolation layer provided in an embodiment of this application. Figure 2JAs shown, insulating material is deposited in the third groove to form a third insulating layer 211. The groove includes a first groove 212a and a second groove 212b. Figure 2J The first channel 212a and the second channel 212b shown in the schematic diagram are rectangular in the top view. Of course, the first channel and the second channel can also be shown in other shapes such as circles or ellipses in the top view. This application does not have any special restrictions on the shape of the first channel and the second channel in the top view.

[0105] Here, the first transistor includes a first channel extending perpendicular to the first substrate, and a gate oxide layer and a first gate are formed on at least one sidewall of the first channel; the second transistor includes a second channel extending perpendicular to the first substrate, and a gate oxide layer and a second gate are formed on at least one sidewall of the second channel.

[0106] In this embodiment, the materials of the first isolation layer 204, the second isolation layer 209, and the third isolation layer 211 can be the same or different.

[0107] Here, multiple first grooves 203 parallel to the Y direction are formed to form multiple active regions parallel to the Y direction on the front side of the substrate. A first isolation layer 204 isolates the multiple active regions parallel to the Y direction from each other. Further, multiple second grooves 206 and third grooves 210 parallel to the X direction are formed to divide each active region parallel to the Y direction into several channels. A second isolation layer 209 and a third isolation layer 211 isolate channels located in the same column from each other. In some embodiments, the first and second channels are arranged in an array along the X and Y directions. Both the first and second channels are used to transfer or stop charge transfer under the action of an applied electric field, causing the first and second transistors to be turned on or off, respectively. The extension directions of the first and second channels are both perpendicular to the surface of the first substrate. Here, the extension directions of the first and second channels are the current directions when the first and second transistors are turned on.

[0108] Still referencing Figure 2J The first isolation layer divides the channel into four columns, and the second and third isolation layers divide the channel into four rows (e.g., Figure 2J (As shown in the dashed box). Here, we'll use the channel in row 2 as the first channel and the channel in row 3 as the second channel as an example. Of course, you can choose any channel in any row as the first channel, or any channel in any row as the second channel. For example, you can choose the channel in row 1 as the first channel and the channel in row 4 as the second channel.

[0109] In the embodiments of this application, the first channel and the second channel may be arranged adjacent to each other or not adjacent to each other.

[0110] Figure 2J The diagram illustrates 16 channels arranged in four rows and four columns, which can be used to form 16 transistors. Here, the gates of the four channels in the same row are interconnected to form the first transistor, and the gates of the four channels in the other row are interconnected to form the second transistor. That is, the first transistor includes four transistors, and the second transistor also includes four transistors. The number of transistors in the semiconductor test structure provided in this application embodiment is not limited to this.

[0111] In this embodiment of the application, the first channel may be a first columnar channel, and the second channel may be a second columnar channel.

[0112] Furthermore, the orthographic projections of the first and second columnar channels onto the substrate can be circular, elliptical, rectangular, rhomboid, or polygonal, etc., and there are no special limitations in this embodiment. In this embodiment, the orthographic projections of the first and second columnar channels onto the substrate can be the same or different. It should be noted that... Figures 2A to 2K The following explanation uses the example where the orthographic projections of the first and second channels onto the substrate are both rectangular.

[0113] refer to Figure 2K , Figure 2K for Figure 2J A partial sectional view of the dashed line JJ. Figure 2K Only the cross-sectional structural diagrams of the channels in the second row (i.e., the first channel 212a) and the channel in the third row (i.e., the second channel 212b) are shown. Figure 2K As shown, ion implantation is performed on the first channel 212a and the second channel 212b respectively. The first source 213a of the first transistor is formed at the end of the first channel 212a away from the substrate, and the second drain 214b of the second transistor is formed at the end of the second channel 212b away from the substrate.

[0114] Here, during ion implantation, the particles to be doped are incident on the end of each channel away from the substrate using an ion beam. Through a series of physicochemical interactions, the doped particles gradually lose energy and remain there, forming the first source of the first transistor at the end of the first channel away from the substrate and the second drain of the second transistor at the end of the second channel away from the substrate.

[0115] In this embodiment, the first channel and the second channel are both trapezoidal in shape in the cross section perpendicular to the substrate (including the YZ plane and the XZ plane). Of course, the first channel and the second channel can also be other shapes in the cross section perpendicular to the substrate, and this embodiment does not have any special limitations on this.

[0116] In this embodiment, the first gate covers one sidewall of the first channel, and the second gate covers one sidewall of the second channel. The gates of channels in the same row are interconnected to form word lines parallel to the X direction. Of course, a gate surrounding the channel can also be formed, i.e., a gate all around transistor can be formed. This embodiment does not have any special limitations on this.

[0117] In the embodiments of this application, the first transistor and the second transistor in the semiconductor test structure may include vertical gate transistors. Specifically, the first transistor and the second transistor may include, but are not limited to, single-gate transistors, dual-gate transistors, triple-gate transistors, and multi-gate transistors.

[0118] In some embodiments, the first transistor has a first channel, the extension direction of the first channel being perpendicular to the first substrate;

[0119] The second transistor has a second channel, the extension direction of which is perpendicular to the first substrate;

[0120] The portion of the doped region connected to the first channel of the first transistor constitutes the drain of the first transistor; the portion of the doped region connected to the second channel of the second transistor constitutes the source of the second transistor.

[0121] As mentioned earlier, the active region is also doped during the substrate doping process. (Refer to...) Figure 2K The portion of the doped region 205 formed in the first substrate 201 that connects to the first channel 212a constitutes the first drain 214a of the first transistor, and the portion of the doped region 205 formed in the first substrate 201 that connects to the second channel 212b constitutes the second source 213b of the second transistor. In other words, the first transistor and the second transistor form a series structure through the doped region 205.

[0122] This application embodiment also provides a semiconductor test structure, which includes at least one structure under test formed on a first substrate. Each structure under test includes a first transistor and a second transistor connected in series. Thus, the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor can be electrically tested by the first test section, the second test section, the third test section, and the fourth test section, respectively. By performing electrical tests on the first transistor and the second transistor connected in series, the electrical monitoring of the front-side process of the first substrate can be realized.

[0123] In the embodiments of this application, the semiconductor test structure includes at least one structure under test (DUT), and each DUT includes a first transistor and a second transistor connected in series. For ease of explanation, the following description uses one DUT as an example, which does not constitute a limitation on the scope of protection of this application.

[0124] refer to Figure 3 , Figure 3 This is a three-dimensional schematic diagram of the structure under test in the semiconductor test structure provided in an embodiment of this application. (See attached diagram.) Figure 3 As shown, the semiconductor test structure includes: a structure under test formed on a first substrate 201, each structure under test including a first transistor and a second transistor connected in series; a first test section 215 electrically connected to the first source 213a of the first transistor; a second test section 216 electrically connected to the second drain 214b of the second transistor; a third test section 217 electrically connected to the first gate 208a of the first transistor; and a fourth test section 218 electrically connected to the second gate 208b of the second transistor.

[0125] In the embodiments of this application, the first substrate is a substrate that has not undergone thinning treatment.

[0126] Here, the semiconductor test structure provided in this application embodiment can perform electrical tests on the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor through the first test section, the second test section, the third test section, and the fourth test section, respectively. Without the need to perform back-side thinning on the first substrate to extract electrical signals, the electrical monitoring of the front-side process of the first substrate can be realized.

[0127] It should be noted that during the formation of the semiconductor test structure, the source, drain, gate, and gate of the first transistor and the second transistor can themselves be used to extract electrical signals. In other words, the source, drain, gate, and gate of the first transistor and the second transistor can themselves function as a test section. Alternatively, different test sections can be set up to extract the electrical signals from the source, drain, gate, and gate of the first transistor and the second transistor respectively.

[0128] In some embodiments, the first substrate includes a device region and a dicing region located around the device region; wherein the structure under test is formed within the dicing region.

[0129] In this embodiment, the structure under test can be located within the dicing region of the first substrate. The semiconductor test structure provided in this embodiment does not impose any special restrictions on the structure of the device region of the first substrate; more specifically, the semiconductor test structure provided in this embodiment does not impose any special restrictions on the structure of the transistors in the device region of the first substrate.

[0130] Still Figure 3 As shown, the first transistor has a first channel 212a, the extension direction of which is perpendicular to the first substrate 201; a first gate 208a of the first transistor is provided on at least one sidewall of the first channel 212a; the second transistor has a second channel 212b, the extension direction of which is perpendicular to the first substrate 201; a second gate 208b of the second transistor is provided on at least one sidewall of the second channel 212b; a first source 213a of the first transistor is provided at one end of the first channel 212a away from the first substrate 201; and a second drain 214b of the second transistor is provided at one end of the second channel 212b away from the first substrate 201.

[0131] Still Figure 3 As shown, a doped region 205 is formed in the first substrate 201; the portion of the doped region 205 connected to the first channel 212a constitutes the first drain 214a of the first transistor; the portion of the doped region 205 connected to the second channel 212b constitutes the second source 213b of the second transistor.

[0132] In some embodiments, reference Figure 3 The first channel 212a, the doped region 205, and the second channel 212b form a U-shaped structure.

[0133] In some embodiments, the semiconductor test structure further includes: a first pad, wherein the first test portion is electrically connected to the source of the first transistor via the first pad; and / or, a second pad, wherein the second test portion is electrically connected to the drain of the second transistor via the second pad; and / or, a third pad, wherein the third test portion is electrically connected to the gate of the first transistor via the third pad; and / or, a fourth pad, wherein the fourth test portion is electrically connected to the gate of the second transistor via the fourth pad.

[0134] refer to Figure 4A , Figure 4A This is a top view of the bonding pad formation provided in an embodiment of this application. Each structure under test includes five transistors in the same row as first transistors and five transistors in another row as second transistors. As shown in FIG4, the first bonding pad 219 is electrically connected to the source of the first transistor (i.e., the five transistors in the same row), the second bonding pad 220 is electrically connected to the drain of the second transistor (i.e., the five transistors in the same row), the third bonding pad 221 is electrically connected to the gate of the first transistor (i.e., the five transistors in the same row), and the fourth bonding pad 222 is electrically connected to the gate of the second transistor (i.e., the five transistors in the same row).

[0135] refer to Figure 4B , Figure 4BA cross-sectional view of an optional structure of the first solder pad provided in an embodiment of this application. (See attached image.) Figure 4B As shown, the first pad 219 is used to electrically connect the first source 213a of the first transistor to the first test section 215. The first pad 219 and the first source 213a are connected through a conductive via 223. The first pad 219 and the first test section 215 are also connected through a conductive via 223. Figure 4B This diagram only illustrates a cross-sectional view of an optional structure in which the first test section is electrically connected to the first source of the first transistor via a first pad. Of course, other structures can also be used to connect the first test section and the first source of the first transistor, as long as the electrical connection function is achieved. The electrical connections between the second test section via a second pad and the second drain of the second transistor, the third test section via a third pad and the gate of the first transistor, and the fourth test section via a fourth pad and the gate of the second transistor can be referenced. Figure 4B The process will not be elaborated upon here.

[0136] This application embodiment also provides a testing method for testing the semiconductor test structure described in the above technical solution, the testing method comprising:

[0137] For each structure under test: electrical signals are applied to the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor through the first test section, the second test section, the third test section, and the fourth test section, respectively;

[0138] If the first and second transistors connected in series are turned on, it is determined that the structure under test has no defects.

[0139] If the first and second transistors connected in series are not conducting, then the structure under test is determined to have a defect.

[0140] Here, a first transistor and a second transistor are connected in series by forming a doped region in a first substrate (i.e., a substrate that has not undergone thinning treatment). Electrical signals are applied to the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor through a first test section, a second test section, a third test section, and a fourth test section, respectively.

[0141] If the first and second transistors connected in series are turned on, it is determined that the structure under test has no defects. That is, all process steps performed before this point have been executed normally, and subsequent process steps can continue. In other words, by performing electrical tests on the structure under test, if the first and second transistors connected in series are turned on, it can be determined that the front-side process of the first substrate has no defects, that is, the process of forming the first and second transistors has no defects.

[0142] If the first and second transistors connected in series are not conducting, it is determined that the structure under test has a defect. That is, at least one of the process steps executed before this point must be in an abnormal execution state, so subsequent process steps cannot be executed. In other words, by performing electrical tests on the structure under test, if the first and second transistors connected in series are not conducting, it can be determined that there is a defect in the front-side process of the first substrate, that is, there is a defect in the process of forming the first and second transistors.

[0143] Here, the non-conductivity of the first and second transistors connected in series includes three scenarios: First, the process for forming the first transistor has a defect, while the process for forming the second transistor is not defective; second, the process for forming the first transistor is not defective, but the process for forming the second transistor has a defect; third, the process for forming the first transistor has a defect, and the process for forming the second transistor also has a defect. In other words, when the first and second transistors connected in series are not conducting, it can be determined that at least one of the processes for forming the first transistor and the second transistor has a defect.

[0144] In some embodiments, a turn-on voltage is applied to the gates of the first transistor and the second transistor through the third test section and the fourth test section, respectively;

[0145] If the first and second transistors connected in series are turned on, it is determined that the structure under test has no defects.

[0146] If the first and second transistors connected in series are not conducting, then the structure under test is determined to have a defect.

[0147] If the processes for forming the first and second transistors are free of defects, then when conduction voltages are applied to the gates of the first and second transistors via the third and fourth test sections respectively, both the series-connected first and second transistors will conduct. Therefore, by observing the conduction of the series-connected first and second transistors, it can be concluded that the processes for forming the first and second transistors are free of defects.

[0148] Here, if both the processes for forming the first and second transistors are defective, then after applying turn-on voltages to the gates of the first and second transistors through the third and fourth test sections respectively, the series-connected first and second transistors will not conduct. If the process for forming the first transistor is defective, but the process for forming the second transistor is not defective, then after applying turn-on voltages to the gates of the first and second transistors through the third and fourth test sections respectively, the series-connected first and second transistors will not conduct. If the process for forming the first transistor is not defective, but the process for forming the second transistor is defective, then after applying turn-on voltages to the gates of the first and second transistors through the third and fourth test sections respectively, the series-connected first and second transistors will not conduct. In other words, if any one of the processes for forming the first and second transistors is defective, then the series-connected first and second transistors will not conduct. Therefore, by observing the phenomenon that the series-connected first and second transistors are not conducting, it can be concluded that at least one of the processes for forming the first and second transistors is defective.

[0149] In some embodiments, if the first and second transistors connected in series are turned on, it is determined that the structure under test (DUT) has no defects. By performing electrical tests on the DUT disposed in the dicing region of the first substrate, it can be determined that the front-side process of the device region and the dicing region on the first substrate has no defects. Subsequently, the first substrate can be subjected to back-side thinning; more specifically, the device region of the first substrate can be subjected to back-side thinning, and the drains of the transistors in the device region can be electrically led out for connection to bit lines. Subsequently, electrical tests can be performed on the transistors in the device region based on word lines and bit lines. If the transistors in the device region cannot be turned on at this time, it can be determined that there are defects in the back-side thinning process or the bit line leading-out process.

[0150] The testing method provided in this application provides that by forming a first transistor and a second transistor connected in series on the front side of a first substrate (i.e., a substrate that has not undergone thinning treatment), the electrical signals of the first transistor and the second transistor connected in series can be extracted from the front side of the first substrate. In this way, the electrical properties of the front side process of the first substrate can be monitored without performing back-side thinning treatment on the first substrate to extract the electrical signals.

[0151] The testing methods provided in this application are applicable to various types of semiconductor devices, such as DRAM, NAND flash memory, static random access memory (SRAM), and phase change memory (PCM).

[0152] The test method provided in this application embodiment can be used to electrically monitor the front-side process of forming vertical gate transistors. The test method provided in this application embodiment can be applied to the electrical monitoring of the front-side process of forming single-gate transistors, dual-gate transistors, tri-gate transistors, and even multi-gate transistors.

[0153] Still referencing Figure 4A The testing method provided in this application can select two transistors from a plurality of transistors arranged in an array as the first transistor and the second transistor in the structure under test, respectively. The electrical signals of the source, drain, gate, and gate of the first transistor and the second transistor are respectively brought out through the first, second, third, and fourth bonding pads. Then, the structure under test is electrically tested through the first, second, third, and fourth testing sections, respectively. Alternatively, multiple transistors located in one row can be selected as the first transistor in the structure under test, and multiple transistors located in another row can be selected as the second transistor. The electrical signals of the source, drain, gate, and gate of the first transistor and the second transistor are respectively brought out through the first, second, third, and fourth bonding pads. Then, the structure under test is electrically tested through the first, second, third, and fourth testing sections, respectively. This application does not have a special limitation on the number of first and second transistors used for electrical testing.

[0154] This application embodiment also provides a semiconductor device, the semiconductor device comprising:

[0155] First substrate;

[0156] A device region is located on the first substrate and a dicing region is located around the device region, wherein a semiconductor test structure is formed in the dicing region; wherein the semiconductor test structure includes at least one structure under test, and the structure under test includes a first transistor and a second transistor connected in series;

[0157] A first test section electrically connected to the source of the first transistor;

[0158] A first test section electrically connected to the drain of the first transistor;

[0159] A third test section and a fourth test section are respectively electrically connected to the gates of the first transistor and the second transistor.

[0160] This application provides a semiconductor test structure, its manufacturing method, a testing method, and a semiconductor device. The semiconductor test structure includes: at least one structure under test (DUT) formed on a first substrate, each DUT including a first transistor and a second transistor connected in series; a first test section electrically connected to the source of the first transistor; a second test section electrically connected to the drain of the second transistor; and a third test section and a fourth test section electrically connected to the gates of the first transistor and the second transistor, respectively. The semiconductor test structure provided in this application includes at least one DUT formed on a first substrate, each DUT including a first transistor and a second transistor connected in series. Thus, electrical tests can be performed on the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor using the first, second, third, and fourth test sections respectively. Electrical monitoring of the front-side process of the first substrate can be achieved by performing electrical tests on the first and second transistors connected in series.

[0161] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0162] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A semiconductor testing structure, characterized in that, The semiconductor testing structure includes: At least one structure under test is formed on a first substrate, the structure under test including a first transistor and a second transistor connected in series; the first transistor has a first channel extending perpendicular to the first substrate, the second transistor has a second channel extending perpendicular to the first substrate; the drain of the first transistor and the source of the second transistor are both disposed in the first substrate. A first test section is provided at the end of the first channel away from the first substrate, which is the source of the first transistor and electrically connected to the source of the first transistor. A second test section is provided at one end of the second channel away from the first substrate, which is the drain of the second transistor and electrically connected to the drain of the second transistor. A third test section and a fourth test section are provided, which are electrically connected to the gates of the first transistor and the second transistor respectively, on at least one sidewall of the first channel and at least one sidewall of the second channel.

2. The semiconductor test structure according to claim 1, characterized in that, The first substrate is an unthinned substrate.

3. The semiconductor test structure according to claim 1, characterized in that, The first substrate includes a device region and a dicing region located around the device region; wherein the structure under test is formed within the dicing region.

4. The semiconductor test structure according to claim 1, characterized in that, A doped region is formed in the first substrate; the portion of the doped region connected to the first channel constitutes the drain of the first transistor; the portion of the doped region connected to the second channel constitutes the source of the second transistor.

5. The semiconductor test structure according to claim 4, characterized in that, The first channel, the doped region, and the second channel form a U-shaped structure.

6. A method for manufacturing a semiconductor test structure, characterized in that, The manufacturing method includes: A first substrate is provided, on which at least one structure under test is formed, the structure under test including a first transistor and a second transistor connected in series; the first transistor has a first channel extending perpendicular to the first substrate, the second transistor has a second channel extending perpendicular to the first substrate; the drain of the first transistor and the source of the second transistor are both disposed in the first substrate. The source of the first transistor is formed at the end of the first channel away from the first substrate, and a first test section is formed that is electrically connected to the source of the first transistor. The drain of the second transistor is formed at one end of the second channel away from the first substrate, and a second test section is formed that is electrically connected to the drain of the second transistor. The gate of the first transistor is formed on at least one sidewall of the first channel, and the gate of the second transistor is formed on at least one sidewall of the second channel. A third test section and a fourth test section are formed, which are electrically connected to the gates of the first transistor and the second transistor, respectively.

7. The method for manufacturing a semiconductor test structure according to claim 6, characterized in that, The provision of the first substrate includes: Provide a first substrate; The first substrate is doped to form a doped region; At least one structure to be tested is formed on the first substrate.

8. The method for manufacturing a semiconductor test structure according to claim 6, characterized in that, The first substrate is an unthinned substrate.

9. The method for manufacturing a semiconductor test structure according to claim 7, characterized in that, The first substrate includes a device region and a dicing region located around the device region; forming at least one structure to be tested on the first substrate includes: At least one structure to be tested is formed within the diced area of ​​the first substrate.

10. The method for manufacturing a semiconductor test structure according to claim 7, characterized in that, The portion of the doped region connected to the first channel of the first transistor constitutes the drain of the first transistor; the portion of the doped region connected to the second channel of the second transistor constitutes the source of the second transistor.

11. A testing method, characterized in that, For testing the semiconductor test structure according to any one of claims 1 to 5; the test method includes: For each structure under test: electrical signals are applied to the source of the first transistor, the drain of the second transistor, the gate of the first transistor, and the gate of the second transistor through the first test section, the second test section, the third test section, and the fourth test section, respectively; If the first and second transistors connected in series are turned on, it is determined that the structure under test has no defects. If the first and second transistors connected in series are not conducting, then the structure under test is determined to have a defect.

12. A semiconductor device, characterized in that, The semiconductor device includes: First substrate; A device region is located on the first substrate, and a dicing region is located around the device region. A semiconductor test structure is formed in the dicing region. The semiconductor test structure includes at least one structure under test, which includes a first transistor and a second transistor connected in series. The first transistor has a first channel, the extension direction of which is perpendicular to the first substrate. The second transistor has a second channel, the extension direction of which is perpendicular to the first substrate. The drain of the first transistor and the source of the second transistor are both disposed in the first substrate. A first test section is provided at the end of the first channel away from the first substrate, which is the source of the first transistor and electrically connected to the source of the first transistor. A second test section is provided at one end of the second channel away from the first substrate, which is the drain of the second transistor and electrically connected to the drain of the second transistor. A third test section and a fourth test section are provided, which are electrically connected to the gates of the first transistor and the second transistor respectively, on at least one sidewall of the first channel and at least one sidewall of the second channel.

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