Electrostatic discharge protection structure and forming method thereof

Abstract

An electrostatic discharge protection structure and a method for forming the same, comprising a substrate having a first isolation structure group on the substrate, the first isolation structure group comprising a plurality of first isolation structures; a first well region and a second well region located on the substrate, the first well region and the second well region being connected, the first well region containing first doped ions, the second well region containing second doped ions, the first doped ions and the second doped ions having different conductivity types, a first isolation structure located at the connection between the first well region and the second well region, and located in both the first well region and the second well region; a fin electrical connection region located at the connection between the first well region and the second well region, the first isolation structure located between the fin electrical connection region, the fin electrical connection region containing third doped ions, the third doped ions having the same conductivity type as the second doped ions; and a heavily doped region located at the bottom of the fin electrical connection region, wherein a trigger voltage for triggering an SCR structure is reduced, thereby protecting the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an electrostatic discharge protection structure and a forming method thereof. Background Art

[0002] As multimedia applications play an increasingly important role in our daily lives and the relationship between computers and consumer electronics grows, there will be a continued demand for increased portability and functionality. This demands higher component integration—a trend that results in sensitive and expensive chips that are at increased risk of damage from ESD surges on external interfaces. As products such as mobile phones, digital cameras, MP3 players, and PDAs offer more functionality, their I / O ports also increase, allowing electrostatic discharge (ESD) to enter the system and interfere with or damage the integrated circuit (IC). Furthermore, with the increase in features and multi-functional integration, IC designs are becoming more sensitive to ESD. Designers face the challenge of ensuring that ICs provide the most effective ESD protection possible while minimizing the board space and cost of additional protection components.

[0003] When using traditional semiconductor controlled rectifier (SCR) as ESD protection, the generated V esd Very low, equal to its V hold Therefore, it can be foreseen that the traditional SCR can conduct a large amount of current, allowing the excess charge to be discharged quickly to prevent the protected device from being burned out, so it is very suitable as an ESD protection device.

[0004] However, in high-voltage integrated circuit applications, high current density and severe heating of the device's PN junction make ESD protection for high-voltage integrated circuits extremely difficult. Furthermore, using SCRs as ESD protection devices in high-voltage integrated circuits presents problems such as uneven triggering and low trigger current. In particular, low trigger current can easily cause the SCR device to falsely trigger due to external noise interference, leading to latch-up. This clamps the pad to a low voltage, disrupting normal signal transmission and rendering ESD protection ineffective.

[0005] Therefore, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide an electrostatic discharge protection structure and a forming method thereof, which can effectively improve the performance of the electrostatic discharge protection structure.

[0007] To solve the above problems, the present invention provides an electrostatic discharge protection structure, comprising: a substrate, having a first isolation structure group thereon, the first isolation structure group including several first isolation structures; a first well region and a second well region located on the substrate, the first well region and the second well region being connected, the first well region having a first doped ion, the second well region having a second doped ion, the first doped ion and the second doped ion having different conductivity types, the first isolation structure being located at the connection between the first well region and the second well region, the first isolation structure being located in both the first well region and the second well region; a fin electrical connection region being located at the connection between the first well region and the second well region, the first isolation structure being located between the fin electrical connection region, the fin electrical connection region having a third doped ion, the third doped ion having the same conductivity type as the second doped ion; a heavily doped region being located at the bottom of the fin electrical connection region, the heavily doped region having a fourth doped ion, the fourth doped ion having a different conductivity type from the third doped ion.

[0008] Optionally, the fin electrical connection region includes one or both of a source / drain doped region located on the fin or a gate structure located on the fin.

[0009] Optionally, it further includes: a plurality of second isolation structures located on the substrate, wherein the width of the second isolation structure is greater than the width of the first isolation structure.

[0010] Optionally, the doping depth of the heavily doped region is less than the depth of the first isolation structure.

[0011] Optionally, it further includes: a third isolation structure located on the substrate, the third isolation structure is located between adjacent second isolation structures, and the width of the third isolation structure is smaller than the width of the second isolation structure.

[0012] Optionally, the first doping ions include N-type ions; the first doping ions include phosphorus or arsenic.

[0013] Optionally, the second doping ions include P-type ions; the second doping ions include boron or indium.

[0014] Optionally, the substrate includes a base and a fin located on the base, the fin having the first well region and the second well region, the first isolation structure, the heavily doped region, and the fin electrical connection region located on the fin.

[0015] Optionally, when the fin electrical connection region is a source-drain doped region located on the fin, the fin electrical connection region also includes: a first fin electrical connection region group, located in the first well region, including a first N-type fin electrical connection region and a first P-type fin electrical connection region, the first N-type fin electrical connection region and the first P-type fin electrical connection region are isolated by the second isolation structure, and the third isolation structure located in the first well region is respectively located between the first N-type fin electrical connection region and the first P-type fin electrical connection region.

[0016] Optionally, the fin electrical connection area also includes: a second fin electrical connection area group, located in the second well area, including a second N-type fin electrical connection area and a second P-type fin electrical connection area, the second N-type fin electrical connection area and the second P-type fin electrical connection area are isolated by the second isolation structure, and the third isolation structure located in the second well area is respectively located between the second N-type fin electrical connection areas and the second P-type fin electrical connection areas.

[0017] Optionally, the first fin electrical connection area group is connected to a power supply voltage or a ground voltage.

[0018] Optionally, the second fin electrical connection area group is connected to a ground voltage or a power supply voltage.

[0019] Correspondingly, the present invention also provides a method for forming the above-mentioned electrostatic discharge protection structure, including: providing a substrate, forming a first isolation structure group on the substrate, the first isolation structure group including several first isolation structures; forming a first well region and a second well region on the substrate, the first well region and the second well region being connected, the first well region having a first doped ion, the second well region having a second doped ion, the first doped ion and the second doped ion having a different conductivity type, the first isolation structure being located at the connection between the first well region and the second well region, the first isolation structure being located in the first well region and the second well region at the same time; forming a fin electrical connection region at the connection between the first well region and the second well region, the fin electrical connection region having the first isolation structure, the fin electrical connection region having a third doped ion, the third doped ion having the same conductivity type as the second doped ion; forming a heavily doped region at the bottom of the fin electrical connection region, the heavily doped region having a fourth doped ion, the fourth doped ion having a different conductivity type from the third doped ion.

[0020] Optionally, the method further includes: forming a plurality of second isolation structures on the substrate, wherein the width of the second isolation structure is greater than the width of the first isolation structure.

[0021] Optionally, the doping depth of the heavily doped region is less than the depth of the first isolation structure.

[0022] Optionally, the method further includes: forming the third isolation structure on the substrate, wherein the third isolation structure is located between adjacent second isolation structures, and the width of the third isolation structure is smaller than the width of the second isolation structure.

[0023] Optionally, the first doping ions include N-type ions; the first doping ions include phosphorus or arsenic.

[0024] Optionally, the second doping ions include P-type ions; the second doping ions include boron or indium.

[0025] Optionally, the substrate includes a base and a fin formed on the base, and the first well region, the second well region, the first isolation structure group, the heavily doped region and the fin electrical connection region located on the fin are formed in the fin.

[0026] Optionally, the fin electrical connection region includes one or both of a source / drain doped region located on the fin or a gate structure located on the fin.

[0027] Optionally, when the fin electrical connection region is a source-drain doped region located on the fin, the fin electrical connection region also includes: forming a first fin electrical connection region group in the first well region, the first fin electrical connection region group including a first N-type fin electrical connection region and a first P-type fin electrical connection region, the first N-type fin electrical connection region and the first P-type fin electrical connection region are isolated by the second isolation structure, and the third isolation structure of the first well region is respectively formed between the first N-type fin electrical connection region and the first P-type fin electrical connection region.

[0028] Optionally, the fin electrical connection area also includes: forming a second fin electrical connection area group in the second well area, the second fin electrical connection area group includes a second N-type fin electrical connection area and a second P-type fin electrical connection area, the second N-type fin electrical connection area and the second P-type fin electrical connection area are isolated by the second isolation structure, and the third isolation structure formed in the second well area is respectively formed between the second N-type fin electrical connection areas and the second P-type fin electrical connection areas.

[0029] Optionally, the first fin electrical connection area group is connected to a power supply voltage or a ground voltage.

[0030] Optionally, the second fin electrical connection area group is connected to a ground voltage or a power supply voltage.

[0031] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0032] In the structure of the technical solution of the present invention, the first well region has a first doped ion, the second well region has a second doped ion, and the first doped ion and the second doped ion have different conductivity types; there is a first isolation structure group at the connection between the first well region and the second well region, and the first isolation structure group is located in the first well region and the second well region at the same time; the fin electrical connection region is located at the connection between the first well region and the second well region, the first isolation structure is located between the fin electrical connection region, the fin electrical connection region has a third doped ion, and the third doped ion and the second doped ion have the same conductivity type; the heavily doped region is located in the fin electrical connection region, the heavily doped region has a fourth doped ion, and the fourth doped ion and the third doped ion have different conductivity types. Since the heavily doped region isolates the fin electrical connection region from the second well region, the heavily doped region is isolated from the first well region by the first isolation structure. A capacitor can be formed between the heavily doped region and the fin electrical connection region through the first isolation structure. Subsequently, different potentials are coupled out from the VDD end. When the ESD event occurs, the VDD potential gradually increases. At this time, the capacitance between the fin electrical connection region and VDD is small, while the capacitance between the heavily doped region and VDD is large, so that the capacitance at the fin electrical connection region can be increased faster. At this time, the PN diode is turned on, and after being turned on, a PNP transistor is formed with the second well region, causing the transistor to be turned on. At this time, the trigger voltage of the SCR structure is reduced. Since the trigger voltage is reduced, the circuit is protected.

[0033] In the formation method of the technical solution of the present invention, a first well region and a second well region are formed, the first well region and the second well region are connected, the first well region has a first doped ion, the second well region has a second doped ion, and the first doped ion and the second doped ion have different conductivity types; a first isolation structure is formed in the first well region and the second well region at the same time; a fin electrical connection region is formed at the connection between the first well region and the second well region, a first isolation structure is formed between the fin electrical connection regions, the fin electrical connection region has a third doped ion, and the third doped ion has the same conductivity type as the second doped ion; a heavily doped region is formed in the fin electrical connection region, the heavily doped region has a fourth doped ion, and the fourth doped ion has a different conductivity type from the third doped ion. Since the heavily doped region isolates the fin electrical connection region from the second well region, the heavily doped region is isolated from the first well region through the first isolation structure. A capacitor can be formed between the heavily doped region and the fin electrical connection region through the first isolation structure. Subsequently, different potentials are coupled out from the VDD end. When the ESD event occurs, the VDD potential gradually increases. At this time, the capacitance between the fin electrical connection region and VDD is small, while the capacitance between the heavily doped region and VDD is large, so that the capacitance at the fin electrical connection region can be increased faster. At this time, the PN diode is turned on, and after being turned on, a PNP transistor is formed with the second well region, causing the transistor to be turned on. At this time, the trigger voltage of the SCR structure is reduced. Since the trigger voltage is reduced, the circuit is protected.

[0034] In addition, a plurality of second isolation structures are formed within the first well region and the second well region, with the first isolation structure group located between adjacent second isolation structures, and the width of the second isolation structure being greater than the width of the first isolation structure in the first isolation structure group. Since the first isolation structure and the second isolation structure have different widths, during the formation of the electrostatic discharge protection structure, under the premise that the injection conditions used are fixed, the capacitance can be adjusted by adjusting the width of the isolation structure (the first isolation structure or the second isolation structure), thereby adjusting the trigger voltage for triggering the SCR structure, making the process more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural diagram of an electrostatic discharge protection structure;

[0036] Figure 2 It is a structural diagram of another electrostatic discharge protection structure;

[0037] Figures 3 to 8 It is a structural schematic diagram of the formation process of an electrostatic discharge protection structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Currently, the performance of the electrostatic discharge protection structure formed by the existing technology needs to be improved. The following will be described in detail with reference to the accompanying drawings.

[0039] Please refer to Figure 1 , a substrate 100, a fin 101 located in the substrate 100, a first well region 102 located in the fin 101, a second well region 103 located in the fin 101, the first well region 102 is connected to the second well region 103, an isolation structure 104 is located in the fin 101, a first fin electrical connection area group 105 is located in the first well region 102, including a plurality of first N-type fin electrical connection areas 106 and a plurality of first P-type fin electrical connection areas 107, connected to the power supply voltage VDD, a second fin electrical connection area group 108 is located in the second well region 103, including a plurality of second N-type fin electrical connection areas 109 and a plurality of second P-type fin electrical connection areas 110, connected to the ground voltage connection VSS, and the first fin electrical connection area group 105 and the second fin electrical connection area group 108 are separated by an isolation structure 104.

[0040] In the above embodiment, the trigger voltage for triggering the SCR structure is determined by the well breakdown voltage at the connection between the first well region and the second well region. This trigger voltage is too high to protect the working circuit.

[0041] Please refer to Figure 2 , another structure, relative to Figure 1 The structure has an additional first isolation structure group, which is located at the connection between the first well region 102 and the second well region 103. The first isolation structure group includes multiple first isolation structures 111 and a fin electrical connection region 112 located between adjacent first isolation structures 111 and isolated by the first isolation structures 111. The fin electrical connection region 112 is doped with N-type ions or P-type ions.

[0042] In the above embodiment, the trigger voltage of the SCR structure is determined by the junction breakdown voltage between the fin electrical connection region and the well region rather than by the Figure 1 The larger well breakdown determines the

[0043] But with the reduction of Vop in advanced technologies, the trigger voltage needs to be lower, which requires other improved SCR structures.

[0044] On this basis, the present invention provides an electrostatic discharge protection structure and a method for forming the same, wherein a heavily doped region is formed at the bottom of the fin electrical connection region, wherein the heavily doped region contains a fourth dopant ion, and the fourth dopant ion has a different conductivity type from the third dopant ion. Since the heavily doped region isolates the fin electrical connection region from the second well region, the heavily doped region is isolated from the first well region by the first isolation structure in the first isolation structure group. A capacitor can be formed between the heavily doped region and the fin electrical connection region through the first isolation structure. Subsequently, different potentials are coupled out from the VDD end. When an ESD event occurs, the VDD potential gradually increases. At this time, the capacitance between the fin electrical connection region and VDD is small, while the capacitance between the heavily doped region and VDD is large, so that the capacitance at the fin electrical connection region can increase faster. At this time, the PN diode is turned on, and after turning on, it forms a PNP transistor with the second well region, causing the transistor to turn on and triggering the SCR structure. In this case, the trigger voltage is reduced, thereby playing a protective role in the circuit.

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0046] Figures 3 to 8 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0047] Please refer to Figure 3 , providing a substrate 200, wherein the substrate includes a first region I and a second region II arranged along a first direction X, wherein the first region I is adjacent to the second region II.

[0048] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the material of the substrate may also be single crystal germanium, silicon germanium, silicon carbide, or silicon on insulator (SOI), germanium on insulator (GOI); or the substrate may also be other materials, such as III-V compounds such as gallium arsenide.

[0049] In this embodiment, the substrate includes: a base 201 and a fin 202 located on the base 201 ; in other embodiments, the substrate may further include: a base.

[0050] In this embodiment, the method for forming the fin 202 includes: providing an initial substrate (not shown); forming a third patterned layer (not shown) on the initial substrate, wherein the third patterned layer exposes a portion of the top surface of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a base 201 and the fin 202 located on the base 201.

[0051] In other embodiments, an initial substrate is provided; a third patterned layer is formed on the initial substrate, wherein the third patterned layer exposes a portion of the top surface of the initial substrate; and the initial substrate is etched using the third patterned layer as a mask to form a base.

[0052] Please refer to Figure 4 After forming the fin 202 , a first isolation structure group is formed in the substrate 201 , where the first isolation structure group includes a plurality of first isolation structures 203 .

[0053] In this embodiment, the material of the first isolation structure 203 is silicon oxide; in other embodiments, the material of the isolation structure may also be silicon oxynitride.

[0054] In this embodiment, the first isolation structure 203 is formed at the connection between the first region I and the second region II.

[0055] In this embodiment, the method for forming the first isolation structure includes: etching a portion of the fin to form an isolation opening in the fin; and forming the first isolation structure in the isolation opening.

[0056] In this embodiment, the first isolation structure group includes three first isolation structures 203 .

[0057] Please continue to refer to Figure 4 , forming a plurality of second isolation structures 204 on the substrate.

[0058] In this embodiment, the width of the second isolation structure 204 is greater than the width of the first isolation structure 203. The reason for this setting is that a wider dielectric isolation layer introduces smaller capacitance, so that the fin electrical connection area couples voltage faster than the heavily doped area.

[0059] In this embodiment, the second isolation structure 204 is located in the first region I and the second region II, respectively, but not at the connection between the first region I and the second region II.

[0060] In this embodiment, at the connection between the first region I and the second region II, the first isolation structure group is located between adjacent second isolation structures 204 .

[0061] Please continue to refer to Figure 4 , the third isolation structure 205 is formed on the substrate, and the third isolation structure 205 is located between adjacent second isolation structures 204.

[0062] In this embodiment, a plurality of the third isolation structures 205 are provided between adjacent second isolation structures 204 .

[0063] In other embodiments, there may be only a single third isolation structure 205 between adjacent second isolation structures 204 .

[0064] In this embodiment, the width of the third isolation structure 205 is smaller than the width of the second isolation structure 204 .

[0065] In this embodiment, the width of the third isolation structure 205 is the same as the width of the first isolation structure 203 .

[0066] In other embodiments, the width of the third isolation structure 205 may be different from the width of the first isolation structure 203 .

[0067] In this embodiment, the third isolation structures 205 are respectively located between adjacent second isolation structures 204 on the first region I and between adjacent second isolation structures 204 on the second region II.

[0068] In this embodiment, the first isolation structure 203, the second isolation structure 204, and the third isolation structure 205 are formed in the same etching process. In other embodiments, the first isolation structure 203, the second isolation structure 204, and the third isolation structure 205 are formed in different etching processes.

[0069] In this embodiment, the process for forming the first isolation structure 203, the second isolation structure 204 and the third isolation structure 205 is a dry etching process; in other embodiments, the process for forming the first isolation structure 203, the second isolation structure 204 and the third isolation structure 205 is a dry etching process, a wet etching process or a mixture of a wet etching process and a dry etching process.

[0070] Please refer to Figure 5 After forming the first isolation structure 203, a first well region 206 is formed in the first region I, and the first well region 206 has first doping ions.

[0071] In this embodiment, the method for forming the first well region 206 includes: forming a first patterned layer (not shown) on the substrate, wherein the first patterned layer exposes the top surface of the first region I; using the first patterned layer as a mask, performing a first dopant ion implantation process on the first region I to form the first well region in the first region I.

[0072] The first doping ion includes an N-type ion; the first doping ion includes phosphorus or arsenic. In this embodiment, the first doping ion is phosphorus.

[0073] In this embodiment, after the first well region 206 is formed, the first patterned layer is removed.

[0074] Please refer to Figure 6 A second well region 207 is formed in the second region II. The second well region 207 has second doping ions. The electrical type of the second doping ions is different from that of the first doping ions.

[0075] In this embodiment, the method for forming the second well region 207 includes: forming a second patterned layer (not shown) on the substrate, the second patterned layer exposing the top surface of the second region II; using the second patterned layer as a mask, performing a second dopant ion implantation process on the second region II to form the second well region 207 in the second region II.

[0076] In this embodiment, after the second well region 207 is formed, the second patterned layer is removed.

[0077] The second doping ion includes a P-type ion; the second doping ion includes boron or indium. In this embodiment, the second doping ion is boron.

[0078] In other embodiments, the second well region may be formed first, and then the first well region may be formed.

[0079] In this embodiment, the first isolation structure group is located at the connection between the first well region 206 and the second well region 207 , and the first isolation structure 203 is located in both the first well region 206 and the second well region 207 .

[0080] Please refer to Figure 7 A fin electrical connection region 208 is formed at the connection between the first well region 206 and the second well region 207, and the first isolation structure 203 is provided between the fin electrical connection region 208. The fin electrical connection region 208 contains third doping ions, and the third doping ions have the same conductivity type as the second doping ions.

[0081] In this embodiment, the third doping ion includes a P-type ion; the third doping ion includes boron or indium. In this embodiment, the third doping ion is boron. In this embodiment, the concentration of the third doping ion is greater than the concentration of the second doping ion.

[0082] In this embodiment, the fin electrical connection region is a source-drain doped region located on the fin 202 ; in other embodiments, the fin electrical connection region may also be a gate structure located on the fin.

[0083] In this embodiment, the method for forming the fin electrical connection area 208 includes: forming a patterned layer on the substrate 200, etching the fin 201 using the patterned layer as a mask, forming the heavily doped opening (not marked) in the fin 201, and forming the fin electrical connection area 208 in the heavily doped opening.

[0084] In this embodiment, the method for forming the fin electrical connection region 208 includes: forming a heavily doped epitaxial layer (not shown) in the heavily doped opening (not shown) using an epitaxial growth process; in-situ doping the heavily doped epitaxial layer during the epitaxial growth process, and introducing a third doping ion into the heavily doped epitaxial layer to form the fin electrical connection region 208.

[0085] In other embodiments, the fin electrical connection region 208 may be formed by an ion implantation process.

[0086] Please continue to refer to Figure 7 A first fin electrical connection area group 209 is formed in the first well area 206, and the first fin electrical connection area group 209 includes a first N-type fin electrical connection area 210 and a first P-type fin electrical connection area 211. The first N-type fin electrical connection area 210 and the first P-type fin electrical connection area 211 are isolated from each other by the second isolation structure 204. The third isolation structure 205 of the first well area 206 is formed between the first N-type fin electrical connection areas and the first P-type fin electrical connection areas, respectively.

[0087] In this embodiment, the first fin electrical connection area group 209 is connected to a power supply voltage (VDD).

[0088] In other embodiments, the first fin electrical connection region group 209 is connected to a ground voltage (VSS).

[0089] In this embodiment, the method for forming the first N-type fin electrical connection region 210 and the first P-type fin electrical connection region 211 includes: forming a patterned layer on the substrate 200, etching the fin 201 of the first region I using the patterned layer as a mask, forming a first N-type heavily doped opening (not marked) and a first P-type heavily doped opening (not marked) in the fin 201, forming the first N-type fin electrical connection region 210 in the first N-type heavily doped opening, and forming the first P-type fin electrical connection region 211 in the first P-type heavily doped opening.

[0090] In this embodiment, the method for forming the first N-type fin electrical connection region 210 and the first P-type fin electrical connection region 211 includes: forming a first N-type heavily doped epitaxial layer (not shown) and a first P-type heavily doped epitaxial layer (not shown) in the first N-type heavily doped opening (not shown) and in the first P-type heavily doped opening using an epitaxial growth process; in-situ doping the first N-type heavily doped epitaxial layer and the first P-type heavily doped epitaxial layer during the epitaxial growth process, doping the first N-type heavily doped epitaxial layer with first N-type doping ions to form the first N-type fin electrical connection region 210, and doping the first P-type heavily doped epitaxial layer with first P-type doping ions to form the first P-type fin electrical connection region 211.

[0091] In other embodiments, the first N-type fin electrical connection region 210 and the first P-type fin electrical connection region 211 may be formed by an ion implantation process.

[0092] Please continue to refer to Figure 7 , also includes: forming a second fin electrical connection area group 212 in the second well area 207, the second fin electrical connection area group 212 includes a second N-type fin electrical connection area 213 and a second P-type fin electrical connection area 214, the second N-type fin electrical connection area 213 and the second P-type fin electrical connection area 214 are isolated by the second isolation structure 204, and the third isolation structure 205 formed in the second well area 207 is formed between the second N-type fin electrical connection area 213 and the second P-type fin electrical connection area 214 respectively.

[0093] In this embodiment, the second fin electrical connection area group 212 is connected to the ground voltage (VSS).

[0094] In other embodiments, the second fin electrical connection region group 212 is connected to a power supply voltage (VDD).

[0095] In this embodiment, the method for forming the second N-type fin electrical connection region 213 and the second P-type fin electrical connection region 214 includes: forming a patterned layer on the substrate 200, etching the fin 201 of the second region II using the patterned layer as a mask, forming a second N-type heavily doped opening (not marked) and a second P-type heavily doped opening (not marked) in the fin 201, forming the second N-type fin electrical connection region 213 in the second N-type heavily doped opening, and forming the second P-type fin electrical connection region 214 in the second P-type heavily doped opening.

[0096] In this embodiment, the method for forming the second N-type fin electrical connection region 213 and the second P-type fin electrical connection region 214 includes: forming a second N-type heavily doped epitaxial layer (not shown) and a second P-type heavily doped epitaxial layer (not shown) in the second N-type heavily doped opening (not shown) and the second P-type heavily doped opening using an epitaxial growth process; in-situ doping the second N-type heavily doped epitaxial layer and the second P-type heavily doped epitaxial layer during the epitaxial growth process, doping the second N-type heavily doped epitaxial layer with second N-type doping ions to form the second N-type fin electrical connection region 213, and doping the second P-type heavily doped epitaxial layer with second P-type doping ions to form the second P-type fin electrical connection region 214.

[0097] In other embodiments, the second N-type fin electrical connection region 213 and the second P-type fin electrical connection region 212 may be formed by an ion implantation process.

[0098] Please refer to Figure 8 A heavily doped region 215 is formed at the bottom of the fin electrical connection region 208 . The heavily doped region 215 contains fourth doping ions, and the fourth doping ions have a different conductivity type from the third doping ions.

[0099] The fourth doping ion includes an N-type ion, and the fourth doping ion includes phosphorus or arsenic. In this embodiment, the fourth doping ion is phosphorus.

[0100] In this embodiment, the heavily doped region 215 is formed by an ion implantation process.

[0101] In this embodiment, the doping depth of the heavily doped region 215 is less than the depth of the first isolation structure 203. The purpose of this setting is to electrically isolate the portion of the heavily doped region located in the second well region from the first well region, so that it can be coupled to VDD through the first isolation structure 203.

[0102] In this embodiment, due to the presence of the heavily doped region 215, the junction area of ​​the first well region and the second well region is expanded, and the fin electrical connection region 208 is not affected by the increase in VSS. The fin electrical connection region 208 and the second well region 207 are isolated by the heavily doped region 215. The heavily doped region 215 is isolated from the first well region 206 by the first isolation structure 203. A capacitor can be formed between the heavily doped region 215 and the fin electrical connection region 208 through the first isolation structure 203. Subsequently, different potentials are coupled out by the VDD end. When an ESD event occurs, the VDD potential gradually increases. At this time, the capacitance between the fin electrical connection region 208 and VDD is small, while the capacitance between the heavily doped region 215 and VDD is large, so that the capacitance at the fin electrical connection region 208 can be increased faster. At this time, the PN diode is turned on, and after being turned on, a PNP transistor is formed with the second well region, causing the transistor to be turned on. At this time, the trigger voltage of the SCR structure is reduced. Since the trigger voltage is reduced, the circuit is protected.

[0103] Accordingly, the present invention also provides an electrostatic discharge protection structure, comprising: a substrate 200 having a first isolation structure group thereon, the first isolation structure group including a plurality of first isolation structures 203; a first well region 206 and a second well region 207 located on the substrate 200, the first well region 206 and the second well region 207 being connected, the first well region 206 having first dopant ions therein, the second well region 207 having second dopant ions therein, the first dopant ions and the second dopant ions having different conductivity types, the first isolation structure group being located at the connection between the first well region and the second well region, The first isolation structure 203 is located in both the first well region 206 and the second well region 207; the fin electrical connection region 208 is located at the connection between the first well region 206 and the second well region 207, and the first isolation structure 203 is located between the fin electrical connection regions 208, and the fin electrical connection region 208 has a third doping ion, and the third doping ion has the same conductivity type as the second doping ion; the heavily doped region 215 is located at the bottom of the fin electrical connection region 208, and the heavily doped region 215 has a fourth doping ion, and the fourth doping ion has a different conductivity type from the third doping ion.

[0104] In this embodiment, the first doping ions include N-type ions; the first doping ions include phosphorus or arsenic.

[0105] In this embodiment, the second doping ions include P-type ions; the second doping ions include boron or indium.

[0106] In this embodiment, due to the presence of the heavily doped region 215, isolation is formed between the fin electrical connection region 208 and the second well region 207. The heavily doped region 215 is isolated from the first well region 206 through the first isolation structure 203. A capacitor can be formed between the heavily doped region 215 and the fin electrical connection region 208 through the first isolation structure 203. Subsequently, different potentials are coupled out from the VDD end. When ESD time occurs, the VDD potential gradually increases. At this time, the capacitance between the fin electrical connection region 208 and VDD is small, while the capacitance between the heavily doped region 215 and VDD is large, so that the capacitance at the fin electrical connection region 208 can be increased faster. At this time, the PN diode is turned on, and after being turned on, a PNP transistor is formed with the second well region, causing the transistor to be turned on. At this time, the trigger voltage of the SCR structure is reduced. Since the trigger voltage is reduced, the circuit is protected.

[0107] In this embodiment, the present invention further includes: a plurality of second isolation structures 204 located on the substrate 200 , wherein the width of the second isolation structure 204 is greater than the width of the first isolation structure 203 .

[0108] In this embodiment, the width of the second isolation structure 204 is greater than that of the first isolation structure 203. The purpose of making the first isolation structure 203 have a smaller width is that the heavily doped region is isolated from the first well region by a larger capacitance, so that the VDD coupling voltage is slower than that of the fin electrical connection region.

[0109] In this embodiment, the doping depth of the heavily doped region 215 is less than the depth of the first isolation structure 203. The purpose of this setting is to electrically isolate the portion of the heavily doped region located in the second well region from the first well region, so that it can be coupled to VDD through the first isolation structure 203.

[0110] In this embodiment, the present invention further includes: a third isolation structure 205 located on the substrate 200 . The third isolation structure 205 is located between adjacent second isolation structures 204 . The width of the third isolation structure 205 is smaller than that of the second isolation structure 204 .

[0111] In this embodiment, the substrate includes a base and a fin located on the base, wherein the fin has the first well region and the second well region, the first isolation structure group, the heavily doped region, and the fin electrical connection region.

[0112] In this embodiment, it also includes: a first fin electrical connection area group 209, located in the first well area 206, the first fin electrical connection area group 209 includes a first N-type fin electrical connection area 210 and a first P-type fin electrical connection area 211, the first N-type fin electrical connection area 210 and the first P-type fin electrical connection area 211 are isolated by the second isolation structure 204, and the third isolation structure 205 of the first well area 206 is respectively formed between the first N-type fin electrical connection area and the first P-type fin electrical connection area.

[0113] In this embodiment, it also includes: a second fin electrical connection area group 212 is located in the second well area 207, the second fin electrical connection area group 212 includes a second N-type fin electrical connection area 213 and a second P-type fin electrical connection area 214, the second N-type fin electrical connection area 213 and the second P-type fin electrical connection area 214 are isolated by the second isolation structure 204, and the third isolation structure 205 formed in the second well area 207 is formed between the second N-type fin electrical connection area 213 and the second P-type fin electrical connection area 214 respectively.

[0114] In this embodiment, the first fin electrical connection area group 209 is connected to a power supply voltage (VDD).

[0115] In other embodiments, the first fin electrical connection region group 209 may also be connected to a ground voltage (VSS).

[0116] In this embodiment, the second fin electrical connection region group 212 is connected to a ground voltage (VSS).

[0117] In other embodiments, the second fin electrical connection region group 212 may also be connected to a power supply voltage (VDD).

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An electrostatic discharge protection structure, characterized in that: include: a substrate having a first isolation structure group thereon, wherein the first isolation structure group includes a plurality of first isolation structures; a first well region and a second well region located on the substrate, the first well region and the second well region being connected, the first well region having first dopant ions, the second well region having second dopant ions, the first dopant ions and the second dopant ions having different conductivity types, the first isolation structure being located at the connection between the first well region and the second well region, and the first isolation structure being located in both the first well region and the second well region; a fin electrical connection region, located at a connection between the first well region and the second well region, wherein the first isolation structure is located between the fin electrical connection regions, and wherein third dopant ions are present in the fin electrical connection region, and wherein the third dopant ions have the same conductivity type as the second dopant ions; The heavily doped region is located at the bottom of the fin electrical connection region. The heavily doped region contains fourth doping ions, and the fourth doping ions have a different conductivity type from the third doping ions.

2. The electrostatic discharge protection structure according to claim 1, wherein: The fin electrical connection region includes one or both of a source / drain doped region located on the fin and a gate structure located on the fin.

3. The electrostatic discharge protection structure according to claim 2, wherein: Also includes: A plurality of second isolation structures are located on the substrate, wherein the width of the second isolation structure is greater than the width of the first isolation structure.

4. The electrostatic discharge protection structure according to claim 1, wherein: The doping depth of the heavily doped region is less than that of the first isolation structure.

5. The electrostatic discharge protection structure according to claim 3, wherein: Also includes: A third isolation structure is located on the substrate, the third isolation structure is located between adjacent second isolation structures, and the width of the third isolation structure is smaller than the width of the second isolation structure.

6. The electrostatic discharge protection structure according to claim 1, wherein: The first doping ions include N-type ions; the first doping ions include phosphorus or arsenic.

7. The electrostatic discharge protection structure according to claim 1, wherein: The second doping ions include P-type ions; The second doping ions include boron or indium.

8. The electrostatic discharge protection structure according to claim 1, wherein: The substrate includes a base and a fin located on the base. The fin has the first well region and the second well region, the first isolation structure, the heavily doped region, and the fin electrical connection region located on the fin.

9. The electrostatic discharge protection structure according to claim 5, wherein: When the fin electrical connection region is a source-drain doped region located on the fin, the fin electrical connection region also includes: a first fin electrical connection region group, located in the first well region, including a first N-type fin electrical connection region and a first P-type fin electrical connection region, the first N-type fin electrical connection region and the first P-type fin electrical connection region are isolated by the second isolation structure, and the third isolation structure located in the first well region is respectively located between the first N-type fin electrical connection region and the first P-type fin electrical connection region.

10. The electrostatic discharge protection structure according to claim 9, wherein: The fin electrical connection area also includes: a second fin electrical connection area group, located in the second well area, including a second N-type fin electrical connection area and a second P-type fin electrical connection area, the second N-type fin electrical connection area and the second P-type fin electrical connection area are isolated by the second isolation structure, and the third isolation structure located in the second well area is respectively located between the second N-type fin electrical connection areas and the second P-type fin electrical connection areas.

11. The electrostatic discharge protection structure according to claim 9, wherein: The first fin electrical connection area group is connected to a power supply voltage or a ground voltage.

12. The electrostatic discharge protection structure according to claim 10, wherein: The second fin electrical connection area group is connected to a ground voltage or a power supply voltage.

13. A method for forming an electrostatic discharge protection structure, characterized in that: include: Providing a substrate, forming a first isolation structure group on the substrate, wherein the first isolation structure group includes a plurality of first isolation structures; forming a first well region and a second well region on the substrate, the first well region and the second well region being connected, the first well region having first dopant ions, the second well region having second dopant ions, the first dopant ions and the second dopant ions having different conductivity types, the first isolation structure being located at the connection between the first well region and the second well region, and the first isolation structure being located in both the first well region and the second well region; forming a fin electrical connection region at a connection between the first well region and the second well region, wherein the first isolation structure is provided between the fin electrical connection regions, and wherein third doping ions are provided in the fin electrical connection region, wherein the third doping ions have the same conductivity type as the second doping ions; A heavily doped region is formed at the bottom of the fin electrical connection region. The heavily doped region contains fourth doping ions, and the fourth doping ions have a different conductivity type from the third doping ions.

14. The method for forming an electrostatic discharge protection structure according to claim 13, wherein: Also includes: A plurality of second isolation structures are formed on the substrate, wherein the width of the second isolation structure is greater than the width of the first isolation structure.

15. The method for forming an electrostatic discharge protection structure according to claim 13, wherein: The doping depth of the heavily doped region is less than that of the first isolation structure.

16. The method for forming an electrostatic discharge protection structure according to claim 14, wherein: Also includes: A third isolation structure is formed on the substrate, and the third isolation structure is located between adjacent second isolation structures. The width of the third isolation structure is smaller than that of the second isolation structure.

17. The method for forming an electrostatic discharge protection structure according to claim 13, wherein: The first doping ions include N-type ions; the first doping ions include phosphorus or arsenic.

18. The method for forming an electrostatic discharge protection structure according to claim 13, wherein: The second doping ions include P-type ions; The second doping ions include boron or indium.

19. The method for forming an electrostatic discharge protection structure according to claim 16, wherein: The substrate includes a base and a fin formed on the base, and the first well region, the second well region, the first isolation structure group, the heavily doped region, and the fin electrical connection region located on the fin are formed in the fin.

20. The method for forming an electrostatic discharge protection structure according to claim 19, wherein: The fin electrical connection region includes one or both of a source / drain doped region located on the fin and a gate structure located on the fin.

21. The method for forming an electrostatic discharge protection structure according to claim 20, wherein: When the fin electrical connection region is a source-drain doped region located on the fin, the fin electrical connection region also includes: forming a first fin electrical connection region group in the first well region, the first fin electrical connection region group including a first N-type fin electrical connection region and a first P-type fin electrical connection region, the first N-type fin electrical connection region and the first P-type fin electrical connection region are isolated by the second isolation structure, and the third isolation structure of the first well region is respectively formed between the first N-type fin electrical connection region and the first P-type fin electrical connection region.

22. The method for forming an electrostatic discharge protection structure according to claim 21, wherein: The fin electrical connection area also includes: a second fin electrical connection area group is formed in the second well area, the second fin electrical connection area group includes a second N-type fin electrical connection area and a second P-type fin electrical connection area, the second N-type fin electrical connection area and the second P-type fin electrical connection area are isolated by the second isolation structure, and the third isolation structure formed in the second well area is formed between the second N-type fin electrical connection areas and the second P-type fin electrical connection areas, respectively.

23. The method for forming an electrostatic discharge protection structure according to claim 21, wherein: The first fin electrical connection area group is connected to a power supply voltage or a ground voltage.

24. The method for forming an electrostatic discharge protection structure according to claim 22, wherein: The second fin electrical connection area group is connected to a ground voltage or a power supply voltage.

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