Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same. In a first transistor structure of the semiconductor structure, a projection of a first channel layer on a substrate is a first pattern, a projection of a first gate electrode layer on the substrate is a second pattern, and a projection of a first source / drain doping layer on the substrate is a third pattern. In a second transistor structure, a projection of a second channel layer on the substrate is a fourth pattern, and a projection of a second gate electrode layer on the substrate is a fifth pattern. In a second direction, adjacent first and fourth patterns partially overlap or are arranged side by side. In a first direction, adjacent second and fifth patterns partially overlap or are arranged side by side, and the adjacent fifth pattern exposes a part of the third pattern between the adjacent second patterns. Therefore, the probability that the first gate electrode layer and the first source / drain doping layer are completely blocked by the second transistor structure is relatively low, so that it is easy to electrically lead out the first gate electrode layer and the first source / drain doping layer in the first transistor structure through plugs.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large scale integrated circuits, the feature size of integrated circuits continues to decrease. To adapt to the reduction of the feature size, the channel length of MOSFETs is also continuously shortened accordingly. However, as the device channel length is shortened, the distance between the source and drain of the device is also shortened, so the gate's control ability over the channel becomes worse, and it becomes more and more difficult for the gate voltage to pinch off the channel, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the reduction of the feature size, semiconductor processes have gradually started to transition from planar MOSFETs to three-dimensional transistors with higher efficiency.

[0004] Among them, complementary FETs (CFETs) composed of vertical stacks are a revolutionary three-dimensional transistor. In the CFET structure, PMOS transistors and NMOS transistors stacked vertically with each other form complementary devices, which can thus save area, increase the transistor integration density, and thus bring benefits in terms of power consumption and cost performance. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are easy to lead out the electrical properties of the first transistor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a first transistor structure, including a substrate, a first channel layer located on the substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and first source / drain doping layers on the substrate on both sides of the first gate electrode layer, the first source / drain doping layers being in contact with ends of the first channel layer below the first gate electrode layer, the first channel layer extending in a first direction, the first gate electrode layer extending in a second direction, and the first direction and the second direction being perpendicular to each other, the first transistor structure having a bonding surface on one side of the first gate electrode layer; a bonding layer located on the bonding surface of the first transistor structure; a second transistor structure located on the bonding layer, the second transistor structure including a second channel layer, a second gate dielectric layer covering the second channel layer, a second gate electrode layer covering the second gate dielectric layer, and second source / drain doping layers on the bonding layer on both sides of the second gate electrode layer, the second source / drain doping layers being in contact with ends of the second channel layer below the second gate electrode layer, the second channel layer extending in the first direction, the second gate electrode layer extending in the second direction; wherein, a projection of the first channel layer on the substrate is a first pattern, a projection of the first gate electrode layer on the substrate is a second pattern, a projection of the first source / drain doping layer on the substrate is a third pattern, a projection of the second channel layer on the substrate is a fourth pattern, a projection of the second gate electrode layer on the substrate is a fifth pattern, in the second direction, adjacent the first pattern and the fourth pattern partially overlap or are arranged side by side, in the first direction, adjacent the second pattern and the fifth pattern partially overlap or are arranged side by side, and the adjacent fifth pattern exposes a part of the third pattern between the adjacent second patterns.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: forming a first transistor structure, where the first transistor structure includes a first substrate, a first channel layer located on the first substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and first source / drain doping layers on the first substrate on both sides of the first gate electrode layer, the first source / drain doping layers are in contact with the ends of the first channel layer located below the first gate electrode layer, the first transistor structure has a bonding surface on one side of the first gate electrode layer, wherein the first channel layer extends in a first direction, the first gate electrode layer extends in a second direction, and the first direction and the second direction are perpendicular to each other, the projection of the first channel layer on the first substrate is a first pattern, the projection of the first gate electrode layer on the first substrate is a second pattern, and the projection of the first source / drain doping layers on the first substrate is a third pattern; bonding a second substrate to the bonding surface using a bonding layer; patterning the second substrate to form a second channel layer extending in the first direction, the projection of the second channel layer on the first substrate is a fourth pattern, and in the second direction, adjacent to the first pattern and the fourth pattern are partially overlapped or arranged side by side; forming a second gate dielectric layer covering the second channel layer, a second gate electrode layer spanning the second channel layer and covering the second gate dielectric layer, and second source / drain doping layers on the bonding layer on both sides of the second gate electrode layer, the second gate electrode layer extends in the second direction, the second source / drain doping layers are in contact with the ends of the second channel layer located below the second gate electrode layer, and the second gate electrode layer, the second gate dielectric layer, the second source / drain doping layers and the second channel layer are used to form a second transistor structure, wherein the projection of the second gate electrode layer on the first substrate is a fifth pattern, in the first direction, adjacent to the second pattern and the fifth pattern are partially overlapped or arranged side by side, and adjacent to the fifth pattern exposes a part of the third pattern between the adjacent second patterns.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, for the first transistor structure, the projection of the first channel layer on the substrate is a first pattern, the projection of the first gate electrode layer on the substrate is a second pattern, and the projection of the first source-drain doping layer on the substrate is a third pattern. For the second transistor structure, the projection of the second channel layer on the substrate is a fourth pattern, and the projection of the second gate electrode layer on the substrate is a fifth pattern. In the second direction, adjacent the first pattern and the fourth pattern partially overlap or are arranged side by side. In the first direction, adjacent the second pattern and the fifth pattern partially overlap or are arranged side by side, and the adjacent fifth pattern exposes a part of the third pattern between the adjacent second patterns. That is to say, the first channel layer in the first transistor structure and the second channel layer in the second transistor structure are staggered in the horizontal direction, the first gate electrode layer in the first transistor structure and the second gate electrode layer in the second transistor structure are staggered in the horizontal direction, and the first source-drain doping layer and the second gate electrode layer are also staggered in the horizontal direction. Therefore, the probability that the first gate electrode layer and the first source-drain doping layer in the first transistor structure are completely blocked by the second transistor structure is relatively low. Correspondingly, when it is necessary to electrically lead out the first source-drain doping layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to form a source-drain plug (contact, CT) electrically connected to the first source-drain doping layer, or to form a gate plug electrically connected to the first gate electrode layer, the probability that the formation process of the plug is blocked by the second transistor structure can be reduced, so that it is easy to electrically lead out the first gate electrode layer and the first source-drain doping layer in the first transistor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, after patterning a second substrate and forming a second channel layer extending in a first direction, the projection of the second channel layer on the first substrate is a fourth pattern. In a second direction, the adjacent first pattern and the fourth pattern partially overlap or are arranged side by side. After forming a second gate dielectric layer covering the second channel layer, a second gate electrode layer spanning the second channel layer and covering the second gate dielectric layer, and second source / drain doping layers on bonding layers located on both sides of the second gate electrode layer, the projection of the second gate electrode layer on the first substrate is a fifth pattern. In the first direction, the adjacent second pattern and the fifth pattern partially overlap or are arranged side by side, and the adjacent fifth pattern exposes a part of the third pattern between the adjacent second patterns; that is to say, the first channel layer in the first transistor structure and the second channel layer in the second transistor structure are staggered in the horizontal direction, the first gate electrode layer in the first transistor structure and the second gate electrode layer in the second transistor structure are staggered in the horizontal direction, and the first source / drain doping layer and the second gate electrode layer are also staggered in the horizontal direction. Therefore, the probability that the first gate electrode layer and the first source / drain doping layer in the first transistor structure are completely blocked by the second transistor structure is relatively low. Correspondingly, when it is necessary to lead out the electrical properties of the first source / drain doping layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to form a source / drain plug electrically connected to the first source / drain doping layer, or to form a gate plug electrically connected to the first gate electrode layer, the probability that the formation process of the plug is blocked by the second transistor structure can be reduced, so that it is easy to lead out the electrical properties of the first gate electrode layer and the first source / drain doping layer in the first transistor structure. Description of the Drawings

[0011] Figure 1 is a perspective view of a semiconductor structure;

[0012] Figure 2 is a perspective view of an embodiment of the semiconductor structure of the present invention;

[0013] Figure 3 is a schematic diagram of the projection patterns of the first channel layer, the first gate electrode layer, the first source / drain doping layer, the second channel layer, and the second gate electrode layer on the substrate in an embodiment of the semiconductor structure of the present invention;

[0014] Figure 4 is a cross-sectional view along the second direction in an embodiment of the semiconductor structure of the present invention;

[0015] Figure 5 is a cross-sectional view along the first direction and at the top position of the second gate layer in an embodiment of the semiconductor structure of the present invention;

[0016] Figure 6 is a cross-sectional view along the first direction and at the side position of the second gate layer in an embodiment of the semiconductor structure of the present invention.

[0017] Figures 7 to 23 It is a schematic diagram of the structures corresponding to the steps in an embodiment of the method for forming a semiconductor structure of the present invention. Detailed implementation manners

[0018] As can be seen from the background art, the CFET structure includes a PMOS transistor and an NMOS transistor vertically stacked with each other. However, it is currently difficult to lead out the electrical properties of the lower transistor in the CFET structure.

[0019] Now, in combination with a semiconductor structure, analyze the reasons why it is difficult to lead out the electrical properties of the lower transistor in the CFET structure.

[0020] Reference Figure 1 , which shows a perspective view of a semiconductor structure.

[0021] The semiconductor structure includes: a first transistor structure 10, including a substrate 11, a first channel layer 12 located on the substrate 11, a first gate structure 13 spanning the first channel layer 12, and a first source / drain doping layer (not shown in the figure) in the first channel layer 12 on both sides of the first gate structure 13. The first transistor structure 10 has a bonding surface (not labeled) on one side of the first gate structure 13; a bonding layer 30 located on the bonding surface; a second transistor structure 20 located on the bonding layer 30. The second transistor structure 20 includes a second channel layer 22, a second gate structure 23 covering the second channel layer 22, and a second source / drain doping layer (not shown in the figure) in the second channel layer 22 on both sides of the second gate structure 23.

[0022] The semiconductor structure is a sequential CFET structure. Specifically, the first transistor structure 10 and the second transistor structure 20 are separately fabricated using separate silicon wafers, and the first transistor structure 10 and the second transistor structure 20 are bonded together by bonding.

[0023] The first source / drain doping layer and the second source / drain doping layer are independently formed. The second channel layer 22 is located directly above the first channel layer 12, and the second gate structure 23 is located directly above the first gate structure 13. Therefore, in the direction from the second transistor structure 20 to the first transistor structure 10, the second channel layer 22 completely blocks the first channel layer 12, and the second gate structure 23 completely blocks the first gate structure 13. For example, the projection of the first channel layer 12 on the substrate 11 is located within the projection of the second channel layer 22 on the substrate 11, and the projections of the second gate structure 23 and the first gate structure 13 on the substrate 11 coincide.

[0024] The semiconductor structure needs to achieve vertical integration and electrical isolation between the first transistor structure 10 and the second transistor structure 20 simultaneously. However, since the second channel layer 22 completely obscures the first channel layer 12, and the second gate structure 23 completely obscures the first gate structure 13, the second transistor structure 20 completely obscures the first source-drain doping layer and the first gate structure 13 in the first transistor structure, making it difficult to lead out the electrical properties of the first source-drain doping layer and the first gate structure 13. Specifically, it is difficult to form a source-drain plug on top of the first source-drain doping layer and a gate plug on top of the first gate structure 13.

[0025] To solve the above technical problem, in the semiconductor structure provided by the embodiment of the present invention, for the first transistor structure, the projection of the first channel layer on the substrate is a first pattern, the projection of the first gate electrode layer on the substrate is a second pattern, and the projection of the first source-drain doping layer on the substrate is a third pattern. For the second transistor structure, the projection of the second channel layer on the substrate is a fourth pattern, and the projection of the second gate electrode layer on the substrate is a fifth pattern. In the second direction, the adjacent first pattern and fourth pattern partially overlap or are arranged side by side. In the first direction, the adjacent second pattern and fifth pattern partially overlap or are arranged side by side, and the adjacent fifth pattern exposes a part of the third pattern between the adjacent second patterns. That is to say, the first channel layer in the first transistor structure and the second channel layer in the second transistor structure are staggered in the horizontal direction, the first gate electrode layer in the first transistor structure and the second gate electrode layer in the second transistor structure are staggered in the horizontal direction, and the first source-drain doping layer and the second gate electrode layer are also staggered in the horizontal direction. Therefore, the probability that the first gate electrode layer and the first source-drain doping layer in the first transistor structure are completely obscured by the second transistor structure is relatively low. Correspondingly, when it is necessary to lead out the electrical properties of the first source-drain doping layer or the first gate electrode layer in the first transistor structure, for example, when it is necessary to form a source-drain plug electrically connected to the first source-drain doping layer or a gate plug electrically connected to the first gate electrode layer, the probability that the formation process of the plug is blocked by the second transistor structure can be reduced, making it easy to lead out the electrical properties of the first gate electrode layer and the first source-drain doping layer in the first transistor structure.

[0026] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0027] With reference to Figures 2 to 6 , Figure 2 is a perspective view of an embodiment of the semiconductor structure of the present invention, Figure 3 is a schematic diagram of the projection patterns of the first channel layer, the first gate electrode layer, the first source-drain doping layer, the second channel layer, and the second gate electrode layer on the substrate in an embodiment of the semiconductor structure of the present invention.Figure 4 is a cross-sectional view along the second direction in an embodiment of the semiconductor structure of the present invention, Figure 5 is a cross-sectional view along the first direction and at the top position of the second gate layer in an embodiment of the semiconductor structure of the present invention, Figure 6 is a cross-sectional view along the first direction and at the side position of the second gate layer in an embodiment of the semiconductor structure of the present invention.

[0028] Wherein, for the convenience of illustration, Figure 2 only the substrate, the first gate electrode layer, the first source / drain doping layer, the bonding layer, the second gate electrode layer, the second source / drain doping layer, the bottom source / drain plug, and the top source / drain plug are schematically shown in

[0029] The semiconductor structure includes: a first transistor structure 400, including a substrate 410, a first channel layer 470 located on the substrate 410, a first gate dielectric layer 430 covering the first channel layer 470, a first gate electrode layer 460 covering the first gate dielectric layer 430, and first source / drain doping layers 403 on the substrate 410 on both sides of the first gate electrode layer 460 (as shown in Figure 2 ), the first source / drain doping layers 403 are in contact with the ends of the first channel layer 470 located below the first gate electrode layer 460, the first channel layer 470 extends along a first direction (as shown by the X direction in Figure 2 ), the first gate electrode layer 460 extends along a second direction (as shown by the Y direction in Figure 2 ), and the first direction and the second direction are perpendicular to each other, the first transistor structure 400 has a bonding surface 401 on one side of the first gate electrode layer 460; a bonding layer 500, located on the bonding surface 401 of the first transistor structure 400; a second transistor structure 600, located on the bonding layer 500, the second transistor structure 600 includes a second channel layer 520, a second gate dielectric layer 610 covering the second channel layer 520, a second gate electrode layer 690 covering the second gate dielectric layer 610, and second source / drain doping layers 601 on the bonding layer 500 on both sides of the second gate electrode layer 690 (as shown in Figure 4 ), the second source / drain doping layers 601 are in contact with the ends of the second channel layer 520 located below the second gate electrode layer 690, the second channel layer 520 extends along the first direction, the second gate electrode layer 690 extends along the second direction; wherein, the projection of the first channel layer 470 on the substrate 410 is a first pattern 1 (as shown in Figure 3 ), the projection of the first gate electrode layer 460 on the substrate 410 is a second pattern 2 (as shown in Figure 3 ), the projection of the first source / drain doping layers 403 on the substrate 410 is a third pattern 3 (as shown in Figure 3As shown, the projection of the second channel layer 520 on the substrate 410 is the fourth pattern 4 (as Figure 3 shown), the projection of the second gate electrode layer 690 on the substrate 410 is the fifth pattern 5 (as Figure 3 shown). In the second direction, the adjacent first pattern 1 and the fourth pattern 4 partially overlap or are arranged side by side. In the first direction, the adjacent second pattern 2 and the fifth pattern 5 partially overlap or are arranged side by side, and the adjacent fifth pattern 5 exposes a part of the third pattern 3 between the adjacent second patterns 2.

[0030] In this embodiment, the first channel layer 470 in the first transistor structure 400 and the second channel layer 520 in the second transistor structure 600 are staggered in the horizontal direction. The first gate electrode layer 460 in the first transistor structure 400 and the second gate electrode layer 690 in the second transistor structure 600 are staggered in the horizontal direction, and the first source / drain doping layer 403 and the second gate electrode layer 690 are also staggered in the horizontal direction. Therefore, the probability that the first gate electrode layer 460 and the first source / drain doping layer 403 in the first transistor structure 400 are completely blocked by the second transistor structure 600 is relatively low. Correspondingly, when it is necessary to lead out the electrical properties of the first source / drain doping layer 403 or the first gate electrode layer 460 in the first transistor structure 400, for example, when it is necessary to form a source / drain plug (contact, CT) electrically connected to the first source / drain doping layer 403, or to form a gate plug electrically connected to the first gate electrode layer 460, the probability that the formation process of the plug is blocked by the second transistor structure 600 can be reduced, so that it is easy to lead out the electrical properties of the first gate electrode layer 460 and the first source / drain doping layer 403 in the first transistor structure 400.

[0031] The semiconductor structure is a CFET structure. The first transistor structure 400 includes a first transistor, and the first transistor is the bottom transistor in the CFET structure. The first transistor includes a first channel layer 470, a first gate dielectric layer 430, a first gate electrode layer 460, and a first source / drain doping layer 403, so as to realize the normal function of the first transistor. In the CFET structure, PMOS transistors and NMOS transistors vertically stacked with each other form complementary devices. Therefore, according to the channel conduction type of the first transistor in the first transistor structure 400, the first transistor can be an NMOS transistor or a PMOS transistor.

[0032] As an example, the first transistor in the first transistor structure 400 is an NMOS transistor. According to the structural type of the first transistor structure 400, the first transistor structure 400 includes a fin field-effect transistor (FinFET) or a gate-all-around (GAA) transistor. Specifically, the GAA transistor can be a horizontal nanosheets transistor. In this embodiment, the first transistor is taken as an example of a GAA transistor.

[0033] The substrate 410 is used to provide a process platform for the formation of a semiconductor structure. In this embodiment, taking the first transistor as an example of a GAA transistor, the substrate 410 includes a substrate 411, fins 413 protruding on the substrate 411, and an isolation layer 412 located on the substrate 411, and the isolation layer 412 covers the sidewalls of the fins 413.

[0034] In this embodiment, the material of the substrate 411 is silicon. In some other embodiments, the material of the substrate 411 can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate 411 can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. As an example, the fins 413 and the substrate 411 are an integral structure.

[0035] In this embodiment, the isolation layer 412 can be a shallow trench isolation structure (STI). The material of the isolation layer 412 is an insulating material. As an example, the material of the isolation layer 412 is silicon oxide.

[0036] The first channel layer 470 is used to provide a channel for the first transistor. In this embodiment, taking the first transistor as an example of a GAA transistor, the first channel layer 470 is located on the substrate 410 and is spaced apart from the substrate 410. Specifically, the first channel layer 470 is located on the fins 413 and is spaced apart from the fins 413. The first channel layer 470 includes one or more first sub-channel layers 476 arranged at intervals. It should be noted that only one first sub-channel layer 476 is illustrated in this embodiment, but the number of the first sub-channel layers 476 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin protruding on the substrate.

[0037] The material of the first channel layer 470 includes silicon, silicon germanide, germanium, or a III-V group semiconductor material. The material of the first channel layer 470 is determined according to the channel conduction type and performance requirements of the first transistor. As an example, the material of the first channel layer 470 is silicon.

[0038] With reference to Figure 2 and Figure 3, in this embodiment, in the first transistor structure 400, the number of the first channel layers 470 is multiple, and the multiple first channel layers 470 are arranged in parallel along the second direction (as shown by the Y direction), and the sum of the width W1 of the first channel layer 470 and the interval S1 between adjacent first channel layers is a first preset pitch P1.

[0039] The first gate electrode layer 460 is used to control the opening or closing of the channel of the first transistor. In this embodiment, the first gate electrode layer 460 surrounds and covers the first gate dielectric layer 430 on the first channel layer 470. In other embodiments, when the first channel layer is the first fin protruding from the substrate, correspondingly, the first gate electrode layer straddles the first fin and covers the first gate dielectric layer on part of the top and part of the sidewalls of the first fin.

[0040] Combined with reference to Figure 2 and Figure 3 , in this embodiment, in the first transistor structure 400, the number of the first gate electrode layers 460 is multiple, and the multiple first gate electrode layers 460 are arranged in parallel along the first direction (as shown by the X direction), and the sum of the width W2 of the first gate electrode layer 460 and the interval S2 between adjacent first gate electrode layers 460 is a second preset pitch P2.

[0041] In this embodiment, the first gate electrode layer 460 and the first channel layer 470 are orthogonal. Therefore, the first channel layer 470 extends along the first direction, the first gate electrode layer 460 extends along the second direction, and the first direction and the second direction are perpendicular to each other.

[0042] In this embodiment, the first gate electrode layer 460 is a metal gate electrode layer. The material of the first gate electrode layer 460 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. As an example, the first gate electrode layer 460 includes a first work function layer 440 and a first electrode layer 450 covering the first work function layer 440. Among them, the first work function layer 440 is used to adjust the threshold voltage of the first transistor, and the first electrode layer 450 is used to lead out the electric property of the first gate electrode layer 460.

[0043] In this embodiment, the first gate dielectric layer 430 is located between the first gate electrode layer 460 and the first channel layer 470. The first gate dielectric layer 430 is used to isolate the first gate electrode layer 460 and the first channel layer 470. The material of the first gate dielectric layer 430 includes HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3, SiO 2 and La 2 O 3 One or more of them. In this embodiment, the first gate dielectric layer 430 includes a first gate oxide layer (not shown in the figure) and a first high-k gate dielectric layer covering the first gate oxide layer (not shown in the figure).

[0044] In this embodiment, the material of the first gate oxide layer is silicon oxide, and the material of the first high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the first high-k gate dielectric layer can be selected from HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al 2 O 3 etc. As an example, the material of the first high-k gate dielectric layer is HfO 2 .

[0045] It should be noted that the first gate dielectric layer 430 and the first gate electrode layer 460 are formed by the process of forming the high-k gate dielectric layer first and then the gate electrode layer (high k last metal gate last). Therefore, the first gate dielectric layer 430 is also located between the bottom of the first gate electrode layer 460 and the substrate 110 and extends to cover the sidewalls of the first gate electrode layer 460.

[0046] It should also be noted that in other embodiments, according to process requirements, the first gate electrode layer can also be other types of device gate electrode layers such as a polysilicon gate layer.

[0047] The first source / drain doping layer 403 is used as the source or drain of the first transistor. In this embodiment, the first source / drain doping layer 403 includes a first epitaxial layer doped with ions, and the conduction type of the doped ions in the first epitaxial layer is the same as the channel conduction type of the first transistor. That is, when the first transistor is an NMOS transistor, the conduction type of the doped ions in the first epitaxial layer is N-type, and the N-type ions include one or more of As, P, and Sb; when the first transistor is a PMOS transistor, the conduction type of the doped ions in the first epitaxial layer is P-type, and the P-type ions include one or more of B, Ga, and In. Among them, the material of the epitaxial layer in the first epitaxial layer includes Si, SiGe, or SiP. The specific description of the first source / drain doping layer 403 will not be elaborated here.

[0048] In this embodiment, the first transistor structure 400 further includes: a first gate sidewall 405 covering the sidewalls of the first gate electrode layer 460. Specifically, the first gate sidewall 405 covers the first gate dielectric layer 430 located on the sidewalls of the first gate electrode layer 460. The first gate sidewall 405 is used to protect the sidewalls of the first gate electrode layer 460 and the first gate dielectric layer 430, and is also used to define the position of the first source-drain doping layer 403. The first gate sidewall 405 can be a single-layer structure or a stacked structure, and the material of the first gate sidewall 405 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the first gate sidewall 405 is a single-layer structure, and the material of the first gate sidewall 405 is silicon nitride.

[0049] As Figure 5 shown, taking the first transistor as a GAA transistor as an example, the first transistor structure 400 may further include: a first inner sidewall (not labeled), along the normal direction of the surface of the substrate 410 (such as Figure 2 the Z direction shown in

[0050] ), the first inner sidewall is located between adjacent first sub-channel layers 476, or between the first sub-channel layer 476 and the substrate 410, and along the first direction (such as the X direction shown), the first inner sidewall is located between the sidewall of the first gate dielectric layer 430 and the first source-drain doping layer 403.

[0051] In this embodiment, the first transistor structure 400 further includes: a first interlayer dielectric layer 420 located on the substrate 410 at the side of the first gate electrode layer 460 and covering the sidewalls of the first gate electrode layer 460.

[0052] The first interlayer dielectric layer 420 is used to isolate adjacent transistors in the first transistor structure 400. The material of the first interlayer dielectric layer 420 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first interlayer dielectric layer 420 is silicon oxide. Correspondingly, the first gate dielectric layer 430 is located between the bottom of the first gate electrode layer 460 and the substrate 410, and between the sidewalls of the first gate electrode layer 460 and the first interlayer dielectric layer 420.

[0053] In this embodiment, the first transistor structure 400 has a bonding surface 401 on one side of the first gate electrode layer 460. The bonding surface 401 is the front surface of the first transistor structure 400. During the preparation of the semiconductor structure, taking the bonding surface 401 as a process platform, a second transistor structure 600 is prepared above the bonding surface 401.

[0054] A bonding layer 500 is located on the bonding surface 401. During the preparation of the second transistor structure 600, the substrate required to form the second transistor structure 600 is bonded to the bonding surface 401 through the bonding layer 500, so that the first transistor structure 400 and the second transistor structure 600 can be prepared separately. The first transistor structure 400 and the second transistor structure 600 are independent of each other, which enables electrical isolation between the first transistor structure 400 and the second transistor structure 600. Among them, through the bonding layer 500, the bonding strength between the first transistor structure 400 and the second transistor structure 600 is improved, thereby improving the reliability of the semiconductor structure; in addition, during the preparation of the second transistor structure 600, the bonding layer 500 can also protect the first transistor structure 400.

[0055] In this embodiment, the material of the bonding layer 500 includes a dielectric material, so as to play an electrical isolation role between the second transistor structure 600 and the first transistor structure 400, and make the bonding layer 500 compatible with the semiconductor process.

[0056] The material of the bonding layer 500 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the material of the bonding layer 500 includes silicon oxide. By using silicon oxide, bonding can be realized by means of fusion bonding, which is beneficial to improving the bonding efficiency and bonding strength; moreover, it is also beneficial to further improve the electrical isolation effect between the second transistor structure 600 and the first transistor structure 400; in addition, by using silicon oxide, the bonding temperature is relatively low, thereby reducing the influence on the performance of the first transistor in the first transistor structure 400.

[0057] It should be noted that in other embodiments, a conductive layer may also be provided in the bonding layer, so as to realize circuit redistribution through the conductive layer to meet the design requirements.

[0058] It should also be noted that the bonding layer 500 is located on the bonding surface 401, and the bonding layer 500 not only covers the top of the first gate electrode layer 460, but also covers the top of the first interlayer dielectric layer 420.

[0059] The second transistor structure 600 is located on the bonding layer 500. The second transistor structure 600 includes a second transistor, and the second transistor is the top transistor in the CFET structure. Among them, the second transistor includes a second channel layer 520, a second gate dielectric layer 610, a second gate electrode layer 690, and a second source / drain doping layer 601, so as to realize the normal function of the second transistor.

[0060] Therefore, the second transistor in the second transistor structure 600 can be an NMOS transistor or a PMOS transistor, and the channel conduction type of the second transistor is different from that of the first transistor. In this embodiment, the first transistor is an NMOS transistor. Therefore, the second transistor is a PMOS transistor. In other embodiments, when the first transistor is a PMOS transistor, the second transistor is an NMOS transistor correspondingly.

[0061] According to the structural type of the second transistor structure 600, the second transistor structure 600 includes a fin field-effect transistor or a GAA transistor. Specifically, the GAA transistor can be a horizontal nanosheet transistor.

[0062] The second channel layer 520 is used to provide the channel of the second transistor. In this embodiment, taking the second transistor as a GAA transistor as an example, the second channel layer 520 is located on the bonding layer 500 and is spaced from the bonding layer 500. The second channel layer 520 includes one or more second sub-channel layers 526 arranged at intervals. It should be noted that Figure 4 only one second sub-channel layer 526 is schematically shown, but the number of the second sub-channel layers 526 is not limited to one.

[0063] In other embodiments, when the second transistor is a FinFET, the second channel layer is a second fin protruding from the bonding layer.

[0064] It should be noted that in this embodiment, during the process of manufacturing the second transistor structure 600, the substrate bonded to the bonding surface 401 is directly patterned into the second channel layer 520. Therefore, the second transistor structure 600 does not contain an additional substrate (such as a substrate). Correspondingly, when the second channel layer is a second fin protruding from the bonding layer, the second fin is in contact with the bonding layer.

[0065] The material of the second channel layer 520 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials. The material of the second channel layer 520 is determined according to the channel conduction type and performance requirements of the second transistor. As an example, the material of the second channel layer 520 is silicon.

[0066] In this embodiment, the second channel layer 520 extends along the first direction (as shown in the X direction), and the extending direction of the second channel layer 520 is the same as that of the first channel layer 470.

[0067] The second gate electrode layer 690 is used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate electrode layer 690 surrounds and covers the second gate dielectric layer 610 on the second channel layer 520. In other embodiments, when the second channel layer is the second fin protruding from the bonding layer, correspondingly, the second gate electrode layer straddles the second fin and covers the second gate dielectric layer on a part of the top and a part of the sidewall of the second fin.

[0068] In this embodiment, the second gate electrode layer 690 extends along the second direction (as shown in the Y direction), and the extending direction of the second gate electrode layer 690 is the same as that of the first gate electrode layer 460.

[0069] In this embodiment, the second gate electrode layer 690 is a metal gate electrode layer, and the material of the second gate electrode layer 690 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. As an example, the second gate electrode layer 690 includes a second work function layer 670 and a second electrode layer 680 covering the second work function layer 670. For the specific descriptions of the second work function layer 670 and the second electrode layer 680 and their materials, reference can be made to the relevant descriptions of the first work function layer 440 and the first electrode layer 450 respectively above, and details are not repeated here.

[0070] In this embodiment, the second gate dielectric layer 610 is located between the second gate electrode layer 690 and the second channel layer 520, and is also located between the second gate electrode layer 690 and the bonding layer 500.

[0071] The second gate dielectric layer 610 is used to isolate the second gate electrode layer 690 and the second channel layer 520. The material of the second gate dielectric layer 610 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 and La 2 O 3 in one or more. As an example, the second gate dielectric layer 610 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. For the specific description of the second gate dielectric layer 610, reference can be made to the relevant description of the first gate dielectric layer 430 above, and details are not repeated here.

[0072] In this embodiment, the second transistor structure 600 does not contain an additional substrate (for example, a substrate), so the second gate dielectric layer 610 is in contact with the top of the bonding layer 500.

[0073] It should be noted that the second gate dielectric layer 610 and the second gate electrode layer 690 are formed by the process of forming the gate electrode layer after forming the high-k gate dielectric layer. Therefore, the second gate dielectric layer 610 also conformally covers the bottom and sidewalls of the second gate electrode layer 690. That is to say, the second gate dielectric layer 610 is located between the second gate electrode layer 690 and the bonding layer 500 and extends to cover the sidewalls of the second gate electrode layer 690.

[0074] It should also be noted that in other embodiments, according to process requirements, the second gate electrode layer may also be other types of device gate electrode layers such as a polysilicon gate electrode layer.

[0075] The second source / drain doping layer 601 is used as the source or drain of the second transistor. In this embodiment, the second source / drain doping layer 601 includes a second epitaxial layer doped with ions, and the conductivity type of the doped ions in the second epitaxial layer is the same as the channel conductivity type of the second transistor. For the specific description of the second source / drain doping layer 601, reference can be made to the relevant description of the foregoing first source / drain doping layer 403, and details are not described herein again.

[0076] In this embodiment, the second transistor structure 600 further includes: a second gate sidewall 605 covering the sidewalls of the second gate electrode layer 690 and the second gate dielectric layer 610. The second gate sidewall 605 is used to protect the sidewalls of the second gate electrode layer 690 and the second gate dielectric layer 610 and is also used to define the position of the second source / drain doping layer 601. For the specific description of the material of the second gate sidewall 605, reference can be made to the corresponding description of the foregoing first gate sidewall 405, and details are not described herein again.

[0077] As Figure 5 shown, it should be noted that taking the second transistor as a GAA transistor as an example, the second transistor structure 600 may further include: a second inner sidewall (not labeled), along the normal direction of the surface of the substrate 410 (such as Figure 2 the Z direction shown in

[0078] ), located between adjacent second channel layers 520, or located between the second channel layer 520 and the bonding layer 500, and along the first direction (such as the X direction shown), the second inner sidewall is located between the sidewall of the second gate dielectric layer 610 and the second source / drain doping layer 601.

[0079] In this embodiment, the second transistor structure 600 further includes: a second interlayer dielectric layer 560, which is located on the bonding layer 500 and covers the second source / drain doping layer 601 and the second gate electrode layer 690. The second interlayer dielectric layer 560 is used to isolate adjacent transistors in the second transistor structure.

[0080] The material of the second interlayer dielectric layer 560 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second interlayer dielectric layer 560 is silicon oxide.

[0081] With reference to Figure 3 , in this embodiment, the projection of the first channel layer 470 on the substrate 410 is a first pattern 1, the projection of the first gate electrode layer 460 on the substrate 410 is a second pattern 2, the projection of the first source / drain doping layer 403 on the substrate 410 is a third pattern 3, the projection of the second channel layer 520 on the substrate 410 is a fourth pattern 4, and the projection of the second gate electrode layer 690 on the substrate 410 is a fifth pattern 5.

[0082] Specifically, in the second direction, the adjacent first pattern 1 and fourth pattern 4 partially overlap or are arranged side by side. In the first direction, the adjacent second pattern 2 and fifth pattern 5 partially overlap or are arranged side by side, and the adjacent fifth pattern 5 exposes a part of the third pattern 3 between the adjacent second patterns 2.

[0083] Among them, in the second direction, the adjacent first pattern 1 and fourth pattern 4 partially overlap or are arranged side by side, so that it is easy to stagger the second channel layer 520 and the first source / drain doping layer 403 in the horizontal direction; in the first direction, the adjacent second pattern 2 and fifth pattern 5 partially overlap or are arranged side by side, so that it is easy to stagger the second gate electrode layer 690 and the first gate electrode layer 460 in the horizontal direction; moreover, the adjacent fifth pattern 5 exposes a part of the third pattern 3 between the adjacent second patterns 2, so that the second gate electrode layer 690 and the first source / drain doping layer 403 can be staggered in the horizontal direction.

[0084] In summary, the probability that the first gate electrode layer 460 and the first source / drain doping layer 403 in the first transistor structure 400 are completely blocked by the second transistor structure 600 is relatively low, so that the electrical properties of the first gate electrode layer 460 and the first source / drain doping layer 403 can be led out through the regions on the sides of the second gate electrode layer 690 and the second channel layer 520.

[0085] It should be noted that, in the second direction, if the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 is too small, it is easy to cause the second channel layer 520 to block too much of the adjacent first source-drain doping layer 403 located on one side of the second channel layer 520, thereby making it difficult to electrically lead out the first source-drain doping layer 403; if the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 is too large, it is easy to block the first source-drain doping layer 403 located on the other side of the second channel layer 520 in the second direction. Therefore, in this embodiment, the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 is 5 nanometers to 50 nanometers, so as to ensure that at least part of the first source-drain doping layer 403 on both sides of the second channel layer 520 in the second direction can be exposed. Among them, the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 refers to: the distance D1 between the center line of the first graphics 1 and the center line of the fourth graphics 4.

[0086] It should also be noted that, in the first direction, if the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 is too small, it is easy to cause the second gate electrode layer 690 to block the adjacent first gate electrode layer 460 located on one side of the second gate electrode layer 690 too much, so that it is difficult to electrically lead out the first gate electrode layer 460; if the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 is too large, it is easy to cause the second gate electrode layer 690 to block the first source-drain doping layer 403 located on the other side of the second gate electrode layer 690 in the first direction. Therefore, in this embodiment, the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 is 5 nanometers to 50 nanometers, so as to ensure that in the first direction, at least part of the first gate electrode layer 460 on one side of the second gate electrode layer 690 can be exposed, and at least part of the first source-drain doping layer 403 on the other side can be exposed. Among them, the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 refers to: the distance D1 between the center line of the second graphics 2 and the center line of the fifth graphics.

[0087] Specifically, the offset distance D1 between the adjacent first graphics 1 and fourth graphics 4 may be determined according to the first preset pitch P1, and the offset distance D2 between the adjacent second graphics 2 and fifth graphics 5 may be determined according to the second preset pitch P2.

[0088] In this embodiment, in the second direction, the first graphic 1 and the fourth graphic 4 are arranged side by side and separated from each other, and in the first direction, the adjacent second graphic 2 and fifth graphic 5 partially overlap.

[0089] Combined with reference Figure 6, in this embodiment, the semiconductor structure further includes: a bottom source / drain plug 481, a bonding layer 500 penetrating through the side of the second channel layer 520 and the second gate electrode layer 690, the bottom source / drain plug 481 is located on top of the first source / drain doping layer 403 and is electrically connected to the first source / drain doping layer 403; a bottom gate plug 482, a bonding layer 500 penetrating through the side of the second channel layer 520 and the second gate electrode layer 690, the bottom gate plug 482 is located on top of the first gate electrode layer 460 and is electrically connected to the first gate electrode layer 460.

[0090] The bottom source / drain plug 481 is used to realize the electrical connection between the first source / drain doping layer 403 and an external circuit structure, and the bottom gate plug 482 is used to realize the electrical connection between the first gate electrode layer 460 and the external circuit structure.

[0091] Specifically, the bottom source / drain plug 481 penetrates through the second interlayer dielectric layer 560, the bonding layer 500, and the first interlayer dielectric layer 420 on top of the first source / drain doping layer 403, and the bottom gate plug 482 penetrates through the second interlayer dielectric layer 560 and the bonding layer 500 on top of the first gate electrode layer 460.

[0092] In this embodiment, both the bottom source / drain plug 481 and the bottom gate plug 482 are of an integral structure to reduce the process difficulty of forming the bottom source / drain plug 481 and the bottom gate plug 482 (for example, the alignment difficulty in the lithography process). In this embodiment, the material of the bottom source / drain plug 481 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, AL, TiSiN, and TiAlC, and the material of the bottom gate plug 482 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, AL, TiSiN, and TiAlC. The above materials have good electrical conductivity.

[0093] Figures 7 to 23 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention.

[0094] Combined with reference to Figures 7 to 10 , Figure 7 is a perspective view of an embodiment of the first transistor structure of the present invention, Figure 8 is Figure 7 a cross-sectional view along the second direction in Figure 9 is Figure 7 a cross-sectional view along the first direction in Figure 10It is a schematic diagram of the projected patterns of the first channel layer, the first gate electrode layer, and the first source / drain doping layer on the first substrate in an embodiment of the first transistor structure of the present invention. The first transistor structure 100 is formed, including a first substrate 110, a first channel layer 170 located on the first substrate 110, a first gate dielectric layer 130 covering the first channel layer 170, a first gate electrode layer 160 covering the first gate dielectric layer 130, and first source / drain doping layers 103 on the first substrate 110 on both sides of the first gate electrode layer 160. The first source / drain doping layers 103 are in contact with the ends of the first channel layer 170 under the first gate electrode layer 160. The first transistor structure 100 has a bonding surface 101 on one side of the first gate electrode layer 160. Among them, for the convenience of illustration, Figure 7 only the first substrate, the first gate electrode layer, and the first source / drain doping layer are schematically shown.

[0095] As Figure 10 shown, the first channel layer 170 extends along a first direction (as shown by the X direction), the first gate electrode layer 160 extends along a second direction (as shown by the Y direction), and the first direction and the second direction are perpendicular to each other. The projection of the first channel layer 170 on the first substrate 110 is a first pattern 1, the projection of the first gate electrode layer 160 on the first substrate 110 is a second pattern 2, and the projection of the first source / drain doping layer 103 on the first substrate 110 is a third pattern 3.

[0096] The forming method is used to form a CFET structure. The first transistor structure 100 includes a first transistor, and the first transistor is the bottom transistor in the CFET structure. Among them, the first transistor includes a first channel layer 170, a first gate dielectric layer 130, a first gate electrode layer 160, and a first source / drain doping layer 103, so as to realize the normal function of the first transistor. The first transistor in the first transistor structure 100 can be an NMOS transistor or a PMOS transistor. According to the structural type of the first transistor structure 100, the first transistor structure 100 includes a FinFET or a GAA transistor. In this embodiment, the first transistor is taken as an example of a GAA transistor.

[0097] The first substrate 110 is used to provide a process platform for the formation of the semiconductor structure. In this embodiment, the first substrate 110 includes a substrate 111, fins 113 protruding on the substrate 111, and an isolation layer 112 located on the substrate 111. The isolation layer 112 covers the sidewalls of the fins 113.

[0098] In this embodiment, the first channel layer 170 is located on the fin 113 and is spaced apart from the fin 113. The first channel layer 170 includes one or more first sub-channel layers 176 that are spaced apart from each other. It should be noted that only one first sub-channel layer 176 is illustrated in this embodiment, but the number of the first sub-channel layers 176 is not limited to one. In other embodiments, when the first transistor is a FinFET, the first channel layer is a first fin protruding from the substrate.

[0099] With reference to Figure 10 , in this embodiment, in the first transistor structure 100, the number of the first channel layers 170 is multiple, and the multiple first channel layers 170 are arranged in parallel along the second direction (as shown by the Y direction), and the sum of the width W1 of the first channel layer 170 and the spacing S1 between adjacent first channel layers is a first preset pitch P1.

[0100] In this embodiment, the first gate electrode layer 160 surrounds and covers the first gate dielectric layer 130 on the first channel layer 170. In other embodiments, when the first channel layer is a first fin protruding from the substrate, correspondingly, the first gate electrode layer straddles the first fin and covers the first gate dielectric layer on a part of the top and a part of the sidewall of the first fin.

[0101] With reference to Figure 10 , in this embodiment, in the first transistor structure 100, the number of the first gate electrode layers 160 is multiple, and the multiple first gate electrode layers 160 are arranged in parallel along the first direction (as shown by the Figure X direction), and the sum of the width W2 of the first gate electrode layer 160 and the spacing S2 between adjacent first gate electrode layers 460 is a second preset pitch P2.

[0102] As an example, the first gate electrode layer 160 includes a first work function layer 140 and a first electrode layer 150 that covers the first work function layer 140.

[0103] In this embodiment, the first gate dielectric layer 130 is located between the first gate electrode layer 160 and the first channel layer 170. Specifically, the first gate dielectric layer 130 includes a first gate oxide layer and a first high-k gate dielectric layer that covers the first gate oxide layer. It should be noted that the first gate dielectric layer 130 and the first gate electrode layer 160 are formed by a process of forming the high-k gate dielectric layer first and then forming the gate electrode layer. Therefore, the first gate dielectric layer 130 also covers the bottom and sidewalls of the first gate electrode layer 160.

[0104] It should also be noted that in other embodiments, according to process requirements, the first gate electrode layer can also be other types of device gate electrode layers such as a polysilicon gate layer.

[0105] The first source-drain doping layer 103 includes a first epitaxial layer doped with ions, and the conductivity type of the doped ions in the first epitaxial layer is the same as the channel conductivity type of the first transistor.

[0106] With reference to Figure 9 , in this embodiment, the first transistor structure 100 further includes: a first gate sidewall 105 covering the sidewalls of the first gate electrode layer 160. Specifically, the first gate sidewall 105 covers the first gate dielectric layer 130 located on the sidewalls of the first gate electrode layer 160.

[0107] With reference to Figure 9 , the first transistor structure 100 may further include: a first inner sidewall (not labeled), along the normal direction of the surface of the first substrate 110 (such as Figure 7 shown in the Z direction in

[0108] , located between adjacent first sub-channel layers 176, or located between the first sub-channel layer 176 and the first substrate 110, and along the first direction, the first inner sidewall is located between the sidewall of the first gate dielectric layer 130 and the first source-drain doping layer 103.

[0109] For the specific description of the first transistor structure 100, reference may be made to the corresponding description in the foregoing embodiment, which will not be elaborated herein.

[0110] In this embodiment, the first transistor structure 100 has a bonding surface 101. The bonding surface 101 is the front surface of the first transistor structure 100. Subsequently, with the bonding surface 101 as a process platform, a second transistor structure is fabricated above the bonding surface 101, thereby forming a sequential CFET structure.

[0111] Refer to Figures 11 to 12 , Figure 11 is a cross-sectional view along the second direction, Figure 12 is a cross-sectional view along the first direction. The second substrate 205 is bonded to the bonding surface 101 by using a bonding layer 200.

[0112] The second substrate 205 is used to form the second channel layer in the second transistor structure.

[0113] Subsequently, a second transistor structure is formed on the bonding layer 200. The second transistor structure includes a second transistor, and the second transistor is the top transistor in the CFET structure. The second transistor in the second transistor structure can be an NMOS transistor or a PMOS transistor, and the channel conductivity type of the second transistor is different from that of the first transistor.

[0114] In this embodiment, the second substrate 205 is bonded to the bonding surface 101 by a bonding method. That is to say, after the preparation process of the first transistor structure 100 is completed, the subsequent preparation process of the second transistor structure can be independently completed, reducing the process difficulty of the subsequent preparation of the second transistor structure and the influence of the process of preparing the second transistor structure on the first transistor structure 100.

[0115] Through the bonding layer 200, the bonding strength between the first transistor structure 400 and the second substrate 205 is improved, thereby improving the reliability of the semiconductor structure; in addition, during the subsequent preparation process of the second transistor structure, the bonding layer 200 can also protect the first transistor structure 200.

[0116] In this embodiment, the material of the bonding layer 200 includes a dielectric material, so as to achieve electrical isolation between the first transistor structure 200 and the subsequently formed second transistor structure, and make the bonding layer 200 compatible with the semiconductor process. The material of the bonding layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide. In this embodiment, the material of the bonding layer 200 is silicon oxide. By using silicon oxide, the bonding can be realized by a fusion bonding method, which is beneficial to improving the bonding efficiency and the bonding strength; moreover, it is also beneficial to further improve the electrical isolation effect of the bonding layer 200; in addition, by using silicon oxide, the bonding temperature is relatively low, thereby reducing the influence on the performance of the first transistor in the first transistor structure 100.

[0117] It should be noted that in other embodiments, a conductive layer may also be provided in the bonding layer, so as to realize the redistribution of the circuit through the conductive layer to meet the design requirements.

[0118] In this embodiment, the bonding layer 200 is located between the second substrate 205 and the first transistor structure 100, and the bonding layer 200 covers the top of the first gate electrode layer 160 and the top of the first interlayer dielectric layer 120.

[0119] As an example, taking the bonding surface 101 of the first transistor structure 100 as the first bonding surface 101, the second substrate 205 includes a second bonding surface (not labeled). The steps of bonding the second substrate 205 to the bonding surface 101 by using the bonding layer 200 include: forming a first sub-bonding layer (not labeled) on the first bonding surface 101, and forming a second sub-bonding layer (not labeled) on the second bonding surface; arranging the first sub-bonding layer and the second sub-bonding layer opposite to each other and bonding them to bond the second substrate 205 to the bonding surface 101. Correspondingly, the first sub-bonding layer and the second sub-bonding layer constitute the bonding layer 200 of the stacked structure. In this embodiment, the materials of the first sub-bonding layer and the second sub-bonding layer are both silicon oxide, so as to achieve silicon oxide-silicon oxide fusion bonding.

[0120] It should be noted that in other embodiments, the bonding layer may also be formed only on one of the first bonding surface and the second bonding surface, and then the second substrate is bonded to the bonding surface through the bonding layer.

[0121] In this embodiment, a deposition process (for example, chemical vapor deposition process) is adopted to form the bonding layer 200.

[0122] In this embodiment, taking the second transistor formed subsequently as a GAA transistor as an example, in the steps of bonding the second substrate 205 to the bonding surface 101 by using the bonding layer 200, the second substrate 205 includes one or more stacked channel material stacks 206. The channel material stack 206 includes a sacrificial material layer 215 and a channel material layer 225 located on the sacrificial material layer 215, and in the same channel material stack 206, the sacrificial material layer 215 is closer to the bonding layer 200 than the channel material layer 225.

[0123] The sacrificial material layer 21 is used to prepare for the subsequent formation of the sacrificial layer, and the channel material layer 225 is used to prepare for the subsequent formation of the second channel layer. In this embodiment, only one channel material stack 206 is schematically shown. However, the number of the channel material stacks 206 is not limited to one.

[0124] Specifically, taking the second substrate 205 including one channel material stack 206 as an example, the steps of forming the second substrate 205 and the second sub-bonding layer include: providing an initial substrate, the material of the initial substrate being the same as that of the channel material layer 225; forming a sacrificial material layer 215 on the channel material layer 225, the sacrificial material layer 215 and the channel material layer 225 constituting one channel material stack 206; after forming the channel material stack 206, forming a second sub-bonding layer on the sacrificial material layer 215.

[0125] In this embodiment, after bonding the second substrate 205 to the bonding surface 101 by using the bonding layer 200, the initial substrate is thinned until the remaining initial substrate reaches a target thickness, and the target thickness of the remaining initial substrate is equal to the target thickness of the channel material layer 225.

[0126] Correspondingly, when the second substrate 205 includes a plurality of stacked channel material stacks 206, after forming the first channel material stack 206 and before forming the second sub-bonding layer, it further includes: alternately forming a channel material layer 225 and a sacrificial material layer 215 located on the channel material layer 225 on the first channel material stack 206 until the total number of the channel material stacks 206 reaches a target number.

[0127] Therefore, in this embodiment, after the second transistor structure is subsequently formed, the second transistor structure does not contain an additional substrate (e.g., a substrate).

[0128] The material of the channel material layer 225 includes silicon, silicon germanide, germanium, or a III-V group semiconductor material. The material of the channel material layer 225 is determined according to the channel conduction type and performance requirements of the second transistor. As an example, the material of the channel material layer 225 is silicon.

[0129] According to the material of the channel material layer 225, the sacrificial material layer 215 is selected to have an etching selectivity ratio with the channel material layer 225. In this embodiment, since the material of the channel material layer 225 is silicon, the material of the sacrificial material layer 215 is silicon germanide. There is a high etching selectivity ratio between silicon germanide and silicon, which is easy to remove the sacrificial material layer 215 subsequently and reduces the damage to the channel material layer 225 during the process of removing the sacrificial material layer 215.

[0130] It should be noted that in other embodiments, when the subsequently formed second transistor is a FinFET, in the step of bonding the second substrate to the bonding surface by using the bonding layer, the second substrate is a fin material layer. Correspondingly, the initial substrate includes a material layer same as the fin material layer, and after bonding, the initial substrate is thinned until it reaches the target thickness of the fin material layer.

[0131] Combined with reference Figure 13 and Figure 14 , Figure 13 is a cross-sectional view along the second direction (as shown in the Y direction), Figure 14 is a schematic diagram of the projected pattern of the first channel layer, the first gate electrode layer, the first source / drain doping layer, and the second channel layer on the first substrate. The second substrate 205 is patterned (as Figure 5 shown) to form the second channel layer 220.

[0132] The second channel layer 220 is used to provide the channel of the second transistor. As an example, the material of the second channel layer 220 is silicon.

[0133] Specifically, in the step of patterning the second substrate 205, the channel material stack 206 is patterned into one or more stacked channel stacks 227 protruding from the bonding layer 200. The channel stack 227 includes a sacrificial layer 210 and a sub-channel layer 226 located on the sacrificial layer 210. The one or more sub-channel layers 226 constitute the second channel layer 220.

[0134] It should be noted that the first channel layer 170 includes one or more first sub-channel layers 176 arranged at intervals. Therefore, in the step of patterning the second substrate 205, the sub-channel layer 226 in the channel stack 227 is defined as the second sub-channel layer 226, and the one or more second sub-channel layers 226 constitute the second channel layer 220. In other embodiments, when the second substrate is a fin material layer, in the step of patterning the second substrate, the second channel layer is a fin (specifically, the second fin) protruding from the bonding layer.

[0135] In this embodiment, the projection of the second channel layer 220 on the first substrate 110 is the fourth pattern 4. In the second direction (as shown in the Y direction), the adjacent first pattern 1 and fourth pattern 4 partially overlap or are arranged side by side.

[0136] By arranging the adjacent first pattern 1 and fourth pattern 4 partially overlapping or side by side in the second direction (as shown in the Y direction), the fourth pattern 4 can expose at least part of the third pattern 3, so that it is easy to stagger the second channel layer 220 and the first source / drain doping layer 103 in the horizontal direction. Therefore, the probability that the first source / drain doping layer 103 is completely blocked by the second channel layer 220 is relatively low. Furthermore, the electrical property of the first source / drain doping layer 103 can be led out through the region on the side of the second gate electrode layer and the second channel layer 220 in the second transistor structure.

[0137] It should be noted that, in the second direction, if the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 is too small, it is easy to cause the second channel layer 220 to block too much of the adjacent first source-drain doping layer 103 located on one side of the second channel layer 220, thereby making it difficult to subsequently electrically lead out the first source-drain doping layer 103; if the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 is too large, it is easy to block the first source-drain doping layer 103 located on the other side of the second channel layer 220 in the second direction. Therefore, in this embodiment, the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 is 5 nanometers to 50 nanometers, so as to ensure that at least part of the first source-drain doping layer 103 on both sides of the second channel layer 220 in the second direction can be exposed. Among them, the distance D1 between the adjacent first graphics 1 and the fourth graphics 4 refers to: the distance D1 between the center line of the first graphics 1 and the center line of the fourth graphics 4.

[0138] In this embodiment, in the second direction, the first graphic 1 and the fourth graphic 4 are arranged side by side and separated from each other.

[0139] Specifically, the offset distance D1 between adjacent first graphics 1 and fourth graphics 4 is determined according to the first preset pitch P1.

[0140] In this embodiment, after the second substrate 205 is bonded to the bonding surface 101 by using the bonding layer 200, the second substrate 205 is patterned. In the process of patterning the second substrate 205, the structure in the first transistor 100 can be used as an alignment mark, which is conducive to accurately controlling the relative position relationship between the second channel layer 220 and the first channel layer 170. Correspondingly, when the second gate electrode layer is subsequently formed, the structure in the first transistor 100 can also be used as an alignment mark, which is conducive to accurately controlling the relative position relationship between the second gate electrode layer and the first gate electrode layer 160.

[0141] Combined with reference Figures 15 to 21 , forming a second gate dielectric layer 310 covering the second channel layer 220, a second gate electrode layer 390 spanning the second channel layer 220 and covering the second gate dielectric layer 310, and a second source-drain doped layer 201 on the bonding layer 200 located on both sides of the second gate electrode layer 390, the second gate electrode layer 390 extends along the second direction (as shown in the Y direction in the figure), the second source-drain doped layer 201 is in contact with the end of the second channel layer 220 located below the second gate electrode layer 390, and the second gate electrode layer 390, the second gate dielectric layer 310, the second source-drain doped layer 201 and the second channel layer 220 are used to form a second transistor structure 700.

[0142] Among them, the projection of the second gate electrode layer 390 on the first substrate 110 is a fifth figure 5, and in the first direction, adjacent second figures 2 and fifth figures 5 are partially overlapped or arranged in parallel, and adjacent fifth figures 5 expose part of the third figure 3 between adjacent second figures 2.

[0143] By partially overlapping or arranging the adjacent second graphics 2 and fifth graphics 5 in the first direction, the fifth graphics 5 can expose at least a portion of the second graphics 2, thereby facilitating the second gate electrode layer 390 and the first gate electrode layer 160 to be staggered in the horizontal direction. Therefore, the probability of the first gate electrode layer 160 being completely blocked by the second gate electrode layer 390 is low, and the electrical properties of the first gate electrode layer 160 can be brought out through the area on the sides of the second gate electrode layer 390 and the second channel layer 220 in the second transistor structure 700.

[0144] Moreover, the adjacent fifth figure 5 exposes part of the third figure 3 between the adjacent second figures 2, so that the second gate electrode layer 690 and the first source-drain doped layer 403 can be staggered in the horizontal direction. Therefore, the probability of the first source-drain doped layer 103 being completely blocked by the second gate electrode layer 390 is low. In other words, the probability of the first source-drain doped layer 103 being completely blocked by the second transistor structure 700 is low, so that the electrical properties of the first gate electrode layer 160 can be brought out through the area on the sides of the second gate electrode layer 390 and the second channel layer 220 in the second transistor structure 700.

[0145] It should be noted that, in the first direction, if the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 is too small, it is easy to cause the second gate electrode layer 390 to block the first gate electrode layer 160 located on one side of the second gate electrode layer 390 too much, so that it is difficult to lead out the electrical properties of the first gate electrode layer 160; if the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 is too large, it is easy to cause the second gate electrode layer 390 to block the first source-drain doping layer 103 located on the other side of the second gate electrode layer 390 in the first direction. Therefore, in this embodiment, the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 is 5 nanometers to 50 nanometers, so as to ensure that in the first direction, at least part of the first gate electrode layer 160 on one side of the second gate electrode layer 390 can be exposed, and at least part of the first source-drain doping layer 103 on the other side can be exposed. Among them, the distance D2 between the adjacent second graphics 2 and the fifth graphics 5 refers to: the distance D2 between the center line of the second graphics 2 and the center line of the fifth graphics 5.

[0146] In this embodiment, in the first direction, the adjacent second graphics 2 and fifth graphics 5 partially overlap.

[0147] Specifically, the offset distance D2 between the adjacent second graphics 2 and fifth graphics 5 is determined according to the second preset pitch P2.

[0148] In this embodiment, the second gate dielectric layer 310 and the second gate electrode layer 390 are formed by a process of forming a high k gate dielectric layer and then forming a gate electrode layer (high k last metal gatelast). Therefore, before forming the second gate dielectric layer 310, the second gate electrode layer 390 and the second source-drain doped layer 201, a step of forming a dummy gate structure is also included.

[0149] Accordingly, before subsequently forming the bottom source and drain plugs and the bottom gate plugs, the formation method further includes: forming a second interlayer dielectric layer 260 on the bonding layer 200. In this embodiment, the second interlayer dielectric layer 260 covers the top of the second source and drain doped layer 201 and the sidewalls of the second gate electrode layer 390.

[0150] The steps of forming the second transistor structure 700 are described in detail below with reference to the accompanying drawings.

[0151] Combined with reference Figures 15 to 17 , Figure 15 is a cross-sectional view along the second direction (as shown in the Y direction), Figure 16 is a cross-sectional view along a first direction (as shown in the X direction), Figure 17 It is a schematic diagram of the projection patterns of the first channel layer, the first gate electrode layer, the first source-drain doping layer, the second channel layer and the dummy gate structure on the first substrate, a dummy gate structure 250 extending along the second direction is formed on the bonding layer 200, the dummy gate structure 250 spans the second channel layer 220 and covers part of the top and part of the sidewall of the second channel layer 220, and the projection of the dummy gate structure 250 on the first substrate is a sixth pattern.

[0152] The dummy gate structure 250 is used to occupy a space for the subsequent formation of the second gate electrode layer 390. Therefore, in this embodiment, in the first direction, adjacent second graphics 2 and sixth graphics 6 partially overlap or are arranged in parallel, and adjacent sixth graphics 6 expose part of the third graphics 3 between adjacent second graphics 2.

[0153] Correspondingly, in this embodiment, the distance D3 between the adjacent second graphics 2 and the sixth graphics 6 is 5 nanometers to 50 nanometers. The distance D3 between the adjacent second graphics 2 and the sixth graphics 6 refers to: the distance D3 between the center line of the second graphics 2 and the center line of the sixth graphics 6.

[0154] In this embodiment, in the first direction, the adjacent second graphics 2 and sixth graphics 6 partially overlap.

[0155] Specifically, the dummy gate structure 250 straddles the channel stack 227 and covers a part of the top and a part of the sidewalls of the channel stack 227.

[0156] In this embodiment, the dummy gate structure 250 includes a dummy gate oxide layer 230 covering the channel stack 227 and a dummy gate layer 240 covering the dummy gate oxide layer 230. As an example, the material of the dummy gate oxide layer 230 is silicon oxide or silicon oxynitride, and the material of the dummy gate layer 240 is polysilicon, amorphous silicon, or amorphous carbon.

[0157] In other embodiments, when the second channel layer is a second fin protruding from the bonding layer, correspondingly, the dummy gate structure straddles the second fin and covers a part of the top and a part of the sidewalls of the second fin.

[0158] Continue to refer to Figures 15 to 17 , after forming the dummy gate structure 250, it further includes: forming a second gate sidewall 255 on the sidewalls of the dummy gate structure 250; after forming the second gate sidewall 255, forming a second source / drain doping layer 201 in the second channel layers 220 on both sides of the dummy gate structure 250, and the second source / drain doping layer 201 is in contact with the ends of the second channel layers 220 located below the dummy gate structure 250.

[0159] The second source / drain doping layer 201 is used as the source or drain of the second transistor. In this embodiment, the second source / drain doping layer 201 includes a second epitaxial layer doped with ions, and the conductive type of the doped ions in the second epitaxial layer is the same as the channel conductive type of the second transistor. Specifically, after removing the second channel layers 220 on both sides of the dummy gate structure 250, the second source / drain doping layer 201 is formed by an epitaxial process.

[0160] It should be noted that after removing the second channel layers 220 on both sides of the dummy gate structure 250 and before forming the second source / drain doping layer 201, it further includes: laterally etching a part of the width of the exposed sacrificial layer 210 to form a trench surrounded by adjacent second channel layers 220 and the sacrificial layer 210, or a trench surrounded by the second channel layer 220, the bonding layer 200, and the sacrificial layer 210; forming a second inner sidewall (not labeled) in the trench.

[0161] For the specific descriptions of the second gate sidewall 255, the second source / drain doping layer 201, and the second inner sidewall, reference can be made to the corresponding descriptions in the foregoing embodiments, and details are not described herein again.

[0162] Continue to refer to Figures 15 to 17 , after forming the second source / drain doping layer 201, a second interlayer dielectric layer 260 is formed on the bonding layer 200 on the side of the dummy gate structure 250, and the second interlayer dielectric layer 260 covers the sidewalls of the dummy gate structure 250 and exposes the top of the dummy gate structure 250.

[0163] The second interlayer dielectric layer 260 is used to isolate adjacent transistors in the subsequent second transistor structure, and is also used to provide a process basis for forming the subsequent second gate dielectric layer 310 and the second gate electrode layer 390. The material of the second interlayer dielectric layer 260 is an insulating material, and the insulating material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second interlayer dielectric layer 260 is silicon oxide.

[0164] Reference Figure 18 , Figure 18 is a cross-sectional view along the second direction (as shown by the Y direction in Figure 17 ), after removing the dummy gate structure 250 (as shown in Figure 15 ), a gate opening 270 is formed in the second interlayer dielectric layer 260.

[0165] The gate opening 270 is used to provide a spatial position for forming the subsequent second gate dielectric layer and the second gate electrode layer. In this embodiment, after forming the gate opening 270, it further includes: removing the sacrificial layer 210 exposed by the gate opening 270 to form a through groove 280 communicating with the gate opening 270. The through groove 280 is also used to provide a spatial position for forming the subsequent second gate dielectric layer and the second gate electrode layer.

[0166] Combined with reference Figures 19 to 21 , Figure 19 is a perspective view of an embodiment of the first transistor structure and the second transistor structure of the present invention, Figure 20 is a schematic diagram of the projection pattern of the first channel layer, the first gate electrode layer, the first source / drain doping layer, the second channel layer, and the second gate electrode layer on the first substrate, Figure 21 is a cross-sectional view along the second direction, forming a second gate dielectric layer 310 covering the bottom and sidewalls of the gate opening 270, and the second gate dielectric layer 310 also covers the top and sidewalls of the second channel layer 220 in the gate opening 270; forming a second gate electrode layer 390 in the gate opening 270, wherein the second gate electrode layer 390, the second gate dielectric layer 310, the second source / drain doping layer 201, and the second channel layer 220 are used to constitute the second transistor structure 700.

[0167] Wherein, for the convenience of illustration, Figure 19 only the first substrate, the first gate electrode layer, the first source / drain doping layer, the bonding layer, the second gate electrode layer, and the second source / drain doping layer are schematically shown in

[0168] In this embodiment, the second gate dielectric layer 310 is used to isolate the subsequently formed second gate electrode layer 390 and the second channel layer 220. In this embodiment, the second gate dielectric layer 310 includes a second gate oxide layer and a second high-k gate dielectric layer covering the second gate oxide layer. Among them, the second gate oxide layer conformally covers each surface of the second channel layer 220; the second high-k gate dielectric layer conformally covers the gate oxide layer and also conformally covers the bottom and sidewalls of the gate opening 270. For the specific description of the second gate dielectric layer 310, reference can be made to the relevant description of the first gate dielectric layer 130 above, and details will not be repeated here.

[0169] It should be noted that in the step of forming the second gate dielectric layer 310, the second gate dielectric layer 310 also covers the top of the second interlayer dielectric layer 260.

[0170] The second gate electrode layer 390 is used to control the opening or closing of the channel of the second transistor. In this embodiment, the second gate electrode layer 390 surrounds and covers the second gate dielectric layer 310 on the second channel layer 220. In other embodiments, when the second channel layer is a second fin, correspondingly, the second gate electrode layer straddles the second fin and covers a part of the top and a part of the sidewall second gate dielectric layer of the second fin. In this embodiment, the second gate electrode layer 390 is a metal gate electrode layer, and the material of the second gate electrode layer 390 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. Specifically, the second gate electrode layer 390 includes a second work function layer 370 and a second electrode layer 380 covering the second work function layer 370. For the specific description of the second work function layer 370 and the second electrode layer 380, reference can be made to the relevant descriptions of the first work function layer 140 and the first electrode layer 150 above, and details will not be repeated here.

[0171] Specifically, the second gate electrode layer 390 is formed in the gate opening 270 through a deposition step and a planarization step performed in sequence. Among them, during the planarization process, the second gate dielectric layer 310 located on the top of the second interlayer dielectric layer 260 is also removed.

[0172] Combined with reference to Figures 22 to 23 , Figure 22 is a perspective view, where 23 is Figure 22A cross-sectional view along a first direction and at a side position of the second gate layer. The forming method further includes: forming a bottom source / drain plug 181 that penetrates through the side of the second channel layer 220 and the second gate electrode layer 390 and is located on top of the first source / drain doping layer 103 and is electrically connected to the first source / drain doping layer 103; forming a bottom gate plug 182 that penetrates through the side of the second channel layer 220 and the second gate electrode layer 390 and is located on top of the first gate electrode layer 160 and is electrically connected to the first gate electrode layer 160.

[0173] For the convenience of illustration, Figure 22 only the first substrate, the first gate electrode layer, the first source / drain doping layer, the bonding layer, the second gate electrode layer, the second source / drain doping layer, the bottom source / drain plug, and the top source / drain plug are schematically shown. The bottom source / drain plug 181 is used to electrically connect the first source / drain doping layer 103 to an external circuit structure, and the bottom gate plug 182 is used to electrically connect the first gate electrode layer 160 to an external circuit structure.

[0174] In this embodiment, the step of forming the bottom source / drain plug 181 includes: forming a first contact hole that penetrates through the top of the first source / drain doping layer 103, the bonding layer 200, and the first interlayer dielectric layer 120, and the first contact hole exposes the first source / drain doping layer 103; filling a conductive material in the first contact hole to form the bottom source / drain plug 181 located in the first contact hole.

[0175] In this embodiment, the step of forming the bottom gate plug 182 includes: forming a second contact hole that penetrates through the top of the first gate electrode layer 160 and the bonding layer 200, and the second contact hole exposes the first gate electrode layer 160; filling a conductive material in the second contact hole to form the bottom gate plug 182 located in the second contact hole.

[0176] In this embodiment, in the same step, a first contact hole that penetrates through the top of the first source / drain doping layer 103, the bonding layer 200, and the first interlayer dielectric layer 120 is formed. Therefore, during the formation of the bottom source / drain plug 181, only one photolithography process is required, and the bottom source / drain plug 181 is an integral structure, thereby reducing the process difficulty of forming the bottom source / drain plug 181.

[0177] Similarly, in the same step, a second contact hole that penetrates through the top of the first gate electrode layer 160 and the bonding layer 200 is formed. Therefore, during the formation of the bottom gate plug 182, only one photolithography process is required, and the bottom gate plug 182 is an integral structure, thereby reducing the process difficulty (such as the alignment difficulty in the photolithography process) of forming the bottom gate plug 182.

[0178] Specifically, a deposition process is used to fill the conductive material, and the conductive material is planarized to form a bottom source / drain plug located in the first contact hole and a bottom gate plug 182 located in the second contact hole. As an example, the bottom source / drain plug 181 and the bottom gate plug 182 can be formed in the same step.

[0179] In this embodiment, the material of the bottom source / drain plug 181 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, AL, TiSiN, and TiAlC, and the material of the bottom gate plug 182 includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, AL, TiSiN, and TiAlC. The above materials have good electrical conductivity.

[0180] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, comprising: A first transistor structure, including a substrate, a first channel layer on the substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and first source / drain doping layers on the substrate on both sides of the first gate electrode layer, the first source / drain doping layers being in contact with the ends of the first channel layer under the first gate electrode layer, the first channel layer extending in a first direction, the first gate electrode layer extending in a second direction, and the first direction and the second direction being perpendicular to each other, the first transistor structure having a bonding surface on one side of the first gate electrode layer; A bonding layer, located on the bonding surface of the first transistor structure; A second transistor structure, located on the bonding layer, the second transistor structure including a second channel layer, a second gate dielectric layer covering the second channel layer, a second gate electrode layer covering the second gate dielectric layer, and second source / drain doping layers on the bonding layer on both sides of the second gate electrode layer, the second source / drain doping layers being in contact with the ends of the second channel layer under the second gate electrode layer, the second channel layer extending in the first direction, the second gate electrode layer extending in the second direction; wherein, the projection of the first channel layer on the substrate is a first pattern, the projection of the first gate electrode layer on the substrate is a second pattern, the projection of the first source / drain doping layer on the substrate is a third pattern, the projection of the second channel layer on the substrate is a fourth pattern, the projection of the second gate electrode layer on the substrate is a fifth pattern, in the second direction, adjacent the first pattern and the fourth pattern partially overlap or are arranged side by side, in the first direction, adjacent the second pattern and the fifth pattern partially overlap or are arranged side by side, and adjacent the fifth pattern exposes a part of the third pattern between adjacent the second patterns.

2. The semiconductor structure according to claim 1, characterized in that, in the second direction, the distance between adjacent the first pattern and the fourth pattern being staggered is 5 nanometers to 50 nanometers.

3. The semiconductor structure according to claim 1, characterized in that, in the first direction, the distance between adjacent the second pattern and the fifth pattern being staggered is 5 nanometers to 50 nanometers.

4. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further includes: a bottom source / drain plug penetrating through the side portions of the second channel layer and the second gate electrode layer of the bonding layer, the bottom source / drain plug being located on the top of the first source / drain doping layer and electrically connected to the first source / drain doping layer; a bottom gate plug penetrating through the side portions of the second channel layer and the second gate electrode layer of the bonding layer, the bottom gate plug being located on the top of the first gate electrode layer and electrically connected to the first gate electrode layer.

5. The semiconductor structure according to claim 4, characterized in that, the first transistor structure further includes: a first interlayer dielectric layer, located on the substrate on the side of the first gate electrode layer and covering the sidewalls of the first gate electrode layer; The second transistor structure further includes: a second interlayer dielectric layer, located on the bonding layer and covering the second source / drain doping layer and the second gate electrode layer; The bottom source / drain plug penetrates through the second interlayer dielectric layer, the bonding layer, and the first interlayer dielectric layer on top of the first source / drain doping layer; The bottom gate plug penetrates through the second interlayer dielectric layer and the bonding layer on top of the first gate electrode layer.

6. The semiconductor structure according to claim 4, wherein, the material of the bottom source / drain plug includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, AL, TiSiN, and TiAlC, and the material of the bottom gate plug includes one or more of W, Co, Ru, TiN, TaN, Ta, Ti, TiAl, AL, TiSiN, and TiAlC.

7. The semiconductor structure according to claim 1, wherein, the first channel layer is a first fin protruding from the substrate; the first gate electrode layer straddles the first fin and covers the first gate dielectric layer on a part of the top and a part of the sidewalls of the first fin; or, the first channel layer is located on the substrate and is spaced apart from the substrate, and the first channel layer includes one or more spaced-apart first sub-channel layers; the first gate electrode layer surrounds and covers the first gate dielectric layer on the first channel layer.

8. The semiconductor structure according to claim 1, wherein, the second channel layer is a second fin protruding from the bonding layer; the second gate electrode layer straddles the second fin and covers the second gate dielectric layer on a part of the top and a part of the sidewalls of the second fin; or, the second channel layer is located on the bonding layer and is spaced apart from the bonding layer, and the second channel layer includes one or more spaced-apart second sub-channel layers; the second gate electrode layer surrounds and covers the second gate dielectric layer on the second channel layer.

9. The semiconductor structure according to claim 1, wherein, the first transistor structure includes an NMOS transistor, and the second transistor structure includes a PMOS transistor; or, the first transistor structure includes a PMOS transistor, and the second transistor structure includes an NMOS transistor.

10. The semiconductor structure according to claim 1, wherein, the material of the first channel layer includes silicon, silicon germanide, germanium, or a III-V group semiconductor material; the material of the second channel layer includes silicon, silicon germanide, germanium, or a III-V group semiconductor material.

11. The semiconductor structure according to claim 1, wherein, the material of the bonding layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon oxide.

12. The semiconductor structure according to claim 1, wherein, The material of the first gate dielectric layer includes HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 or one or more of them; the material of the second gate dielectric layer includes HfO 2 , ZrO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al 2 O 3 , SiO 2 and La 2 O 3 or one or more of them.

13. The semiconductor structure according to claim 1, wherein, The material of the first gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC; the material of the second gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

14. A method for forming a semiconductor structure, characterized in that, comprising: forming a first transistor structure, the first transistor structure including a first substrate, a first channel layer located on the first substrate, a first gate dielectric layer covering the first channel layer, a first gate electrode layer covering the first gate dielectric layer, and first source / drain doping layers on the first substrate on both sides of the first gate electrode layer, the first source / drain doping layers being in contact with the ends of the first channel layer under the first gate electrode layer, the first transistor structure having a bonding surface on one side of the first gate electrode layer, wherein the first channel layer extends in a first direction, the first gate electrode layer extends in a second direction, and the first direction and the second direction are perpendicular to each other, the projection of the first channel layer on the first substrate is a first pattern, the projection of the first gate electrode layer on the first substrate is a second pattern, and the projection of the first source / drain doping layers on the first substrate is a third pattern; bonding a second substrate to the bonding surface using a bonding layer; patterning the second substrate to form a second channel layer extending in the first direction, the projection of the second channel layer on the first substrate being a fourth pattern, and in the second direction, the adjacent first pattern and the fourth pattern partially overlap or are arranged side by side; forming a second gate dielectric layer covering the second channel layer, a second gate electrode layer spanning the second channel layer and covering the second gate dielectric layer, and second source / drain doping layers on the bonding layer on both sides of the second gate electrode layer, the second gate electrode layer extending in the second direction, the second source / drain doping layers being in contact with the ends of the second channel layer under the second gate electrode layer, the second gate electrode layer, the second gate dielectric layer, the second source / drain doping layers, and the second channel layer being used to form a second transistor structure, wherein the projection of the second gate electrode layer on the first substrate is a fifth pattern, in the first direction, the adjacent second pattern and the fifth pattern partially overlap or are arranged side by side, and the adjacent fifth pattern exposes a part of the third pattern between the adjacent second patterns.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, the forming method further includes: forming a bottom source / drain plug penetrating through the side portions of the second channel layer and the second gate electrode layer and the bonding layer, the bottom source / drain plug being located on top of the first source / drain doping layer and being electrically connected to the first source / drain doping layer; forming a bottom gate plug penetrating through the side portions of the second channel layer and the second gate electrode layer and the bonding layer, the bottom gate plug being located on top of the first gate electrode layer and being electrically connected to the first gate electrode layer.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, In the step of forming the first transistor structure, the first transistor structure further includes a first interlayer dielectric layer, which is located on the first substrate at the side of the first gate electrode layer and covers the sidewalls of the first gate electrode layer; Before forming the bottom source / drain plug and the bottom gate plug, the forming method further includes: forming a second interlayer dielectric layer on the bonding layer, wherein the second interlayer dielectric layer covers the top of the second source / drain doping layer and the sidewalls of the second gate electrode layer; The step of forming the bottom source / drain plug includes: forming a first contact hole penetrating through the second interlayer dielectric layer, the bonding layer and the first interlayer dielectric layer on the top of the first source / drain doping layer, the first contact hole exposing the first source / drain doping layer; filling a conductive material in the first contact hole to form a bottom source / drain plug located in the first contact hole; The step of forming the bottom gate plug includes: forming a second contact hole penetrating through the second interlayer dielectric layer and the bonding layer on the top of the first gate electrode layer, the second contact hole exposing the first gate electrode layer; filling a conductive material in the second contact hole to form a bottom gate plug located in the second contact hole.

17. The method for forming a semiconductor structure according to claim 14, wherein, Before forming the second gate dielectric layer, the second gate electrode layer and the second source / drain doping layer, the forming method further includes: forming a dummy gate structure extending along the second direction on the bonding layer, the dummy gate structure straddling the second channel layer and covering a part of the top and a part of the sidewalls of the second channel layer, the projection of the dummy gate structure on the first substrate being a sixth pattern, in the first direction, the adjacent second pattern and the sixth pattern partially overlap or are arranged side by side, and the adjacent sixth pattern exposes a part of the third pattern between the adjacent second patterns; The step of forming the second source / drain doping layer includes: forming second source / drain doping layers in the second channel layer on both sides of the dummy gate structure, the second source / drain doping layers being in contact with the ends of the second channel layer located under the dummy gate structure; After forming the second source / drain doping layer, the forming method further includes: forming a second interlayer dielectric layer on the bonding layer at the side of the dummy gate structure, the top interlayer dielectric layer covering the sidewalls of the dummy gate structure and exposing the top of the dummy gate structure; The step of forming the second gate dielectric layer and the second gate electrode layer includes: removing the dummy gate structure, forming a gate opening in the top interlayer dielectric layer; forming a second gate dielectric layer covering the bottom and the sidewalls of the gate opening, the second gate dielectric layer further covering the top and the sidewalls of the second channel layer in the gate opening; forming a second gate electrode layer in the gate opening.

18. The method for forming a semiconductor structure according to claim 17, wherein, In the step of bonding the second substrate to the bonding surface by using the bonding layer, the second substrate is a fin material layer; In the step of patterning the second substrate, the second channel layer is a fin protruding from the bonding layer; In the step of forming the pseudo-gate structure, the pseudo-gate structure straddles the fin and covers a part of the top and a part of the sidewall of the fin; Or, In the step of bonding the second substrate to the bonding surface by using a bonding layer, the second substrate includes one or more stacked channel material stacks, the channel material stack includes a sacrificial material layer and a channel material layer located on the sacrificial material layer, and in the same channel material stack, the sacrificial material layer is closer to the bonding layer than the channel material layer; In the step of patterning the second substrate, the channel material stack is patterned into one or more stacked channel stacks protruding from the bonding layer, the channel stack includes a sacrificial layer and a sub-channel layer located on the sacrificial layer, and the one or more sub-channel layers constitute the second channel layer; In the step of forming the pseudo-gate structure, the pseudo-gate structure straddles the channel stack and covers a part of the top and a part of the sidewall of the channel stack; After forming the gate opening and before forming the second gate dielectric layer, it further includes: removing the sacrificial layer exposed by the gate opening; In the step of forming the second gate electrode layer, the second gate electrode layer surrounds and covers the second gate dielectric layer on the second channel layer.

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