Semiconductor structure and method for forming the same, and memory

Abstract

A semiconductor structure and a method for forming the same, as well as a memory, the semiconductor structure comprising: a substrate, including a plurality of discrete cell array regions, for forming memory cells; a plurality of isolation structures extending in the column direction and arranged in the row direction, located in the substrate, the top surface of the isolation structure in the cell array region being lower than the top surface of the substrate; a first drain doping layer, located on the side wall of the substrate exposed along the second side of the row direction of the isolation structure; a second drain doping layer, located on the side wall of the substrate exposed along the first side of the row direction of the isolation structure; a floating gate, located on a portion of the substrate between adjacent isolation structures in the cell array region, and the floating gates are arranged discretely and spaced apart in the column direction; a source region in the column direction, located in the substrate between adjacent floating gates in the cell array region. The embodiment of the present invention allows the formation process of the first drain doping layer and the second drain doping layer to be free from the limitation of the ion implantation process, improves the formation quality of the first drain doping layer and the second drain doping layer, and optimizes the performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] With the development of semiconductor process technology, flash memory with faster access speed has been developed in storage devices. Flash memory is also called flash memory. The main feature of flash memory is that it can keep the stored information for a long time without power supply, and it has the advantages of high integration, fast access speed, easy erasure and read and write, so it has become the mainstream memory of non-volatile memory (NVM).

[0003] According to the different structures, flash memory is divided into NOR Flash Memory and NAND Flash Memory. NOR flash uses memory random read technology. Each unit is connected in parallel, and the storage unit is uniformly addressed (with independent address lines), so any word can be accessed randomly. In the NOR flash array, when a word line is selected, the M NVM units originally connected to the word are all activated. On the other hand, the other NVM units connected to the unselected word lines are electrically separated from the M bit lines. Through the connected M bit lines, the current changes of the drains of the M selected NVM units can be detected. Because the bias and signal in the NOR flash array are directly applied to the electrodes of the selected NVM cells, generally speaking, the NOR flash array has a faster read access speed and a lower operating voltage than the NAND flash array. Also, because the NOR flash array has dedicated address pins for addressing, it is easier to connect to other chips and supports local execution.

[0004] A NOR flash array is currently proposed, which includes a plurality of NOR cells, wherein the paired drains of the plurality of NOR cells form a plurality of diffused sub-bit lines, and the diffused sub-bit lines are separated by trench field isolation regions. The diffused sub-bit lines are twisted along the extension direction of the trench field isolation regions in a manner less than or equal to a column pitch, so that the diffused sub-bit lines can connect the diffusion lines of their sub-feature size (whose feature size is less than the minimum feature size F) to a plurality of full feature size diffusion regions, and a plurality of full feature size contacts can be set on the full feature size diffusion regions. In this NOR flash array, the area of ​​the NVM cell can be only 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0005] However, NOR memory still has the problem of poor performance. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, and a memory, so as to optimize the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a plurality of discrete cell array areas, for forming storage cells; a plurality of isolation structures extending along the column direction and arranged along the row direction, located in the substrate, and the top surface of the isolation structure in the cell array area is lower than the top surface of the substrate; a first drain doping layer, located on the side wall of the substrate exposed along the second side of the row direction of the isolation structure; a second drain doping layer, located on the side wall of the substrate exposed along the first side of the row direction of the isolation structure; a floating gate, located on a portion of the substrate between adjacent isolation structures in the cell array area, and the floating gates are arranged discretely and spaced apart along the column direction; and a source region along the column direction, located in the substrate between adjacent floating gates in the cell array area.

[0008] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a plurality of discrete cell array areas, for forming storage cells; forming a plurality of grooves penetrating a portion of the thickness of the substrate, the grooves extending in the column direction and arranged in the row direction; forming an isolation structure in the groove, the top surface of the isolation structure in the cell array area being lower than the top surface of the substrate; using an epitaxial process, forming a first drain doping layer on the side wall of the substrate exposed along the second side of the isolation structure in the row direction, and forming a second drain doping layer on the side wall of the substrate exposed along the first side of the isolation structure in the row direction; forming a floating gate material layer on the substrate between the isolation structures; forming a source region opening along the column direction in the floating gate material layer, the source region opening penetrating the cell array area along the column direction, and a portion of the width of the floating gate material layer is retained on both sides of the source region opening; and forming a source region in the substrate at the bottom of the source region opening.

[0009] Correspondingly, an embodiment of the present invention further provides a memory, including: the semiconductor structure provided by an embodiment of the present invention.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of forming an isolation structure, the top surface of the isolation structure in the cell array region is lower than the top surface of the substrate, and then an epitaxial process is used to form a first drain doping layer on the substrate sidewall exposed along the second side of the isolation structure in the row direction, and a second drain doping layer is formed on the substrate sidewall exposed along the first side of the isolation structure in the row direction. Compared with the solution of forming a drain region by ion implantation, the epitaxial process used in the embodiment of the present invention is conducive to avoiding the formation of the first drain doping layer and the second drain doping layer being restricted by the ion implantation process (for example, the restriction of the ion implantation angle), and the epitaxial process enables the first drain doping layer and the second drain doping layer to be selectively formed. The first drain-doped layer and the second drain-doped layer are formed on the exposed side wall of the isolation structure, thereby achieving self-alignment of the formation positions of the first drain-doped layer and the second drain-doped layer, and improving the position accuracy of the first drain-doped layer and the second drain-doped layer; moreover, by adopting the epitaxial process to form the first drain-doped layer and the second drain-doped layer in the same step, it is beneficial to improve the ion doping uniformity and the film growth uniformity of the first drain-doped layer and the second drain-doped layer, and correspondingly improve the performance consistency between storage cells; in addition, during the epitaxial process, the doped atoms can be grown in situ in the lattice without the need for an additional activation step, which is beneficial to reducing the resistance of the first drain-doped layer and the second drain-doped layer; in summary, the embodiments of the present invention are beneficial to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0013] Figure 3 to Figure 4 yes Figure 1 to Figure 2 The schematic diagram of the structure corresponding to the steps of forming the semiconductor structure shown;

[0014] Figure 5 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figures 6 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] As can be seen from the background technology, the current NOR memory still has the problem of poor performance. 2 Taking a NOR memory as an example, the reasons why the NOR memory still has poor performance problems are analyzed in combination with a semiconductor structure and a formation method thereof.

[0017] refer to Figure 1 to Figure 2 , Figure 1 is a top view of the cell array area. Figure 2 yes Figure 1The cross-sectional view along the a-a1 cut line shows a schematic structural diagram of a semiconductor structure.

[0018] The semiconductor structure comprises: a substrate 1, comprising a plurality of discrete cell array regions 1c for forming storage cells (Cell); a plurality of rows (such as Figure 1 y direction) and along the row direction (as shown in Figure 1 The isolation structure is arranged in the substrate 1 (as shown in the x direction), and is located in the substrate 1; the isolation structure includes a main extension portion 3 located in the cell array area 1c, and the main extension portion 3 extends in the column direction; a plurality of gate structures 4 extending in the row direction and arranged in the column direction are located on the substrate 1 in the cell array area, and the gate structure includes: floating gates 2 located on the substrate 1 on both sides of the isolation structure, and the floating gates 2 in each of the gate structures 4 are arranged at intervals along the row direction; a control gate 5 covers the floating gates 2 along the row direction, and the substrate 1 and the isolation structure between the floating gates 2; a source doping region 7 along the column direction, and is located in the substrate 1 between adjacent floating gates 2 in the cell array area 1c; a first drain doping region 81, located in the substrate 1 on the second side wall of the main extension portion 3 along the row direction; a second drain doping region 82, located in the substrate 1 on the first side wall of the main extension portion 3 along the row direction.

[0019] For the convenience of illustration and description, the gate structure is only illustrated in a cross-sectional view.

[0020] In the above semiconductor structure, Figure 1 and Figure 2 As shown, the source doping region (Common source) 7 of the memory cell is located in the active area (Active Area, AA) between two adjacent floating gates 2, and the first drain doping region 81 and the second drain doping region 82 are arranged along the column direction (such as Figure 1 The main extension portion 3 extends in the y direction as shown in the figure, and is used as a drain sub-bitline, which is respectively located in the limited active areas on both sides of the main extension portion 3 and at the bottom of the floating gate 2.

[0021] Combined with reference Figure 3 and Figure 4 , showing Figure 1 and Figure 2 A schematic cross-sectional view corresponding to the formation process of the semiconductor structure. Figure 3 is a top view of the cell array area. Figure 4 for Figure 3 Section view along the secant line a-a1.

[0022] like Figure 3 and Figure 4As shown, a substrate 1 and a floating gate material layer 6 located on the substrate 1 are provided, and a plurality of isolation structures extending along the column direction and arranged along the row direction are formed in the substrate, and the top surface of the isolation structure is flush with the top surface of the substrate 1; the isolation structure includes a main extension portion 3 located in the unit array area 1c, and the main extension portion 3 extends along the column direction.

[0023] like Figure 3 and Figure 4 As shown, a first ion implantation 61 is performed on the substrate 1 along the second side wall of the main extension portion 3 to form the first drain doping region 81 .

[0024] like Figure 3 and Figure 4 As shown, a second ion implantation 62 is performed on the substrate 1 along the first side wall of the main extension portion 3 to form the second drain doping region 82 .

[0025] The first drain doping region 81 and the second drain doping region 82 are formed by ion implantation. When forming the first drain doping region 81 and the second drain doping region 82, the ion implantation requires a certain implantation angle so that the ions can be implanted into the substrate 1 on both sides of the isolation structure, and the aspect ratio of the opening 9 located above the isolation structure limits the angle of the ion implantation. The higher the aspect ratio of the opening 9, the smaller the ion implantation angle, the more difficult it is to implant the ions into the substrate 1 on both sides of the isolation structure, and the shallower the depth of the ion implantation in the substrate 1 at the bottom of the floating gate material layer 6 along the lateral direction, resulting in a greater resistance of the first drain doping region 81 and the second drain doping region 82.

[0026] Moreover, the ion implantation needs to pass through the isolation structure and be implanted into the substrate 1 at the bottom of the floating gate material layer 6. The thickness of the isolation structure through which the ion implantation needs to pass needs to be precisely controlled, otherwise the depth and implantation dose of the ion implantation cannot be guaranteed, which also increases the difficulty of forming the first drain doping region 81 and the second drain doping region 82.

[0027] In addition, the first drain doping region 81 is formed by the first ion implantation 61, and the second drain doping region 82 is formed by the second ion implantation 62. The first drain doping region 81 and the second drain doping region 82 are formed in different ion implantation steps, respectively, and the consistency of the implantation dose and the implantation depth of the two ion implantations cannot be guaranteed, resulting in poor consistency of the device and poor performance of the device.

[0028] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, wherein the top surface of the isolation structure in the cell array region is lower than the top surface of the substrate, the first drain doping layer is located on the substrate side wall exposed along the second side of the isolation structure in the row direction, and the second drain doping layer is located on the substrate side wall exposed along the first side of the isolation structure in the row direction, and the first drain doping layer and the second drain doping layer are formed on the substrate side wall exposed by the isolation structure through an epitaxial process. In the embodiment of the present invention, the formation process of the first drain doping layer and the second drain doping layer avoids being restricted by the ion implantation process (for example, the restriction of the ion implantation angle), and the epitaxial process enables the first drain doping layer and the second drain doping layer to be selectively formed on the substrate exposed by the isolation structure. On the side wall, self-alignment of the formation positions of the first drain-doped layer and the second drain-doped layer is achieved, and the position accuracy of the first drain-doped layer and the second drain-doped layer is improved; moreover, the first drain-doped layer and the second drain-doped layer can be formed by an epitaxial process in the same step, which is beneficial to improving the ion doping uniformity and film growth uniformity of the first drain-doped layer and the second drain-doped layer, and correspondingly improving the performance consistency between storage cells; in addition, in the process of the epitaxial process for forming the first drain-doped layer and the second drain-doped layer, the doped atoms can be grown in situ in the lattice without the need for an additional activation step, which is beneficial to reducing the resistance of the first drain-doped layer and the second drain-doped layer; in summary, the embodiments of the present invention are beneficial to improving the performance of the semiconductor structure.

[0029] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 5 , shows a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 5 (a) is a top view, Figure 5 (b) Figure 5 (a) Cross-section along the 1-1' secant line.

[0030] like Figure 5 As shown, in this embodiment, the semiconductor structure includes: a substrate 100, including a plurality of discrete cell array regions C, for forming storage cells; a plurality of isolation structures extending in the column direction and arranged in the row direction, located in the substrate 100, and the top surface of the isolation structure in the cell array region C is lower than the top surface of the substrate 100; a first drain doping layer 210, located on the side wall of the substrate 100 exposed along the second side of the row direction of the isolation structure; a second drain doping layer 220, located on the side wall of the substrate 100 exposed along the first side of the row direction of the isolation structure; a floating gate 510, located on a portion of the substrate 100 between adjacent isolation structures in the cell array region C, and the floating gates 510 are discretely arranged at intervals along the column direction; a source region 240 along the column direction, located in the substrate 100 between adjacent floating gates 510 in the cell array region C.

[0031] The substrate 100 provides a process platform for forming a NOR Flash Memory.

[0032] Specifically, in this embodiment, the semiconductor structure is used to form 4F 2 In this NOR flash array, the area of ​​the NVM cell can be only 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0033] In this embodiment, the base 100 includes a substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0034] The cell array region C is used to form memory cells.

[0035] In this embodiment, the substrate 100 also includes a selection gate region S located between the cell array regions C along the column direction, a first transition region I located between the cell array region C and the selection gate region S on one side adjacent to the cell array region C along the column direction, and a second transition region II located between the cell array region C and the selection gate region S on the other side adjacent to the cell array region C along the column direction.

[0036] The select gate region S is located between the cell array regions C along the column direction and is used to form a select gate (SG). The first transition region I is used to connect the cell array region C and the select gate region S on one side adjacent to the cell array region C, and the second transition region II is used to connect the select gate region S on the other side adjacent to the cell array region C.

[0037] The isolation structure is used to isolate adjacent devices along the row.

[0038] In this embodiment, the isolation structure is a shallow trench isolation (STI) structure, and the material of the isolation structure is silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0039] In this embodiment, the top surface of the isolation structure of the cell array area C is lower than the top surface of the substrate 100, so that an epitaxial process can be used to form a first drain doping layer 210 on the side wall of the substrate 100 exposed along the second side of the row direction of the isolation structure, and to form a second drain doping layer 220 on the side wall of the substrate 100 exposed along the first side of the row direction of the isolation structure.

[0040] Combined with reference Figure 7In this embodiment, a plurality of grooves are formed in the substrate 100 and penetrate a portion of the thickness of the substrate 100. The grooves are arranged along the column direction (eg Figure 7 (a)) and along the row direction (as shown in the y direction) Figure 7 (a) as shown in the x-direction).

[0041] The trench is used to provide a spatial location for forming an isolation structure, and the trench is also used to define the area and location of an active area (AA).

[0042] In this embodiment, the trenches include a main trench 130 located in the cell array region C, a first offset trench 131 located in the select gate region S adjacent to one side of the cell array region C, and a second offset trench 132 located in the select gate region S adjacent to the other side of the cell array region C. The main trench 130, the first offset trench 131, and the second offset trench 132 extend in the column direction. The first offset trench 131 extends toward the first side (such as the first side) relative to the main trench 130 in the row direction. Figure 7 The second offset groove 132 is offset relative to the main groove 130 along the row direction toward the second side (as shown in the x1 direction in (a)). Figure 7 The groove further includes a first transition groove 1311 located between the first offset groove 131 and the main groove 130, and a second transition groove 1312 located between the second offset groove 132 and the main groove 130; the groove further includes a sub-groove 133 located in the selection gate region S and extending along the column direction, the sub-groove 133 is arranged with the first offset groove 131 and the second offset groove 132 in the row direction, and the sub-groove 133 also extends to the first transition region I and the second transition region II in the column direction.

[0043] The first transition groove 1311 is used to connect the first offset groove 131 and the main groove 130 , and the second transition groove 1312 is used to connect the second offset groove 132 and the main groove 130 .

[0044] As an embodiment, the first transition groove 1311 and the second transition groove 1312 are grooves with right-angle turns so as to be able to connect the corresponding offset groove and the main groove 130, and the first transition groove 1311 and the second transition groove 1312 are graphics with right-angle turns, which is also convenient for layout design.

[0045] In other embodiments, the first transition groove and the second transition groove may also be grooves of other shapes, as long as the first transition groove can connect the main groove and the first offset groove offset toward the first side along the row direction relative to the main groove, and the second transition groove can connect the main groove and the second offset groove offset toward the second side along the row direction relative to the main groove.

[0046] Accordingly, the active area (AA) of the selection gate region S adjacent to the cell array region C is arranged along the row direction toward the first side (eg, Figure 7 The active area of ​​the selection gate area S adjacent to the other side of the cell array area C is offset along the row direction relative to the active area of ​​the cell array area C toward the second side (as shown in the x1 direction in (a)). Figure 7 (a) is offset in the x2 direction.

[0047] Combined with reference Fig.10 In this embodiment, the isolation structure includes a main extension portion 300 located in the cell array region C, a first offset extension portion 310 located in the selection gate region S adjacent to one side of the cell array region C, and a second offset extension portion 320 located in the selection gate region S adjacent to the other side of the cell array region C; the main extension portion 300, the first offset extension portion 310 and the second offset extension portion 320 extend in the column direction, and the first offset extension portion 310 extends in the row direction toward the first side (such as Fig.10 The second offset extension portion 320 is offset relative to the main extension portion 300 along the row direction toward the second side (as shown in the x1 direction in (a)). Fig.10 (a) is offset in the x2 direction.

[0048] In this embodiment, the isolation structure also includes a first transition extension portion 330 located between the first offset extension portion 310 and the main extension portion 300, and a second transition extension portion 340 located between the second offset extension portion 320 and the main extension portion 300, the first transition extension portion 330 is formed on the first transition zone I, and the second transition extension portion 340 is formed on the second transition zone II.

[0049] Specifically, the main extension portion 300 is located in the main groove 130, the first offset extension portion 310 is located in the first offset groove 131, the second offset extension portion 320 is located in the second offset groove 132, the first transition extension portion 330 is located in the first transition groove 1311, and the second transition extension portion 340 is located in the second transition groove 1312.

[0050] In this embodiment, the first transition extension portion 330 and the adjacent portion of the first offset extension portion 310 further expose the second side along the row direction (eg Fig.10 (a) in the x2 direction) and covers the sidewall of the substrate 100 along the first side of the row direction (as shown in FIG. Fig.10The side wall of the substrate 100 (as shown in the x1 direction in (a)) is configured so that during the process of forming the first drain doped layer 210 by an epitaxial process, the first drain doped layer 210 can also extend to the first transition region I and the adjacent part of the selection gate region S, so that the first drain doped layer 210 can be electrically connected on the selection gate region S.

[0051] In this embodiment, the second transition extension 340 and the adjacent portion of the second offset extension 320 further expose the first side along the row direction (eg Fig.10 (a) in the x1 direction) and covers the sidewall of the substrate 100 along the second side in the row direction (as shown in FIG. Fig.10 The side wall of the substrate 100 (as shown in the x2 direction in (a)) is configured so that during the process of forming the second drain doped layer 220 by an epitaxial process, the second drain doped layer 220 can also extend to the second transition region II and the adjacent part of the selection gate region S, so that the second drain doped layer 220 can be electrically connected on the selection gate region S.

[0052] In this embodiment, the isolation structure further includes a secondary extension portion 350 located in the selection gate region S, along the column direction (eg Fig.10 The secondary extension portions 350 extend in the y direction (as shown in FIG. 1 ) and are arranged in a row direction with the first offset extension portions 310 or the second offset extension portions 320 . The secondary extension portions 350 cover the sidewalls of the substrate 100 .

[0053] In this embodiment, the top surface of the isolation structure located in the selection gate region S, the first transition region I and the second transition region II is relatively high. Fig.10 As shown in (a), the top surface of the isolation structure shown by the dotted line frame is higher, and the top surfaces of the remaining isolation structures are lower than the top surface of the substrate 100.

[0054] It should be noted that, along the direction perpendicular to the top surface of the substrate 100, the distance D between the top surface of the isolation structure of the cell array region C and the top surface of the substrate 100 (combined with reference Fig.10) should not be too small or too large. If the distance D is too small, the height of the side wall of the substrate 100 exposed by the isolation structure is too small, which may easily lead to the height of the first drain doping layer 210 or the second drain doping layer 220 formed on the side wall of the substrate 100 exposed by the isolation structure by the epitaxial process being too small, which may correspondingly lead to the volume of the first drain doping layer 210 or the second drain doping layer 220 being too small, and thus easily lead to the resistance of the first drain doping layer 210 and the second drain doping layer 220 being relatively large; if the distance D is too large, the height of the side wall of the substrate 100 exposed by the isolation structure is too large, which may easily lead to the depth of the first drain doping layer 210 and the second drain doping layer 220 being too deep, and thus easily increase the risk of leakage. For this reason, in the present embodiment, along the direction perpendicular to the top surface of the substrate 100, the distance D between the top surface of the isolation structure of the unit array area C and the top surface of the substrate 100 is 2nm to 20nm.

[0055] The first drain doped layer 210 is used to form a first drain sub-bitline.

[0056] In this embodiment, the first drain doped layer 210 is located on the sidewalls of the substrate 100 exposed along the second side of the row direction of the main extension portion 300, the first transition extension portion 330 and the adjacent portion of the first offset extension portion 310. The first drain doped layer 210 extends along the sidewalls of the substrate 100 along the second side of the row direction of the main extension portion 300 and the first transition extension portion 330, and the first drain doped layer 210 also extends to the sidewalls of the substrate 100 along the second side of the row direction of the adjacent first offset extension portion 310, so that the first drain doped layer 210 extends to the portion of the select gate region S adjacent to the first transition region I, thereby connecting the memory cell corresponding to the first drain sub-bit line to the select gate.

[0057] The second drain doped layer 220 is used to form a second drain sub-bitline.

[0058] In this embodiment, the second drain doping layer 220 is located on the sidewalls of the substrate 100 exposed along the first side of the row direction of the main extension portion 300, the second transition extension portion 340, and the adjacent portion of the second offset extension portion 320. The second drain doping layer 220 extends along the sidewalls of the main extension portion 300 and the second transition extension portion 340 along the first side of the row direction, and the second drain doping layer 220 also extends to the portion of the substrate 100 along the sidewalls of the adjacent second offset extension portion 320 along the first side of the row direction, so that the second drain doping layer 220 extends to the portion of the select gate region S adjacent to the second transition region II, thereby connecting the memory cell corresponding to the second drain sub-bit line to the select gate.

[0059] In the present embodiment, the first drain-doped layer 210 and the second drain-doped layer 220 include epitaxial layers doped with ions, and the first drain-doped layer 210 and the second drain-doped layer 220 are formed by an epitaxial process.

[0060] The epitaxial layer can also be used as a stress layer, thereby providing stress to the channel region, thereby improving the mobility of carriers.

[0061] In this embodiment, when a PMOS transistor is formed, the first drain doping layer 210 and the second drain doping layer 220 include an epitaxial layer doped with P-type ions, and the material of the epitaxial layer is Si or SiGe; when an NMOS transistor is formed, the first drain doping layer 210 and the second drain doping layer 220 include an epitaxial layer doped with N-type ions, and the material of the epitaxial layer is Si or SiC.

[0062] In this embodiment, the first drain doping layer 210 is recessed in the side wall of the substrate, and the second drain doping layer 220 is recessed in the side wall of the substrate 100, so that the first drain doping layer 210 and the second drain doping layer 220 also extend toward the inside of the substrate 100 at the bottom of the floating gate 510 along the channel extension direction, which is beneficial to form a graded junction between the first drain doping layer 210 and the channel, and between the second drain doping layer 220 and the channel, thereby helping to reduce the peak electric field near the first drain doping layer 210 and the second drain doping layer 220, and further helping to weaken the hot carrier injection effect, thereby optimizing the performance of the semiconductor structure.

[0063] It should be noted that the depth of the first drain doping layer 210 or the second drain doping layer 220 sunken into the side wall of the substrate 100 along the direction perpendicular to the side wall of the substrate 100 should not be too small or too large. If the depth of the first drain doping layer 210 or the second drain doping layer 220 sunken into the side wall of the substrate 100 is too small, the depth of the first drain doping layer 210 and the second drain doping layer 220 extending into the substrate 100 at the bottom of the floating gate 510 along the channel extension direction is too small, and the effect of weakening the hot carrier injection effect is not obvious; if the depth of the first drain doping layer 210 or the second drain doping layer 220 sunken into the side wall of the substrate 100 is too large, the depth of the first drain doping layer 210 and the second drain doping layer 220 extending into the substrate 100 at the bottom of the floating gate 510 along the channel extension direction is too large, which easily leads to the distance between the first drain doping layer 210 and the source region 240, and between the second drain doping layer 220 and the source region 240 being too close. To this end, in this embodiment, along a direction perpendicular to the sidewall of the substrate 100 , the first drain doping layer 210 or the second drain doping layer 220 is recessed into the sidewall of the substrate 100 to a depth of 1 nm to 10 nm.

[0064] In this embodiment, the semiconductor structure further includes: a filling dielectric layer 180 located on the isolation structure and covering the sidewalls of the first drain doping layer 210 and the second drain doping layer 220 , and the top surface of the filling dielectric layer 180 is flush with the top surface of the substrate 100 .

[0065] The filling dielectric layer 180 is used to make the top surface of the substrate 100 and the top surface of the isolation structure flush with each other.

[0066] In this embodiment, the filling dielectric layer 180 and the isolation structure constitute an isolation portion, and the entire surface of the isolation portion is flush with the top surface of the substrate 100 .

[0067] In this embodiment, in order to improve process compatibility, the material of the filling dielectric layer 180 is the same as that of the isolation structure, and the material of the filling dielectric layer 180 is silicon oxide. In other embodiments, the material of the filling dielectric layer and the isolation structure may be different, and the filling dielectric layer may also be made of other materials.

[0068] When the NOR flash memory is working, the floating gate 510 can capture and store electrons, and after power failure, the electrons stored in the floating gate 510 will not be lost. The amount of charge stored in the floating gate 510 can change the on-voltage of the field effect transistor, and different on-voltages can represent different states, thereby realizing information storage.

[0069] In this embodiment, the floating gate 510 is an island structure.

[0070] In this embodiment, the floating gate 510 is made of polysilicon or amorphous silicon.

[0071] The semiconductor structure further includes a tunneling oxide layer 410 located between the floating gate 510 and the substrate 100 .

[0072] The tunneling oxide (TOX) layer 410 is used to provide a tunneling channel for electrons from the substrate 100 to the floating gate 510. The tunneling oxide layer 410 is also used to isolate the floating gate 510 from the substrate 100. In this embodiment, the material of the tunneling oxide layer 410 is silicon oxide.

[0073] The source region 240 is used as a common source region. The source region 240 is located in the substrate 100 below the source region opening 230, and the source region 240 extends along the column direction. In this embodiment, the source region 240 is located in the cell array region C, the adjacent first transition region I and second transition region II, and part of the selection gate region S along the column direction, so that the source region 240 can extend to the selection gate region S to be connected to the selection gate.

[0074] When forming an NMOS device, the source region 240 is doped with N-type ions; when forming a PMOS device, the source region 240 is doped with P-type ions. The ion doping type of the source region 240 is the same as that of the first drain region 210 and the second drain region 220 .

[0075] In this embodiment, the semiconductor structure also includes: a plurality of control gates 530 extending in the row direction and arranged at intervals in the column direction, covering the floating gates 510 in the row direction, as well as the substrate 100 and the filling dielectric layer 180 between the floating gates 510; and an inter-gate dielectric layer 520, located between the floating gates 510 and the control gates 530 in the cell array region C.

[0076] When the NOR flash memory is working, programming is achieved by changing the electron injection into the floating gate 510 or erasing from the floating gate 510 through the control gate 530.

[0077] In this embodiment, the control gate 530 is a strip-shaped structure extending along the row direction.

[0078] In this embodiment, the control gate 530 covers the floating gate 510, the substrate 100, and the isolation portion formed by the filling dielectric layer 180 and the isolation structure.

[0079] In this embodiment, the material of the control gate 530 is polysilicon or amorphous silicon.

[0080] The inter-gate dielectric layer 520 is used to achieve isolation between the control gate 530 and the floating gate 510 . The inter-gate dielectric layer 520 is also used to achieve isolation between the control gate 530 and the substrate 100 .

[0081] The material of the gate dielectric layer 520 is a dielectric material. In this embodiment, the gate dielectric material layer 430 is a stacked structure. As an example, the gate dielectric layer 520 is an ONO (Oxide-Nitride-Oxide) structure, and the gate dielectric layer 520 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0082] In other embodiments, according to actual process requirements, the inter-gate dielectric layer may also be made of other suitable materials, and the inter-gate dielectric layer may also be a single-layer structure.

[0083] In this embodiment, the floating gate 510 , the inter-gate dielectric layer 520 , and the control gate 530 located in the cell array region C constitute a gate structure 500 .

[0084] In the selection gate region S, there is no isolation between the floating gate 510 and the control gate 530, and the floating gate 510 and the control gate 530 can contact each other, so that the floating gate 510 and the control gate 530 located in the selection gate region S are used to form the gate of the selection gate MOS.

[0085] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0086] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0087] refer to Figure 6 , providing a substrate 100, including a plurality of discrete cell array regions C for forming memory cells.

[0088] The substrate 100 provides a process platform for forming a NOR Flash Memory. Specifically, in this embodiment, the substrate 100 is used to form a 4F 2 In this NOR flash array, the area of ​​the NVM cell can be only 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0089] In this embodiment, the base 100 includes a substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0090] The cell array region C is used to form memory cells.

[0091] In this embodiment, the substrate 100 also includes a selection gate region S located between the cell array regions C along the column direction, a first transition region I located between the cell array region C and the selection gate region S on one side adjacent to the cell array region C along the column direction, and a second transition region II located between the cell array region C and the selection gate region S on the other side adjacent to the cell array region C along the column direction.

[0092] The select gate region S is located between the cell array regions C along the column direction and is used to form a select gate (SG). The first transition region I is used to connect the cell array region C and the select gate region S on one side adjacent to the cell array region C, and the second transition region II is used to connect the select gate region S on the other side adjacent to the cell array region C.

[0093] refer to Figure 7 , Figure 7 (a) is a top view, Figure 7 (b) Figure 7 (a) A cross-sectional view along the 1-1' cut line, forming a plurality of grooves penetrating a portion of the thickness of the substrate 100, the grooves extending along the column direction (eg Figure 7 (a)) and along the row direction (as shown in the x direction) Figure 7 (a) as shown in the y direction).

[0094] The trench is used to provide a spatial location for forming an isolation structure, and the trench is also used to define the area and location of an active area (AA).

[0095] In this embodiment, the trenches include a main trench 130 located in the cell array region C, a first offset trench 131 located in the select gate region S adjacent to one side of the cell array region C, and a second offset trench 132 located in the select gate region S adjacent to the other side of the cell array region C. The main trench 130, the first offset trench 131, and the second offset trench 132 extend in the column direction. The first offset trench 131 extends toward the first side (such as the first side) relative to the main trench 130 in the row direction. Figure 8 The second offset groove 132 is offset relative to the main groove 130 along the row direction toward the second side (as shown in the x1 direction in (a)). Figure 8 The groove further includes a first transition groove 1311 located between the first offset groove 131 and the main groove 130, and a second transition groove 1312 located between the second offset groove 132 and the main groove 130; the groove further includes a sub-groove 133 located in the selection gate region S and extending along the column direction, the sub-groove 133 is arranged with the first offset groove 131 and the second offset groove 132 in the row direction, and the sub-groove 133 also extends to the first transition region I and the second transition region II in the column direction.

[0096] The first transition groove 1311 is used to connect the first offset groove 131 and the main groove 130 , and the second transition groove 1312 is used to connect the second offset groove 132 and the main groove 130 .

[0097] As an embodiment, the first transition groove 1311 and the second transition groove 1312 are grooves with right-angle turns so as to be able to connect the corresponding offset groove and the main groove 130, and the first transition groove 1311 and the second transition groove 1312 are graphics with right-angle turns, which is also convenient for layout design.

[0098] In other embodiments, the first transition groove and the second transition groove may also be grooves of other shapes, as long as the first transition groove can connect the main groove and the first offset groove offset toward the first side along the row direction relative to the main groove, and the second transition groove can connect the main groove and the second offset groove offset toward the second side along the row direction relative to the main groove.

[0099] Accordingly, the active area (AA) of the selection gate region S adjacent to the cell array region C is arranged along the row direction toward the first side (eg, Figure 7 The active area of ​​the selection gate area S adjacent to the other side of the cell array area C is offset along the row direction relative to the active area of ​​the cell array area C toward the second side (as shown in the x1 direction in (a)). Figure 7 (a) is offset in the x2 direction.

[0100] In this embodiment, the step of forming the groove includes: forming a hard mask layer 120 on the substrate 100, wherein a plurality of mask openings 125 are formed in the hard mask layer 120; using the hard mask layer 120 as a mask, removing a portion of the thickness of the substrate 100 exposed by the mask openings 125 to form the groove.

[0101] The hard mask layer 120 is used as an etching mask for forming a groove, and the mask opening 125 is used to define the shape and position of the groove. In addition, the hard mask layer 120 is also used to protect the top surface of the substrate 100 during the subsequent formation of the isolation structure, the first drain doping layer and the second drain doping layer.

[0102] As an embodiment, the material of the hard mask layer 120 is silicon nitride.

[0103] It should be noted that before forming the hard mask layer 120 on the substrate 100, the formation method further includes: forming a pad oxide layer 110 on the substrate 100. The pad oxide layer 110 is used to improve the adhesion between the hard mask layer 120 and the substrate 100, and prevent the hard mask layer 120 from being directly formed on the substrate 100 to generate a large stress and cause defects and other problems.

[0104] In this embodiment, the material of the pad oxide layer 110 is silicon oxide.

[0105] refer to Figures 8 to 10 , an isolation structure is formed in the trench, and a top surface of the isolation structure in the cell array region C is lower than a top surface of the substrate 100 .

[0106] The isolation structure is used to isolate adjacent devices along the row.

[0107] In this embodiment, the isolation structure is a shallow trench isolation (STI) structure, and the material of the isolation structure is silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0108] In this embodiment, the top surface of the isolation structure of the cell array area C is lower than the top surface of the substrate 100, so that an epitaxial process can be subsequently used to form a first drain doping layer on the side wall of the substrate 100 exposed along the second side of the row direction of the isolation structure, and to form a second drain doping layer on the side wall of the substrate 100 exposed along the first side of the row direction of the isolation structure.

[0109] In this embodiment, the isolation structure includes a main extension portion 300 located in the cell array region C, a first offset extension portion 310 located in the selection gate region S adjacent to one side of the cell array region C, and a second offset extension portion 320 located in the selection gate region S adjacent to the other side of the cell array region C; the main extension portion 300, the first offset extension portion 310 and the second offset extension portion 320 extend in the column direction, and the first offset extension portion 310 extends in the row direction relative to the main extension portion 300 toward the first side (such as Fig.10 The second offset extension portion 320 is offset relative to the main extension portion 300 along the row direction toward the second side (as shown in the x1 direction in (a)). Fig.10 (a) is offset in the x2 direction.

[0110] In this embodiment, the isolation structure also includes a first transition extension portion 330 located between the first offset extension portion 310 and the main extension portion 300, and a second transition extension portion 340 located between the second offset extension portion 320 and the main extension portion 300, the first transition extension portion 330 is formed on the first transition zone I, and the second transition extension portion 340 is formed on the second transition zone II.

[0111] Specifically, the main extension portion 300 is located in the main groove 130, the first offset extension portion 310 is located in the first offset groove 131, the second offset extension portion 320 is located in the second offset groove 132, the first transition extension portion 330 is located in the first transition groove 1311, and the second transition extension portion 340 is located in the second transition groove 1312.

[0112] In this embodiment, the first transition extension portion 330 and the adjacent portion of the first offset extension portion 310 further expose the second side along the row direction (eg Fig.10 (a) in the x2 direction) and covers the sidewall of the substrate 100 along the first side of the row direction (as shown in FIG. Fig.10 The side wall of the substrate 100 (as shown in the x1 direction in (a)) is provided so that in the subsequent process of forming the first drain doped layer by an epitaxial process, the first drain doped layer can also extend to the first transition region I and the adjacent part of the selection gate region S, so that in the subsequent process flow, the first drain doped layer can be electrically connected on the selection gate region S.

[0113] In this embodiment, the second transition extension 340 and the adjacent portion of the second offset extension 320 further expose the first side along the row direction (eg Fig.10 (a) in the x1 direction) and covers the sidewall of the substrate 100 along the second side in the row direction (as shown in FIG. Fig.10 The side wall of the substrate 100 (as shown in the x2 direction in (a)) is provided so that in the subsequent process of forming the second drain doped layer by an epitaxial process, the second drain doped layer can also extend to the second transition region II and the adjacent part of the selection gate region S, so that in the subsequent process flow, the second drain doped layer can be electrically connected on the selection gate region S.

[0114] In this embodiment, the isolation structure further includes a secondary extension portion 350 located in the selection gate region S, along the column direction (eg Fig.10 The secondary extension portions 350 extend in the y direction (as shown in FIG. 1 ) and are arranged in a row direction with the first offset extension portions 310 or the second offset extension portions 320 . The secondary extension portions 350 cover the sidewalls of the substrate 100 .

[0115] Specifically, in this embodiment, the second transition extension portion 340 and the adjacent portion of the second offset extension portion 320 also cover the second side along the row direction (eg Fig.10 The second transition extension 340 and the adjacent second offset extension 320 also cover the sidewall of the hard mask layer 120 along the second side in the row direction (as shown in the x2 direction in (a)). Fig.10 The secondary extension portion 350 also covers the sidewall of the hard mask layer 120 .

[0116] Accordingly, in this embodiment, the top surface of the portion of the isolation structure located in the selection gate region S, the first transition region I and the second transition region II is relatively high. Fig.10 As shown in (a), the top surface of the isolation structure shown by the dotted line frame is higher, and the top surfaces of the remaining isolation structures are lower than the top surface of the substrate 100.

[0117] It should be noted that, along the direction perpendicular to the top surface of the substrate 100, the distance D between the top surface of the isolation structure of the cell array region C and the top surface of the substrate 100 should not be too small or too large. If the distance D is too small, the height of the side wall of the substrate 100 exposed by the isolation structure is too small, which may easily lead to the height of the first drain doping layer or the second drain doping layer formed on the side wall of the substrate 100 exposed by the isolation structure by the subsequent epitaxial process being too small, which may correspondingly easily lead to the volume of the first drain doping layer or the second drain doping layer being too small, and thus easily lead to the resistance of the first drain doping layer and the second drain doping layer being large; if the distance D is too large, the height of the side wall of the substrate 100 exposed by the isolation structure is too large, which may easily lead to the depth of the subsequent first drain doping layer and the second drain doping layer being too deep, and thus easily increase the risk of leakage. For this reason, in the present embodiment, along the direction perpendicular to the top surface of the substrate 100, the distance D between the top surface of the isolation structure of the cell array region C and the top surface of the substrate is 2nm to 20nm.

[0118] The specific steps of forming the isolation structure in this embodiment are described in detail below with reference to the accompanying drawings.

[0119] like Figure 8 As shown, Figure 8 (a) is a top view, Figure 8 (b) Yes Figure 8 (a) is a cross-sectional view along the 1-1′ cut line, in which the trench is filled with an isolation material layer 140. In this embodiment, the isolation material layer 140 is also filled in the mask opening 125.

[0120] The isolation material layer 140 is used to form an isolation structure through subsequent back etching.

[0121] In this embodiment, the step of forming the isolation material layer 140 includes: filling an isolation film (not shown) in the groove and the mask opening 125, and the isolation film is also formed on the hard mask layer 120; planarizing the isolation film, removing the isolation film located on the hard mask layer 120, and the remaining isolation film is used as the isolation material layer 140.

[0122] In this embodiment, the process of forming the isolation film includes a flow chemical vapor deposition process.

[0123] In this embodiment, the process of planarizing the isolation film includes a chemical mechanical planarization process.

[0124] like Fig. 9 As shown, it is shown based on Figure 8(a) shows a top view, in which an etching mask layer 150 is formed on the isolation material layer 140. Specifically, the isolation material layer 140 is also located on the hard mask layer 120, and the etching mask layer 150 exposes the isolation material layer 140 to be etched. In this embodiment, the etching mask layer 150 covers a portion of the top surface of the isolation material layer 140 in the selection gate region S, the first transition region I, and the second transition region II.

[0125] The etching mask layer 150 may be an inorganic mask layer, such as silicon nitride, silicon oxynitride and other materials; the etching mask layer 150 may also be an organic mask layer, such as photoresist, spin-on carbon (SOC) and other materials.

[0126] like Fig.10 As shown, Fig.10 (a) is a top view, Fig.10 (b) Fig.10 (a) A cross-sectional view along the 1-1′ cut line, in which a portion of the isolation material layer 140 exposed by the etching mask layer 150 is removed, and the remaining isolation material layer 140 after etching is used as the isolation structure.

[0127] As an example, a wet etching process is used to etch the isolation material layer 140 exposed by the etching mask layer 150. In other embodiments, a dry etching process or an etching process combining a wet etching process and a dry etching process may also be used to etch the isolation material layer exposed by the etching mask layer.

[0128] After removing the partially exposed isolation material layer 140 by the etching mask layer 150 , the method further includes: removing the etching mask layer 150 to facilitate subsequent process steps.

[0129] Combined with reference Figure 11 to Figure 12 In an optional solution, the method for forming the semiconductor structure further includes: after forming the isolation structure, forming a sidewall groove 170 in the sidewall of the substrate 100 exposed by the isolation structure.

[0130] By forming a sidewall groove 170 in the sidewall of the substrate 100 exposed by the isolation structure, after forming a first drain doping layer or a second drain doping layer in the sidewall groove 170, the first drain doping layer and the second drain doping layer are correspondingly recessed in the sidewall of the substrate 100. After subsequently forming a floating gate on the substrate 100 exposed by the isolation structure, the first drain doping layer and the second drain doping layer are correspondingly extended toward the inside of the substrate 100 at the bottom of the floating gate along the channel extension direction, which is beneficial to forming a graded junction between the first drain doping layer and the channel, and between the second drain doping layer and the channel, thereby facilitating the reduction of the peak electric field near the first drain doping layer and the second drain doping layer, and further facilitating the weakening of the hot carrier injection effect.

[0131] It should be noted that the depth of the sidewall groove 170 should not be too small or too large along the direction perpendicular to the sidewall of the substrate 100 exposed by the isolation structure. If the depth of the sidewall groove 170 is too small, the depth of the first drain doping layer and the second drain doping layer extending into the floating gate bottom substrate 100 along the channel extension direction is too small, and the weakening effect of the hot carrier injection effect is not obvious; if the depth of the sidewall groove 170 is too large, the depth of the first drain doping layer and the second drain doping layer extending into the floating gate bottom substrate 100 along the channel extension direction is too large, and after the source region is subsequently formed, it is easy to cause the distance between the first drain doping layer and the source region, and between the second drain doping layer and the source region to be too close. For this reason, in this embodiment, along the direction perpendicular to the sidewall of the substrate 100 exposed by the isolation structure, the depth of the sidewall groove 170 is 1nm to 10nm.

[0132] As an embodiment, the step of forming a sidewall groove 170 in the sidewall of the substrate 100 exposed by the isolation structure includes:

[0133] like Fig.11 As shown, a cross-sectional view along the row direction in the cell array region C is shown, and the side wall of the substrate 100 exposed by the isolation structure is oxidized so that a portion of the thickness of the side wall of the substrate 100 exposed by the isolation structure is converted into a sacrificial oxide layer 160.

[0134] In this embodiment, the material of the substrate 100 is silicon, and the material of the sacrificial oxide layer 160 is correspondingly silicon oxide.

[0135] In this embodiment, a thermal oxidation process is used to oxidize the sidewalls of the substrate 100 exposed by the isolation structure.

[0136] As an embodiment, a low temperature oxidation process is used to oxidize the exposed sidewalls of the substrate 100 of the isolation structure. The temperature of the low temperature oxidation process is relatively low, which is beneficial to reducing the thermal budget.

[0137] like Fig.12 As shown, the sacrificial oxide layer 160 is removed to form the sidewall groove 170 .

[0138] In this embodiment, a wet etching process is used to remove the sacrificial oxide layer 160 .

[0139] Specifically, the sacrificial oxide layer 160 is made of silicon oxide, and a diluted hydrofluoric acid solution (DHF) is used to remove the sacrificial oxide layer 160 .

[0140] It should be noted that the above step of forming the sidewall groove 170 is only an embodiment, and the method of forming the sidewall groove 170 is not limited thereto.

[0141] For example, in other embodiments, an isotropic etching process may be used to etch the exposed substrate sidewall of the isolation structure to form the sidewall groove. The isotropic etching process has the characteristic of isotropic etching, so that the substrate sidewall can be etched along a direction perpendicular to the substrate sidewall, thereby forming the sidewall groove on the substrate sidewall.

[0142] Specifically, the isotropic etching process includes a remote plasma etching process or a wet etching process. Both the remote plasma etching process and the wet etching process can achieve isotropic etching.

[0143] refer to Fig.13 , Fig.13 (a) is a top view, Fig.13 (b) Fig.13 (a) A cross-sectional view along the 1-1' cut line, wherein an epitaxial process is used to extend the isolation structure along the second side (eg Fig.14 The first drain doping layer 210 is formed on the sidewall of the substrate 100 exposed along the x2 direction in (a), and the first side of the isolation structure along the row direction (such as Fig.13 The exposed substrate sidewall 100 (in the x1 direction in (a)) forms a second drain doping layer 220.

[0144] Compared with the solution of forming the drain region by ion implantation, the epitaxial process adopted in this embodiment is advantageous in avoiding the formation of the first drain doping layer and the second drain doping layer being restricted by the ion implantation process (for example, the restriction of the ion implantation angle), and the epitaxial process enables the first drain doping layer 210 and the second drain doping layer 220 to be selectively formed on the sidewall of the substrate 100 exposed by the isolation structure, thereby achieving self-alignment of the formation positions of the first drain doping layer 210 and the second drain doping layer 220, and improving the position accuracy of the first drain doping layer 210 and the second drain doping layer 220;

[0145] Moreover, by forming the first drain doping layer 210 and the second drain doping layer 220 in the same step by using an epitaxial process, it is beneficial to improve the ion doping uniformity and film growth uniformity of the first drain doping layer 210 and the second drain doping layer 220, and correspondingly improve the performance consistency between memory cells;

[0146] In addition, during the epitaxial process, doping atoms can be grown in situ in the crystal lattice without an additional activation step, which is beneficial to reducing the resistance of the first drain doping layer 210 and the second drain doping layer 220;

[0147] In summary, this embodiment is beneficial to improving the performance of the semiconductor structure.

[0148] The first drain doped layer 210 is used to form a first drain sub-bitline.

[0149] In this embodiment, the first drain doping layer 210 is formed on the sidewalls of the substrate 100 exposed along the second side of the row direction of the main extension portion 300, the first transition extension portion 330 and the adjacent portion of the first offset extension portion 310. The first drain doping layer 210 extends along the sidewalls of the substrate 100 along the second side of the row direction of the main extension portion 300 and the first transition extension portion 330, and the first drain doping layer 210 also extends to the sidewalls of the substrate 100 along the second side of the row direction of the adjacent first offset extension portion 310, so that the first drain doping layer 210 extends to the portion of the select gate region S adjacent to the first transition region I, thereby connecting the memory cell corresponding to the first drain sub-bit line to the select gate.

[0150] The second drain doped layer 220 is used to form a second drain sub-bitline.

[0151] In this embodiment, the second drain doping layer 220 is formed on the sidewalls of the substrate 100 exposed along the first side of the row direction of the main extension portion 300, the second transition extension portion 340, and the adjacent portion of the second offset extension portion 320. The second drain doping layer 220 extends along the sidewalls of the main extension portion 300 and the second transition extension portion 340 along the first side of the row direction, and the second drain doping layer 220 also extends to the portion of the substrate 100 along the sidewalls of the adjacent second offset extension portion 320 along the first side of the row direction, so that the second drain doping layer 220 extends to the portion of the select gate region S adjacent to the second transition region II, thereby connecting the storage cell corresponding to the second drain sub-bit line to the select gate.

[0152] Specifically, in this embodiment, the first drain doping layer 210 is formed in the sidewall groove 170 on the second side of the isolation structure along the row direction, and the second drain doping layer 220 is formed in the sidewall groove 170 on the first side of the isolation structure along the row direction.

[0153] The first drain doping layer 210 and the second drain doping layer 220 are respectively recessed in the side walls of the substrate 100. After a floating gate is subsequently formed on the substrate 100 where the isolation structure is exposed, the first drain doping layer 210 and the second drain doping layer 220 are respectively extended along the channel extension direction toward the inside of the substrate 100 at the bottom of the floating gate, which is beneficial to form a graded junction between the first drain doping layer 210 and the channel, and between the second drain doping layer 220 and the channel, thereby facilitating the reduction of the peak electric field near the first drain doping layer 210 and the second drain doping layer 220, and further facilitating the weakening of the hot carrier injection effect, thereby optimizing the performance of the semiconductor structure.

[0154] Accordingly, the first drain doping layer 210 and the second drain doping layer 220 include epitaxial layers doped with ions, wherein the epitaxial layers can also be used as stress layers, thereby providing stress to the channel region, thereby improving the mobility of carriers.

[0155] In this embodiment, when a PMOS transistor is formed, the first drain doping layer 210 and the second drain doping layer 220 include an epitaxial layer doped with P-type ions, and the material of the epitaxial layer is Si or SiGe; when an NMOS transistor is formed, the first drain doping layer 210 and the second drain doping layer 220 include an epitaxial layer doped with N-type ions, and the material of the epitaxial layer is Si or SiC.

[0156] In this embodiment, an epitaxial process is adopted to form the epitaxial layer, and in the process of forming the epitaxial layer, ions are self-doped in situ to form the first drain doping layer 210 and the second drain doping layer 220 .

[0157] In this embodiment, the epitaxial process is a selective epitaxial process. The selective epitaxial process utilizes the basic principle of epitaxial growth and the property that silicon is difficult to nucleate and form a film on an insulator, so that epitaxial growth can be performed only in specific areas of the semiconductor structure. Specifically, during the epitaxial process, a corrosive gas (e.g., HCl) is also introduced to remove the epitaxial material formed on the undesired area (e.g., the insulating material).

[0158] In this embodiment, a floating gate material layer is subsequently formed on the substrate 100 between the isolation structures. The material of the floating gate material layer is usually polycrystalline silicon or amorphous silicon. Before forming the floating gate material layer, the first drain doping layer 210 and the second drain doping layer 220 are formed to prevent damage to the floating gate material layer during the epitaxial process.

[0159] refer to Figure 14 to Figure 15 In this embodiment, after forming the first drain doping layer 210 and the second drain doping layer 220 and before forming the floating gate material layer, the formation method further includes: removing the hard mask layer 120 to expose the top surface of the substrate 100, so that a floating gate material layer can be subsequently formed on the substrate 100.

[0160] In this embodiment, after removing the hard mask layer 120 , the method further includes: removing the pad oxide layer 110 .

[0161] Combined with reference Fig.14 In this embodiment, the method for forming the semiconductor structure further includes: after forming the first drain doping layer 210 and the second drain doping layer 220, before removing the hard mask layer 120, forming a filling dielectric layer 180 filling the trench and the mask opening 125 on the isolation structure.

[0162] Accordingly, in the step of removing the hard mask layer 120, the filling dielectric layer 180 and the substrate 100 form a floating gate opening 320, so that the floating gate opening 320 can define the shape and formation position of the subsequent floating gate material layer, so that the formation of the floating gate material layer does not require a graphic step, which is correspondingly conducive to simplifying the process and saving costs.

[0163] In this embodiment, in order to improve process compatibility, the material of the filling dielectric layer 180 is the same as that of the isolation structure, and the material of the filling dielectric layer 180 is silicon oxide. In other embodiments, the material of the filling dielectric layer and the isolation structure may be different, and the filling dielectric layer may also be made of other materials.

[0164] In this embodiment, the step of forming the filling dielectric layer 180 includes: filling a dielectric material layer in the groove and the mask opening 125, and the dielectric material layer is also formed on the hard mask layer 120; using a planarization process to remove the dielectric material layer located on the hard mask layer 120.

[0165] In this embodiment, a deposition process is used to form the dielectric material layer. Specifically, the deposition process may be a flow chemical vapor deposition process. In this embodiment, the planarization process may be a chemical mechanical planarization process.

[0166] Accordingly, in this embodiment, during the process of forming the hard mask layer 120, the height of the hard mask layer 120 needs to be greater than or equal to the target height of the floating gate material layer so that during the subsequent process of forming the floating gate material layer in the floating gate opening, the floating gate material layer can have the target height.

[0167] refer to Fig.16 , a floating gate material layer 420 is formed on the substrate 100 between the isolation structures.

[0168] The floating gate material layer 420 is used to form a floating gate.

[0169] In this embodiment, the floating gate material layer 420 is made of polysilicon or amorphous silicon.

[0170] In this embodiment, the step of forming the floating gate material layer 420 includes: filling the floating gate material layer 420 in the floating gate opening 190 .

[0171] Specifically, an initial floating gate material layer is formed in the floating gate opening 190 , and the initial floating gate material layer is also formed on the top surface of the filling dielectric layer 180 ; the initial floating gate material layer is planarized, and the initial floating gate material layer located on the top surface of the filling dielectric layer 180 is removed to form a floating gate material layer 420 .

[0172] In this embodiment, a tunneling oxide layer 410 is further formed between the floating gate material layer 420 and the top surface of the substrate 100. The tunneling oxide (TOX) layer 410 is used to provide a tunneling channel for electrons from the substrate 100 to the floating gate. The tunneling oxide layer 410 is also used to isolate the floating gate from the substrate 100. In this embodiment, the material of the tunneling oxide layer 410 is silicon oxide.

[0173] refer to Fig.17 A source region opening 230 is formed in the floating gate material layer 420 along the column direction. The source region opening 230 penetrates the cell array region C along the column direction, and a partial width of the floating gate material layer 420 is retained on both sides of the source region opening 230 .

[0174] The source region opening 230 is used to define the subsequent source region formation area. In this embodiment, the source region opening 230 penetrates the cell array region C, the adjacent first transition region I and second transition region II, and part of the selection gate region S along the column direction, so that after the source region is subsequently formed in the substrate 100 at the bottom of the source region opening 230 and the selection gate located in the selection gate region S is formed, the source region can extend to the selection gate region S to be connected to the selection gate.

[0175] Specifically, a mask layer (not shown) may be formed first, and then the floating gate material layer 420 may be etched using the mask layer as a mask and a dry etching process.

[0176] In this embodiment, the bottom of the source region opening 230 exposes the top surface of the substrate 100 as an example for description. In other embodiments, the bottom of the source region opening may also retain the tunnel oxide layer, which can protect the substrate in the subsequent process of forming the source region.

[0177] refer to Fig.18 , a source region 240 is formed in the substrate at the bottom of the source region opening 230 .

[0178] The source region 240 is used as a common source region. The source region 240 is located in the substrate 100 below the source region opening 230, and the source region 240 extends along the column direction. In this embodiment, the source region 240 is located in the cell array region C, the adjacent first transition region I and second transition region II, and part of the selection gate region S along the column direction, so that after the selection gate located in the selection gate region S is subsequently formed, the source region 240 can extend to the selection gate region S to be connected to the selection gate.

[0179] When forming an NMOS device, the source region 240 is doped with N-type ions; when forming a PMOS device, the source region 240 is doped with P-type ions. The ion doping type of the source region 240 is the same as that of the first drain region 210 and the second drain region 220 .

[0180] In this embodiment, an ion implantation process is used to perform ion doping on the substrate 100 at the bottom of the source region opening 230 to form the source region 240 .

[0181] In the present embodiment, in the step of forming the source region 240, the filling dielectric layer 180 is also retained, and the filling dielectric layer 180 covers the side walls of the first drain-doped layer 210 and the second drain-doped layer 220, and the top surface of the filling dielectric layer 180 is flush with the top surface of the floating gate material layer 420, so as to protect the first drain-doped layer 210 and the second drain-doped layer 220, so as to prevent the ion doping process for forming the source region 240 from affecting the first drain-doped layer 210 and the second drain-doped layer 220, for example: preventing the ion implantation process for forming the source region 240 from passing through the filling dielectric layer 180 or the isolation structure and implanting ions into the first drain-doped layer 210 and the second drain-doped layer 220, and the filling dielectric layer 180 and the isolation structure, as well as the floating gate material layer 420, can completely cover the area where the source region 240 is not desired to be formed, which is also beneficial to improving the position accuracy of the source region 240.

[0182] refer to Fig.19 After forming the source region 240, the method for forming the semiconductor structure includes: removing a portion of the thickness of the filling dielectric layer 180 so that the top surface of the remaining filling dielectric layer 180 is flush with the top surface of the substrate 100, thereby exposing the side walls of the floating gate material layer 420 and the area between adjacent floating gate material layers 420, so as to subsequently form a control gate material layer covering the floating gate material layer 420, the filling dielectric layer 180 and the substrate 100, as well as a patterned control gate material layer and the floating gate material layer 420.

[0183] In this embodiment, in the step of removing a portion of the filling dielectric layer 180 , a portion of the isolation structure is also removed, and the remaining filling dielectric layer 180 and the isolation structure constitute an isolation portion, the entire surface of which is flush with the top surface of the substrate 100 .

[0184] The process of removing a portion of the filling dielectric layer 180 may be any one or both of dry etching and wet etching processes.

[0185] refer to Fig. 20 After removing a portion of the thickness of the filling dielectric layer 180 , the method for forming the semiconductor structure further includes: forming a control gate material layer 440 covering the floating gate material layer 420 , the filling dielectric layer 180 and the substrate 100 .

[0186] The control gate material layer 440 is used for subsequently forming a control gate.

[0187] In this embodiment, the control gate material layer 440 covers the floating gate material layer 420 , the substrate 100 , and the isolation portion formed by the remaining filling dielectric layer 180 and the isolation structure.

[0188] In this embodiment, the material of the control gate material layer 440 is polysilicon or amorphous silicon. In this embodiment, the process of forming the control gate material layer includes a deposition process (eg, a chemical vapor deposition process).

[0189] In this embodiment, the formation method also includes: before forming the control gate material layer 440, forming a gate dielectric material layer 430 on the isolation portion, the substrate 100, and the top surface and side wall of the floating gate material layer 420; and removing the gate dielectric material layer 430 located in the selection gate region S.

[0190] Correspondingly, the control gate material layer 440 located in the selection gate area S is formed on the floating gate material layer 420, so that after the control gate material layer 440 and the floating gate material layer 420 are subsequently patterned to form a control gate and a floating gate respectively, in the selection gate area S, there is no isolation between the floating gate and the control gate, and the floating gate and the control gate can contact each other, and the floating gate and the control gate located in the selection gate area S constitute the gate of the selection gate MOS.

[0191] Correspondingly, the control gate material layer 440 located in the first transition region I and the second transition region II is formed on the gate dielectric material layer 430 .

[0192] The gate dielectric material layer 430 is used to form an inter-gate dielectric layer.

[0193] The material of the gate dielectric material layer 430 is a dielectric material. In this embodiment, the gate dielectric material layer 430 is a stacked structure. As an example, the gate dielectric material layer 430 is an ONO (Oxide-Nitride-Oxide) structure, and the gate dielectric material layer 430 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0194] In other embodiments, according to actual process requirements, the gate dielectric material layer may also be other suitable materials, and the gate dielectric material layer may also be a single-layer structure.

[0195] refer to Fig.21 , patterning the control gate material layer 440 and the floating gate material layer 420, forming a plurality of control gates 530 extending in the row direction and arranged in the column direction on the cell array region C and the adjacent selection gate region S, and the remaining floating gate material layer 420 located at the bottom of the control gate 530 is used as a floating gate 510, and the floating gate 510 and the control gate 530 located on the floating gate 510 are used to form a gate structure 500.

[0196] When the NOR flash memory is working, programming is achieved by changing the electron injection into the floating gate 510 or erasing from the floating gate 510 through the control gate 530.

[0197] When the NOR flash memory is working, the floating gate 510 can capture and store electrons, and after power failure, the electrons stored in the floating gate 510 will not be lost. The amount of charge stored in the floating gate 510 can change the on-voltage of the field effect transistor, and different on-voltages can represent different states, thereby realizing information storage.

[0198] In this embodiment, the step of patterning the control gate material layer 440 and the floating gate material layer 420 includes: forming a plurality of mask layers (not shown) extending in the row direction and arranged at intervals in the column direction on the control gate material layer 440 on the cell array region C and the adjacent selection gate region S; and patterning the control gate material layer 440 and the floating gate material layer 420 using the mask layer as a mask.

[0199] In this embodiment, an anisotropic dry etching process is used to pattern the control gate material layer 440 and the floating gate material layer 420 using the mask layer as a mask. The anisotropic dry etching process has anisotropic etching characteristics, which can achieve high profile controllability and pattern transfer accuracy, and is correspondingly conducive to making the morphology and size of the control gate 530 and the floating gate 510 meet the process requirements.

[0200] In this embodiment, after the control gate material layer 440 and the floating gate material layer 420 are patterned, the control gate 530 is a strip-shaped structure extending along the row direction, and the floating gate 510 is an island-shaped structure.

[0201] In this embodiment, in the step of patterning the control gate material layer 440 and the floating gate material layer 420 , the gate dielectric material layer 430 is also patterned, and the remaining gate dielectric material layer 430 is used as an inter-gate dielectric (IPD) layer 520 .

[0202] Specifically, the inter-gate dielectric layer 520 is located in the cell array region C, and is used to isolate the control gate 530 from the floating gate 510 , and is also used to isolate the control gate 530 from the substrate 100 .

[0203] The inter-gate dielectric layer 520 is also a stacked structure. Specifically, the inter-gate dielectric layer 190 is an ONO structure.

[0204] Therefore, the gate structure 500 located in the cell array region C further includes an inter-gate dielectric layer 520 .

[0205] In the selection gate region S, there is no isolation between the floating gate 510 and the control gate 530, and the floating gate 510 and the control gate 530 can be in contact with each other. The floating gate 510 and the control gate 530 located in the selection gate region S are used to form the gate of the selection gate MOS.

[0206] Correspondingly, an embodiment of the present invention further provides a memory, comprising the semiconductor structure provided by an embodiment of the present invention.

[0207] As can be seen from the above description, the performance consistency between the memory cells in the semiconductor structure provided by the embodiment of the present invention is high, and the resistance of the first drain doping layer and the second drain doping layer is low. Accordingly, the performance of the memory including the semiconductor structure provided by the embodiment of the present invention is also improved.

[0208] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate including a plurality of discrete cell array regions for forming memory cells; A plurality of isolation structures extending in the column direction and arranged in the row direction, located in the substrate, wherein the top surface of the isolation structure in the cell array region is lower than the top surface of the substrate; A first drain doped layer is located on the sidewall of the substrate exposed along the second side of the row direction of the isolation structure; A second drain doped layer is located on the sidewall of the substrate exposed along the first side of the row direction of the isolation structure; A floating gate is located on a portion of the substrate between adjacent isolation structures in the cell array region, and the floating gates are arranged in a column direction with discrete intervals; A source region along the column direction is located in the substrate between adjacent floating gates in the cell array region; The first drain doping layer and the second drain doping layer include epitaxial layers doped with ions, and the first drain doping layer and the second drain doping layer further extend toward the inside of the substrate at the bottom of the floating gate along the channel extension direction.

2. The semiconductor structure according to claim 1, wherein: The first drain doping layer is recessed in the side wall of the substrate, and the second drain doping layer is recessed in the side wall of the substrate.

3. The semiconductor structure according to claim 2, wherein: Along a direction perpendicular to the side wall of the substrate, the first drain doping layer or the second drain doping layer is recessed into the side wall of the substrate to a depth of 1 nm to 10 nm.

4. The semiconductor structure according to claim 1, wherein: Along a direction perpendicular to the top surface of the substrate, a distance between a top surface of the isolation structure in the cell array region and the top surface of the substrate is 2 nm to 20 nm.

5. The semiconductor structure according to claim 1, wherein: The substrate further includes a selection gate region located between the cell array regions along the column direction, a first transition region located between the cell array region and a selection gate region adjacent to one side of the cell array region along the column direction, and a second transition region located between the cell array region and a selection gate region adjacent to the other side of the cell array region along the column direction; The isolation structure comprises a main extension located in the cell array region, a first offset extension located in the selection gate region adjacent to one side of the cell array region, and a second offset extension located in the selection gate region adjacent to the other side of the cell array region; the main extension, the first offset extension, and the second offset extension extend in a column direction, the first offset extension is offset toward a first side relative to the main extension in a row direction, and the second offset extension is offset toward a second side relative to the main extension in a row direction; the isolation structure further comprises a first transition extension located between the first offset extension and the main extension, and a second transition extension located between the second offset extension and the main extension, the first transition extension is formed on the first transition region, and the second transition extension is formed on the second transition region; The first transition extension and the adjacent part of the first offset extension further expose a part of the height sidewall of the substrate along the second side of the row direction, and cover the sidewall of the substrate along the first side of the row direction; the second transition extension and the adjacent part of the second offset extension further expose a part of the height sidewall of the substrate along the first side of the row direction, and cover the sidewall of the substrate along the second side of the row direction; The first drain doped layer is located on the substrate sidewalls of the main extension portion, the first transition extension portion, and the adjacent portion of the first offset extension portion exposed along the second side in the row direction, and the second drain doped layer is located on the substrate sidewalls of the main extension portion, the second transition extension portion, and the adjacent portion of the second offset extension portion exposed along the first side in the row direction; The source region penetrates the cell array region, the adjacent first transition region and the second transition region, and a portion of the selection gate region along a column direction.

6. The semiconductor structure according to claim 5, characterized in that The isolation structure further includes a secondary extension portion located in the selection gate region, extending along the column direction and arranged in a row direction with the first offset extension portion or the second offset extension portion, and the secondary extension portion covers the side wall of the substrate.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a filling dielectric layer, which is located on the isolation structure and covers the sidewalls of the first drain-doped layer and the second drain-doped layer, wherein the top surface of the filling dielectric layer is flush with the top surface of the substrate; A plurality of control gates extending in the row direction and arranged at intervals in the column direction cover the floating gates, as well as the substrate and the filling dielectric layer between the floating gates in the row direction.

8. The semiconductor structure according to claim 7, wherein: The semiconductor structure further includes: a tunneling oxide layer located between the floating gate and the substrate; The inter-gate dielectric layer is located between the floating gate and the control gate in the cell array region.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate including a plurality of discrete cell array regions for forming memory cells; forming a plurality of grooves penetrating a portion of the thickness of the substrate, wherein the grooves extend in a column direction and are arranged in a row direction; forming an isolation structure in the trench, wherein a top surface of the isolation structure in the cell array region is lower than a top surface of the substrate; Using an epitaxial process, a first drain doping layer is formed on a substrate sidewall exposed along the second side of the isolation structure in the row direction, and a second drain doping layer is formed on a substrate sidewall exposed along the first side of the isolation structure in the row direction; forming a floating gate material layer on the substrate between the isolation structures; Forming a source region opening along the column direction in the floating gate material layer, wherein the source region opening penetrates the cell array region along the column direction, and a floating gate material layer with a partial width is retained on both sides of the source region opening; A source region is formed in the substrate at the bottom of the source region opening.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for forming the semiconductor structure further comprises: after forming the isolation structure and before forming the first drain doping layer and the second drain doping layer, forming a sidewall groove in a substrate sidewall exposed by the isolation structure; The first drain doping layer is formed in the sidewall groove of the isolation structure along the second side in the row direction, and the second drain doping layer is formed in the sidewall groove of the isolation structure along the first side in the row direction.

11. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming a sidewall groove in the substrate sidewall exposed by the isolation structure comprises: Performing oxidation treatment on the exposed side wall of the substrate of the isolation structure, so that the partial thickness material of the exposed side wall of the substrate of the isolation structure is converted into a sacrificial oxide layer; removing the sacrificial oxide layer to form the side wall groove; Alternatively, an isotropic etching process is used to etch the exposed sidewall of the substrate of the isolation structure to form the sidewall groove.

12. The method for forming a semiconductor structure according to claim 11, wherein: Using a thermal oxidation process, oxidizing the sidewall of the substrate exposed by the isolation structure; The sacrificial oxide layer is removed by a wet etching process.

13. The method for forming a semiconductor structure according to claim 11, wherein: The isotropic etching process includes a remote plasma etching process or a wet etching process.

14. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the groove comprises: forming a hard mask layer on the substrate, wherein a plurality of mask openings are formed in the hard mask layer; using the hard mask layer as a mask, removing a portion of the substrate exposed by the mask openings to form the groove; After forming the first drain doping layer and the second drain doping layer and before forming the floating gate material layer, the forming method further includes: removing the hard mask layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the semiconductor structure further comprises: after forming the first drain doping layer and the second drain doping layer and before removing the hard mask layer, forming a filling dielectric layer filling the trench and the mask opening on the isolation structure; In the step of removing the hard mask layer, the filling dielectric layer and the substrate form a floating gate opening; The step of forming the floating gate material layer includes: filling the floating gate material layer in the floating gate opening; After forming the source region, the method for forming the semiconductor structure includes: removing a portion of the thickness of the filling dielectric layer so that the top surface of the remaining filling dielectric layer is flush with the top surface of the substrate.

16. The method for forming a semiconductor structure according to claim 15, wherein: After removing a portion of the thickness of the filling dielectric layer, the method for forming the semiconductor structure further includes: forming a control gate material layer covering the floating gate material layer, the filling dielectric layer and the substrate; patterning the control gate material layer and the floating gate material layer, and forming a plurality of control gates extending in the row direction and arranged in the column direction on the cell array region and the adjacent selection gate region, the remaining floating gate material layer located at the bottom of the control gate is used as a floating gate, and the floating gate and the control gate located on the floating gate are used to constitute a gate structure.

17. The method for forming a semiconductor structure according to claim 9, wherein: The substrate further includes a selection gate region located between the cell array regions along the column direction, a first transition region located between the cell array region and a selection gate region adjacent to one side of the cell array region along the column direction, and a second transition region located between the cell array region and a selection gate region adjacent to the other side of the cell array region along the column direction; In the step of forming the isolation structure, the isolation structure includes a main extension located in the cell array region, a first offset extension located in the selection gate region adjacent to one side of the cell array region, and a second offset extension located in the selection gate region adjacent to the other side of the cell array region; the main extension, the first offset extension, and the second offset extension extend in a column direction, the first offset extension is offset toward a first side relative to the main extension in a row direction, and the second offset extension is offset toward a second side relative to the main extension in a row direction; the isolation structure also includes a first transition extension located between the first offset extension and the main extension, and a second transition extension located between the second offset extension and the main extension, the first transition extension is formed on the first transition region, and the second transition extension is formed on the second transition region; The first transition extension and the adjacent part of the first offset extension further expose a part of the height sidewall of the substrate along the second side of the row direction, and cover the sidewall of the substrate along the first side of the row direction; the second transition extension and the adjacent part of the second offset extension further expose a part of the height sidewall of the substrate along the first side of the row direction, and cover the sidewall of the substrate along the second side of the row direction; The first drain doped layer is formed on the substrate sidewalls of the main extension portion, the first transition extension portion, and the adjacent portion of the first offset extension portion exposed along the second side in the row direction, and the second drain doped layer is formed on the substrate sidewalls of the main extension portion, the second transition extension portion, and the adjacent portion of the second offset extension portion exposed along the first side in the row direction; In the step of forming a source region opening extending in the column direction in the floating gate material layer, the source region opening passes through the cell array region, the adjacent first transition region and the second transition region, and a portion of the selection gate region in the column direction.

18. The method for forming a semiconductor structure according to claim 17, wherein: In the step of forming the isolation structure, the isolation structure further includes a secondary extension portion located in the selection gate region, extending along the column direction and arranged in a row direction with the first offset extension portion or the second offset extension portion, and the secondary extension portion covers the side wall of the substrate.

19. A memory, characterized in that: include: A semiconductor structure as claimed in any one of claims 1 to 8.

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