Display device

Abstract

In a high-definition display device, narrow bezel implementation is provided. The display device includes: a display area; a bezel area surrounding the display area; a plurality of pixel circuits disposed in the display area; peripheral circuits disposed in the bezel area; and wirings connecting the pixel circuits and the peripheral circuits. The peripheral circuits include: a plurality of switch circuits disposed along a direction away from the display area; a plurality of relay electrodes disposed between the display area and the plurality of switch circuits; and a plurality of connection wirings respectively connecting the plurality of relay electrodes and the plurality of switch circuits. The plurality of relay electrodes are connected to the wirings, and one of the plurality of connection wirings connecting one of the plurality of switch circuits and one of the plurality of relay electrodes crosses other switch circuits in a top view.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor. Background Art

[0002] Recently, transistors using an oxide semiconductor for a channel are being developed as an alternative to amorphous silicon, low-temperature polycrystalline silicon, and single-crystalline silicon. A transistor using an oxide semiconductor for a channel has a simple structure and is formed by a low-temperature process, like a transistor using amorphous silicon for a channel. It is known that a transistor using an oxide semiconductor for a channel has a higher mobility and a very low off-current than a transistor using amorphous silicon for a channel.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-146819

[0004] Patent Document 2: Japanese Patent Application Laid-Open No. 2015-159315

[0005] On the other hand, in a display device such as a head-mounted display, a high-definition display with an increased number of pixels is desired. If the number of pixels increases (high definition), the number of wirings of peripheral circuits and terminal portions for driving pixels increases in the border area. Therefore, in the border area, the occupied area of the wirings increases, and it is difficult to achieve a narrow border. Summary of the Invention

[0006] In view of the above problems, one object of an embodiment of the present invention is to provide a narrow border in a high-definition display device.

[0007] The display device according to one embodiment of the present invention includes: a display area; a border area surrounding the periphery of the display area; a plurality of pixel circuits provided in the display area; a peripheral circuit provided in the border area; and wirings connecting the pixel circuits and the peripheral circuit. The peripheral circuit includes: a plurality of switch circuits provided along a direction away from the display area; a plurality of relay electrodes provided between the display area and the plurality of switch circuits; and a plurality of connection wirings respectively connecting the plurality of relay electrodes and the plurality of switch circuits. The plurality of relay electrodes are connected to the wirings, and one of the plurality of connection wirings connecting one of the plurality of switch circuits and one of the plurality of relay electrodes crosses other switch circuits in a plan view. Brief Description of the Drawings

[0008] Figure 1 It is a plan view showing an outline of a display device according to one embodiment of the present invention.

[0009] Figure 2 It is a block diagram showing a circuit structure of a display device according to one embodiment of the present invention.

[0010] Figure 3 It is a circuit diagram of a pixel circuit of a pixel of a display device according to an embodiment of the present invention.

[0011] Figure 4 It is a cross-sectional view showing the structure of a display device according to an embodiment of the present invention.

[0012] Figure 5 It is a layout of pixels of a display device according to an embodiment of the present invention.

[0013] Figure 6 It is a block diagram for explaining a gate driving circuit of a display device according to an embodiment of the present invention.

[0014] Figure 7 It is an example of a circuit diagram of a switching circuit.

[0015] Figure 8 It is an example of a layout of peripheral circuits of a display device according to an embodiment of the present invention.

[0016] Figure 9 It is for Figure 8 a diagram for explaining the layout of the gate electrode and the semiconductor layer of the switching circuit shown.

[0017] Figure 10 It is an example of a layout of peripheral circuits of a display device according to an embodiment of the present invention.

[0018] Figure 11 It is an example of a layout of peripheral circuits of a display device according to an embodiment of the present invention.

[0019] Figure 12 It is for Figure 11 a diagram for explaining the layout of the second intermediate electrode and the transparent intermediate electrode shown.

[0020] Figure 13 It is an example of a layout of peripheral circuits of a display device according to an embodiment of the present invention.

[0021] Figure 14 It is a cross-sectional view when cutting along the A1 - A2 line of Figure 13

[0022] Figure 15 It is an example of a layout of a terminal portion of a display device according to an embodiment of the present invention.

[0023] Figure 16 It is a cross-sectional view when cutting along the B1 - B2 line of Figure 15 Detailed implementation manners

[0024] Hereinafter, each embodiment of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Structures that those skilled in the art can easily conceive by maintaining the gist of the invention and appropriately changing the structure of the embodiment are of course included in the scope of the present invention. For the sake of clarity in the description, the drawings sometimes schematically show the width, thickness, shape, etc. of each part compared with the actual manner. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each figure, sometimes for the figures that have already appeared, for the structures with the same structure as the foregoing content, letters are added after the same reference numerals, and the detailed description is appropriately omitted.

[0025] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. In this way, for the convenience of description, words such as above or below are used for description. However, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer can also be arranged in an orientation different from that shown in the figure. In the following description, for example, an expression such as an oxide semiconductor layer on a substrate is merely to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be arranged between the substrate and the oxide semiconductor layer. Above or below means being located on the upper side or the lower side in a structure in which multiple layers are stacked, and it is not required to be in an overlapping relationship with each other in a top view.

[0026] "Display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" sometimes also refers to a display panel including an electro-optical layer, or sometimes also refers to a structure in which other optical components (such as a polarization component, a backlight, a touch panel, etc.) are assembled with respect to the display unit. "Electro-optical layer" may include a liquid crystal layer, an electroluminescence (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer as long as there is no technical contradiction. Therefore, for the embodiments described later, as a display device, a liquid crystal display device including a liquid crystal layer is illustrated for description, but the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0027] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C as long as there is no special indication. And these expressions do not exclude the case where α includes other elements either.

[0028] It should be noted that the following embodiments can be combined with each other as long as there is no technical contradiction.

[0029] [First Embodiment]

[0030] [1. Outline of the display device 10]

[0031] Refer to Figures 1 to 3 , and the outline of the display device 10 according to an embodiment of the present invention will be described. Figure 1 is a plan view showing the outline of the display device 10 according to an embodiment of the present invention. As Figure 1 shown, the display device 10 includes an array substrate 300, a sealing portion 400, a counter substrate 500, a flexible printed circuit board 600 (FPC600), and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded by the sealing portion 400. Liquid crystal is filled in the display area 22 surrounded by the sealing portion 400, and a plurality of pixels 310 are arranged in a matrix along the first direction D1 (row direction) and the second direction D2 (column direction) intersecting the first direction D1. The plurality of pixels 310 include red pixels R, green pixels G, and blue pixels B. The first direction D1 and the second direction D2 may be orthogonal. The display area 22 is an area that overlaps with a liquid crystal element 410 described later in a plan view.

[0032] The sealing portion area 24 provided with the sealing portion 400 is provided in the frame area 28 surrounding the display area 22. The FPC600 is connected to the terminal area 26. The terminal area 26 is provided in the area where the array substrate 300 in the frame area 28 is exposed from the counter substrate 500, and is provided outside the sealing portion area 24. It should be noted that the outside of the sealing portion area 24 refers to the outside of the area surrounded by the sealing portion 400 in the frame area 28. The IC chip 700 is provided on the FPC600. The IC chip 700 supplies signals for driving the pixel circuits 350 of the respective pixels 310 (refer to Figure 2 ).

[0033] [2. Circuit structure of the display device 10]

[0034] Figure 2 is a block diagram showing the circuit structure of the display device 10 according to an embodiment of the present invention. As Figure 2 shown, a gate driving circuit 330 is provided at a position adjacent to the display area 22 in the first direction D1 where the pixel circuits 350 of the pixels 310 are arranged, and a source driving circuit 320 is provided at a position adjacent to the display area 22 in the second direction D2. The gate driving circuit 330 and the source driving circuit 320 are provided in the above-mentioned frame area 28.

[0035] The gate wiring 331 extends from the gate driving circuit 330 along the first direction D1 and is connected to the pixel circuits 350 of the plurality of pixels 310 arranged in the first direction D1. The source wiring 321 extends from the source driving circuit 320 along the second direction D2 and is connected to the pixel circuits 350 of the plurality of pixels 310 arranged in the second direction D2.

[0036] A plurality of terminal portions 333 are provided in the terminal region 26. The structure of the terminal portion 333 will be described in detail later. The plurality of terminal portions 333 are respectively connected to the source driving circuit 320 through the connection wirings 341. Similarly, the terminal portion 333 is connected to the gate driving circuit 330 through the connection wiring 341. The FPC 600 is connected to the terminal portion 333, so that the source driving circuit 320 and the gate driving circuit 330 are connected to the IC chip 700. The IC chip controls the source driving circuit 320 and the gate driving circuit 330 based on an input signal from an external device. As a result, the pixel circuits 350 included in the respective pixels 310 in the display region 22 are driven.

[0037] [3. Pixel Circuit 350 of Pixel 310 of Display Device 10]

[0038] Figure 3 is a circuit diagram showing the pixel circuit 350 of the pixel 310 of the display device 10 according to an embodiment of the present invention. As Figure 3 shown, the pixel circuit 350 includes elements such as a pixel transistor (pixel switch) 800, a holding capacitor 890, and a liquid crystal element 410. Details will be described later, but one electrode of the holding capacitor 890 is the pixel electrode PTCO2, and the other electrode includes a common electrode CTCO2. Similarly, one electrode of the liquid crystal element 410 is the pixel electrode PTCO2, and the other electrode is the common electrode CTCO2. A common potential VCOM is supplied to the common electrode CTCO2. The pixel transistor 800 has a gate electrode 810, a source electrode 830, and a drain electrode 840. The gate electrode 810 is connected to the gate wiring 331. The source electrode 830 is connected to the source wiring 321. The drain electrode 840 is connected to the holding capacitor 890 and the liquid crystal element 410. It should be noted that in the present embodiment, for convenience of explanation, 830 refers to the source electrode and 840 refers to the drain electrode, but the functions of the source electrode and the drain electrode as electrodes can also be interchanged.

[0039] [4. Structure of Display Device 10]

[0040] Refer to Figure 4 and Figure 5 , and the details of the structure of the display device 10 according to an embodiment of the present invention will be described. Figure 4 is a cross-sectional view showing the structure of the display device 10 according to an embodiment of the present invention.Figure 5 This is the layout of the pixels of the display device 10 according to an embodiment of the present invention. It should be noted that Figure 4 The cross-sectional view is a typical cross-sectional view for briefly explaining the layer structure of the display device 10, showing the peripheral circuit adjacent to the pixel circuit 350. In fact, the pixel circuit 350 is within the display area 22, and the peripheral circuit is provided in the border area 28 outside the display area 22. It goes without saying that the pixel circuit 350 and the peripheral circuit are separately arranged. In particular, in Figure 4 the pixel circuit 350 in, it is shown centered on the peripheral part of the contact hole in the pixel area, and only a part of the transmissive area (opening area) contributing to display is shown. In addition, Figure 4 in, what is shown as the peripheral circuit is a typical example showing around the transistors provided in the source driver circuit 320 and the gate driver circuit 330, and what is shown as the pixel circuit 350 is a typical example showing around the pixel transistors within the pixel circuit 350.

[0041] As Figure 4 shown, the display device 10 has a substrate SUB. In addition, the display device 10 has a transistor Tr1, a transistor Tr2, wirings W1, W2, connection electrodes ZTCO1, ZTCO2, a transparent conductive layer PTCO1, a pixel electrode PTCO2, common auxiliary electrodes CMTL1, CMTL2, a transparent conductive layer CTCO1, and a common electrode CTCO2 above the substrate SUB. It should be noted that TCO is an abbreviation for Transparent Conductive Oxide. The transistor Tr1 is a transistor included in a peripheral circuit such as the source driver circuit 320 or the gate driver circuit 330. The transistor Tr2 is a transistor included in the pixel circuit 350 of the pixel 310 of the display device 10.

[0042] [5. Structure of Peripheral Circuit]

[0043] In the peripheral circuit, at least the transistor Tr1 has a p-type transistor Tr1-1 and an n-type transistor Tr1-2.

[0044] Both the n-type transistor Tr1-1 and the p-type transistor Tr1-2 have a gate wiring GL1, a gate insulating layer GI1, and a semiconductor layer S. The gate wiring GL1 faces the semiconductor layer S. The gate insulating layer GI1 is provided between the semiconductor layer S and the gate wiring GL1. In the present embodiment, a bottom-gate transistor in which the gate wiring GL1 is provided on the substrate SUB side with respect to the semiconductor layer S is illustrated, but a top-gate transistor in which the positional relationship between the semiconductor layer S and the gate wiring GL1 is reversed may also be used.

[0045] The semiconductor layer S of the p-type transistor Tr1-2 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr1-1 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is the semiconductor layer in the region that overlaps with the gate wiring GL1 in a top view. The semiconductor layer S1 functions as the channel of the transistor Tr1-1. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer with a higher resistance than the semiconductor layer S2. In addition, sometimes in the gate wiring GL1, the region overlapping with the semiconductor layer S is called the gate electrode. The semiconductor layer S3 suppresses hot carrier degradation by attenuating the hot carriers that invade the semiconductor layer S1.

[0046] An insulating layer IL1 and a gate insulating layer GI2 are provided on the semiconductor layer S. In the transistor Tr1, the gate insulating layer GI2 functions only as an interlayer film. A wiring W1 is provided on these insulating layers. The wiring W1 is connected to the semiconductor layer S through an opening provided in the insulating layer IL1 and the gate insulating layer GI2. An insulating layer IL2 is provided on the wiring W1. A wiring W2 is provided on the insulating layer IL2. The wiring W2 is connected to the wiring W1 through an opening provided in the insulating layer IL2.

[0047] The gate wiring GL1 and the light-shielding layer LS2 are the same layer. The wiring W1 and the gate wiring GL2 are the same layer. Hereinafter, the same layer or the same layer means that multiple components are formed by patterning one layer.

[0048] An insulating layer IL2 is provided on the wiring W1. A wiring W2 is provided on the insulating layer IL2. The wiring W2 is connected to the wiring W1 via a contact hole provided in the insulating layer IL2. An insulating layer IL3 is provided on the insulating layer IL2 and the wiring W2. A connection electrode ZTCO1 is provided on the insulating layer IL3. The connection electrode ZTCO1 is connected to the wiring W2 via a contact hole provided in the insulating layer IL3. The connection electrode ZTCO1 is a transparent conductive layer. An insulating layer IL4 is provided on the insulating layer IL3 and the connection electrode ZTCO1. The insulating layer IL4 alleviates a step formed by a structure disposed on a layer lower than the insulating layer IL4. A transparent conductive layer PTCO1 is provided on the insulating layer IL4. The transparent conductive layer PTCO1 is connected to the connection electrode ZTCO1 via a contact hole provided in the insulating layer IL4. An insulating layer IL5 is provided on the insulating layer IL4 and the transparent conductive layer PTCO1. A common auxiliary electrode CMTL1 is provided on the insulating layer IL5. The common auxiliary electrode CMTL1 is connected to the transparent conductive layer PTCO1 via a contact hole provided in the insulating layer IL5. A transparent conductive layer CTCO1 is provided on the common auxiliary electrode CMTL1. The wiring W1 is connected to the transparent conductive layer CTCO1 via the wiring W2, the connection electrode ZTCO1, the transparent conductive layer PTCO1, and the common auxiliary electrode CMTL1. Regarding the connection electrode ZTCO1, the transparent conductive layer PTCO1, the common auxiliary electrode CMTL1, and the transparent conductive layer CTCO1, Figure 7 will be described in detail below.

[0049] [6. Structure of Pixel Circuit 350]

[0050] Next, with reference to Figure 4 and Figure 5 , the structure of the pixel circuit 350 will be described. The transistor Tr2 has an oxide semiconductor layer OS, a gate insulating layer GI2, and a gate wiring GL2. The gate wiring GL2 faces the oxide semiconductor layer OS. The gate insulating layer GI2 is provided between the oxide semiconductor layer OS and the gate wiring GL2. In the present embodiment, a top-gate transistor in which the oxide semiconductor layer OS is provided on the substrate SUB side with respect to the gate wiring GL2 is illustrated, but a bottom-gate transistor in which the positional relationship between the gate wiring GL2 and the oxide semiconductor layer OS is reversed may also be used. It should be noted that Figure 5 in, the layout of the insulating layer IL5, the common auxiliary electrode CMTL2, and the common electrode CTCO2 is omitted from the drawing.

[0051] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 is a region that overlaps with the gate wiring GL2 in a plan view. The oxide semiconductor layer OS1 functions as a semiconductor layer and switches between a conductive state and a non-conductive state according to the voltage supplied to the gate wiring GL2. In other words, the oxide semiconductor layer OS1 functions as the channel of the transistor Tr2. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are formed of the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is a region that is made to have a low resistance by doping impurities into a layer having the same physical properties as the oxide semiconductor layer OS1.

[0052] An insulating layer IL2 is provided on the gate wiring GL2. A wiring W2 is provided on the insulating layer IL2. The wiring W2 is connected to the oxide semiconductor layer OS2 through an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI2. A data signal related to the gray level of a pixel is transmitted to the wiring W2. The wiring W2 functions as one of a source electrode or a drain electrode. An insulating layer IL3 is provided on the insulating layer IL2 and the wiring W2. A connection electrode ZTCO2 is provided on the insulating layer IL3. The connection electrode ZTCO2 is connected to the oxide semiconductor layer OS2 through an opening ZCON provided in the insulating layers IL3, IL2, and the gate insulating layer GI2. The connection electrode ZTCO2 functions as the other of a source electrode or a drain electrode. The connection electrode ZTCO2 abuts on the oxide semiconductor layer OS2 at the bottom of the opening ZCON. The connection electrode ZTCO2 is a transparent conductive layer.

[0053] Here, for example, when a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized by process gases and oxygen ions during ITO film formation. The oxide layer formed on the surface of the semiconductor layer has a high resistance, and thus the contact resistance between the semiconductor layer and the transparent conductive layer becomes high. As a result, poor electrical contact occurs between the semiconductor layer and the transparent conductive layer. On the other hand, even when the above-mentioned transparent conductive layer is formed in contact with the oxide semiconductor layer, no high-resistance oxide layer as described above is formed on the surface of the oxide semiconductor layer. Therefore, no poor electrical contact occurs between the oxide semiconductor layer and the transparent conductive layer.

[0054] An insulating layer IL4 is provided on the connection electrode ZTCO2. The insulating layer IL4 is sometimes referred to as a planarization film. A pixel electrode PTCO2 is provided on the insulating layer IL4. The pixel electrode PTCO2 is connected to the connection electrode ZTCO2 through an opening PCON provided in the insulating layer IL4. The pixel electrode PTCO2 is a transparent conductive layer.

[0055] An insulating layer IL5 is provided on the pixel electrode PTCO2. A common auxiliary electrode CMTL2 and a common electrode CTCO2 are provided on the insulating layer IL5. Although details will be described later, the common auxiliary electrode CMTL2 and the common electrode CTCO2 have different planar patterns. The common auxiliary electrode CMTL2 is a metal layer. The common electrode CTCO2 is a transparent conductive layer. The resistance of the common auxiliary electrode CMTL2 is lower than the resistance of the common electrode CTCO2. In addition, the common auxiliary electrode CMTL2 also functions as a light-shielding layer, for example, suppressing color mixing by shielding light from adjacent pixels. A spacer SP is provided on the common electrode CTCO2.

[0056] The spacer SP is provided for a part of the pixels. For example, the spacer SP may be provided for any one of the red pixels, green pixels, and blue pixels. Among them, the spacer SP may also be provided for all the pixels. The height of the spacer SP is half the height of the cell gap. A spacer is also provided on the counter substrate, and the spacer on the counter substrate overlaps with the above-mentioned spacer SP in a top view.

[0057] It should be noted that the spacer SP can not only adopt such a structure, but also adopt a structure having a height equivalent to the cell gap, and can also adopt a structure that only fills the second contact area CON2.

[0058] A light-shielding layer LS is provided between the transistor Tr2 and the substrate SUB. In the present embodiment, light-shielding layers LS1 and LS2 are provided as the light-shielding layer LS. However, the light-shielding layer LS may also be formed only by the light-shielding layer LS1 or only by the light-shielding layer LS2. In a top view, the light-shielding layer LS is provided in a region where the gate wiring GL2 overlaps with the oxide semiconductor layer OS. In other words, in a top view, the light-shielding layer LS is provided in a region that overlaps with the oxide semiconductor layer OS1. The light-shielding layer LS suppresses light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1. When a conductive layer is used as the light-shielding layer LS, a voltage can be applied to the light-shielding layer LS to control the oxide semiconductor layer OS1. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate wiring GL2 can be connected through the border region 28. In a top view, the above-mentioned first contact area CON1 is provided in a region that does not overlap with the light-shielding layer LS.

[0059] [7. Materials of the components of the display device 10]

[0060] As the substrate SUB, a rigid substrate such as a glass substrate, a quartz substrate, or a sapphire substrate that has translucency and does not have flexibility can be used. On the other hand, when the substrate SUB needs to have flexibility, as the substrate SUB, a flexible substrate such as a polyimide substrate, an acrylic substrate, a silicone substrate, or a fluororesin substrate that contains resin and has flexibility can be used. Impurities may also be introduced into the above resin in order to improve the heat resistance of the substrate SUB.

[0061] As the gate wirings GL1 and GL2, the wirings W1 and W2, the light-shielding layer LS, and the common auxiliary electrodes CMTL1 and CMTL2, a metal material can be used. For example, as the metal material, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), or silver (Ag), or an alloy or compound thereof is used. As the above components, the above metal material can be used as a single layer or can be used in a stacked manner. For example, as the gate wiring GL2, a stacked structure of Ti / Al / Ti is used. In the present embodiment, the cross-sectional shape of the pattern end portion of the gate wiring GL2 having the above stacked structure is a regular conical shape.

[0062] As the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL5, a general insulating material can be used. For example, as the insulating layers IL1 to IL3 and IL5, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum oxynitride (AlN x O y ), or aluminum nitride (AlN x ) and other inorganic insulating layers can be used. As these insulating layers, an insulating layer with few defects can be used. As the insulating layer IL4, an organic insulating material such as a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluororesin, or a silicone resin can be used. It should be noted that as the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL3 and IL5, the above organic insulating materials can be used. As the above components, the above materials can be used as a single layer or can be used in a stacked manner.

[0063] It should be noted that as an example of the above insulating layer, SiO with a thickness of 100 nm is used. x, as the gate insulating layer GI1. In addition, SiO with a total thickness of 600 nm to 700 nm is used. x / SiN x / SiO x , as the insulating layer IL1. SiO with a total thickness of 60 to 100 nm is used. x / SiN x , as the gate insulating layer GI2. SiO with a total thickness of 300 nm to 500 nm is used. x / SiN x / SiO x , as the insulating layer IL2. SiO with a total thickness of 200 nm to 500 nm is used. x (single layer), SiN x (single layer) or a stack of these is used as the insulating layer IL3. An organic layer with a thickness of 2 μm to 4 μm is used as the insulating layer IL4. SiN with a thickness of 50 nm to 150 nm is used as the insulating layer IL5. x (single layer), as the insulating layer IL5.

[0064] The above-mentioned SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). In addition, SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0065] As the oxide semiconductor layer OS, an oxide semiconductor having semiconductor characteristics can be used. The oxide semiconductor layer OS has light transmittance. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a different composition from the above can also be used. For example, the ratio of In can be made larger than the above in order to increase the mobility. In addition, the ratio of Ga can be made larger than the above in order to increase the bandgap and reduce the influence of light irradiation.

[0066] Other elements may also be added to the oxide semiconductor containing In, Ga, Zn, and O. For example, metal elements such as Al or Sn may also be added to the oxide semiconductor. It may also be that, in addition to the above-mentioned oxide semiconductor, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), or an oxide semiconductor containing In and W, etc. is used as the oxide semiconductor layer OS. The oxide semiconductor layer OS may be amorphous, may be crystalline, or may be a mixed phase of amorphous and crystalline.

[0067] A transparent conductive material is used as the connection electrodes ZTCO1, ZTCO2, the transparent conductive layer PTCO1, the pixel electrode PTCO2, the transparent conductive layer CTCO1, and the common electrode CTCO2. The transparent conductive layer PTCO1 and the pixel electrode PTCO2 are formed of the same film. In addition, the transparent conductive layer CTCO1 and the common electrode CTCO2 are formed of the same film. As the transparent conductive material, a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO), etc. can be used. As the transparent conductive material, materials other than the above can also be used.

[0068] [8. Structure of Peripheral Circuit]

[0069] Next, as an example of the peripheral circuit, refer to Figures 6 to 14 to describe the structure of the gate drive circuit 330. Figure 6 is a block diagram for describing the structure of the gate drive circuit 330. Figure 6 In this, the gate drive circuit 330 has a plurality of units each composed of at least a shift register SR and first to fourth switch circuits BR1 to BR4. The first to fourth switch circuits BR1 to BR4 are respectively connected to the gate wirings 331-1 to 331-4 via connection wirings 250-1 to 250-4 and relay electrodes 202-5 to 202-8. The gate wirings 331-1 to 331-8 are respectively connected to the gate wirings GL2 of the transistors Tr2 in the display area 22.

[0070] The switch circuit BR is driven based on the signal output from the shift register SR, and a gate signal GATE including a pulse wave is supplied to the gate wiring 331 via the relay electrode 202 from the switch circuit BR. Through the gate signal GATE, the on-state or off-state of each transistor Tr2 is controlled.

[0071] Figure 7This is an example of the circuit diagram of the switch circuit BR. In the following description, the switch circuit BR is described without separately distinguishing the first switch circuit BR1 to the fourth switch circuit BR4. In addition, the structural elements of the first switch circuit BR1 to the fourth switch circuit BR4 are the same.

[0072] As Figure 7 shown, the switch circuit BR includes: a first switch unit SW1 and a second switch unit SW2 that receive inputs from the shift register SR. The inputs to the first switch unit SW1 and the second switch unit SW2 are complementary to each other. For example, when a high signal is input to the first switch unit SW1 as the first input signal input1, a low signal is simultaneously input to the second switch unit SW2 as the second input signal input2. Alternatively, in the first switch unit SW1 and the second switch unit SW2, the input of the first input signal input1 and the second input signal input2 can be interchanged.

[0073] The first switch unit SW1 includes an n-type first transistor Tr1-1n and a p-type second transistor Tr1-2p to which the first input signal input1 is input. In addition, the second switch unit SW2 includes: an n-type third transistor Tr1-3n to which the second input signal input2 is input. In addition, in each of the first switch circuit BR1 to the fourth switch circuit BR4, the first switch units SW1 are connected to each other, and the second switch units SW2 are connected to each other. Their connection relationship will be described later.

[0074] In a high-definition display device that reduces the size of pixels relative to the display area 22 to increase the number of pixels, the number of pixel rows also increases significantly. As a result, when the switch circuits SW that supply potential to the gate wirings for each pixel row are simply arranged in the second direction D2, the length of the gate drive circuit in the second direction D2 becomes significantly larger than the length of the display area 22 in the second direction D2. Therefore, in the display device according to an embodiment of the present invention, four switch circuits BR are arranged as a unit in the first direction D1, and such units are arranged in the second direction D2. In each unit, the first switch circuit BR1 to the fourth switch circuit BR4 are slightly offset in the second direction D2 and arranged in the first direction D1. In addition, only the first switch circuit BR1 is directly connected to the shift register SR in one unit, and the second switch circuit BR2 receives the output of the shift register SR through the first switch circuit BR1. In addition, the third switch circuit BR3 receives the output of the shift register SR through the first switch circuit BR1 and the second switch circuit BR2, and the fourth switch circuit BR4 receives the output of the shift register SR through the first switch circuit BR1, the second switch circuit BR2, and the third switch circuit BR3. By sequentially supplying the output from the shift register SR in this way, the four first switch circuits BR1 to BR4 in the unit are sequentially driven.

[0075] Hereinafter, Figures 8 to 14 the layout of the switch circuit BR will be described. Since the structures of the respective switch circuits BR are almost the same, in the following description, the structure of the first switch circuit BR1 will be mainly described.

[0076] It should be noted that, in the following description, the structure numbered 202-n indicates the same layer as the Figure 4 gate wiring GL1 in Figure 4 . In addition, the structure numbered 204-n indicates the same layer as the Figure 4 semiconductor layer S in Figure 4 . In addition, the structure numbered 206-n indicates a contact hole formed in the Figure 4 insulating layer IL1 and the gate insulating layer GI2 in Figure 4 . In addition, the structure numbered 208-n indicates the same layer as the Figure 4 gate wiring GL2 and the wiring W1 in Figure 4The connecting electrode ZTCO therein is on the same layer. In addition, the structure numbered 222-n represents a contact hole formed in the Figure 4 insulating layer IL4 therein. In addition, the structure numbered 224-n represents being on the same layer as the Figure 4 pixel electrode PTCO2 therein. In addition, the structure numbered 226-n represents a contact hole formed in the Figure 4 insulating layer IL5 therein. In addition, the structure numbered 228-n represents being on the same layer as the Figure 4 common auxiliary electrode CMTL2 therein. In addition, the structure numbered 232-n represents being on the same layer as the Figure 4 common electrode CTCO2 therein.

[0077] As Figure 8 well as Figure 9 shown, on the insulating surface of the substrate SUB, there are provided a conductive layer 202-1 that functions as a gate wiring of the first transistor Tr1-1n and the second transistor Tr1-2p, and a conductive layer 202-2 that functions as a gate wiring of the third transistor Tr1-3n. More specifically, the conductive layer 202-1 has a first gate electrode 202-11 of the first transistor Tr1-1n and a second gate electrode 202-12 of the second transistor Tr1-2p, and has a connection portion 202-13 that connects the first gate electrode 202-11 and the second gate electrode 202-12. Both the first gate electrode 202-11 and the second gate electrode 202-12 have a double-gate structure. In the first switching portion SW1, the connection portion 202-13 receives an input of a signal output from the shift register SR. In addition, the conductive layer 202-1 has a first connection line 202-14 connected to one of the second gate electrodes 202-12 having a double-gate structure, and the first connection line 202-14 is connected to the connection portion 202-13 of the first transistor Tr1-1n of the second switching circuit BR2. Such a connection relationship is the same between the second switching circuit BR2 and the third switching circuit BR3, and between the third switching circuit BR3 and the fourth switching circuit BR4. Thereby, the signal from the shift register SR input to the first switching portion SW1 (connection portion 202-13) of the first switching circuit BR1 is sequentially supplied to the first switching portions SW1 of the second switching circuit BR2 to the fourth switching circuit BR4.

[0078] In addition, the conductive layer 202-2 has a third gate electrode 202-21 of the third transistor Tr1-3n. The third gate electrode 202-21 has a double-gate structure. In addition, the conductive layer 202-2 has a second connection line 202-22 connected to one side of the third gate electrode 202-21 having the double-gate structure, and the second connection line 202-22 is connected to the third gate electrode 202-21 of the third transistor Tr1-3n of the second switch circuit BR2. Such a connection relationship is the same between the second switch circuit BR2 and the third switch circuit BR3, and between the third switch circuit BR3 and the fourth switch circuit BR4. Accordingly, the signal input to the second switch unit SW2 of the first switch circuit BR1 is sequentially supplied to the second switch units SW2 of the second switch circuit BR2 to the fourth switch circuit BR4.

[0079] In addition, a bridge electrode 202-3 is provided at a position between the respective switch circuits BR.

[0080] In addition, relay electrodes 202-5 to 202-8 are provided between the fourth switch circuit BR4 and the display region 22. Although not shown, the relay electrode 202-5 is electrically connected to the output of the first switch circuit BR1. The relay electrode 202-6 is electrically connected to the output of the second switch circuit BR2. The relay electrode 202-7 is electrically connected to the output of the third switch circuit BR3. The relay electrode 202-8 is electrically connected to the output of the fourth switch circuit BR4. The relay electrodes 202-5 to 202-8 are respectively connected to gate wirings GL2 extending along the first direction D1 in the display region 22 although not shown.

[0081] As Figure 8 and Figure 9 shown, semiconductor layers 204-1 to 204-4 are arranged along the first direction D1 in a region overlapping with the conductive layers 202-1 and 202-2. The semiconductor layers 204-1 to 204-4 constitute the semiconductor layers of the first switch circuit BR1 to the fourth switch circuit BR4, respectively. Since the structures of the respective semiconductor layers are the same, hereinafter, with reference to Figure 9 only the semiconductor layer 204-1 will be described.

[0082] The semiconductor layer 204-1 has a first n-type channel portion 204-11 facing the first gate electrode 202-11. In addition, the semiconductor layer 204-1 has a first n-type source portion 204-12 and a first n-type drain portion 204-13 on both sides of the first n-type channel portion 204-11, that is, Figure 9 in the vertical direction.

[0083] In addition, the semiconductor layer 204-1 has a p-type channel portion 204-14 facing the second gate electrode 202-12. In addition, the semiconductor layer 204-1 has, on both sides of the p-type channel portion 204-14, that is,Figure 9 has a p-type drain portion 204-15 and a p-type source portion 204-16 in the vertical direction.

[0084] In addition, the semiconductor layer 204-1 has a second n-type channel portion 204-17 opposed to the third gate electrode 202-21. In addition, on both sides of the second n-type channel portion 204-17 of the semiconductor layer 204-1, that is, Figure 9 in the vertical direction on the above, there are a second n-type source portion 204-18 and a second n-type drain portion 204-19.

[0085] That is, the semiconductor layer 204-1 of the first switch circuit BR1 is arranged and provided with a first n-type source portion 204-12, a first n-type channel portion 204-11, a first n-type drain portion 204-13, a p-type drain portion 204-15, a p-type channel portion 204-14, a p-type source portion 204-16, a second n-type source portion 204-18, a second n-type channel portion 204-17, and a second n-type drain portion 204-19 in order from top to bottom. Figure 9

[0086] The first n-type drain portion 204-13 and the p-type drain portion 204-15 are adjacently arranged. In addition, the p-type source portion 204-16 and the second n-type source portion 204-18 are adjacently arranged.

[0087] Figure 4 As Figures 8 to 10 shown, an insulating layer IL1 and a gate insulating layer GI2 are provided on the semiconductor layers 204-1 to 204-4. In the insulating layer IL1 and the gate insulating layer GI2, as Figures 8 to 10 shown, contact holes 206-1 to 206-7 are provided at positions overlapping with the semiconductor layer 204-1. More specifically, as Figure 9 shown, a plurality of contact holes 206-1 are provided along the first direction D1 to expose the p-type source portion 204-16 and the second n-type source portion 204-18. A plurality of contact holes 206-2 are provided along the first direction D1 to expose the second n-type drain portion 204-19. A plurality of contact holes 206-3 are provided along the first direction D1 to expose the first n-type drain portion 204-13 and the p-type drain portion 204-15. A plurality of contact holes 206-4 are provided along the first direction D1 to expose the first n-type source portion 204-12.

[0088] As Figure 8 shown, a plurality of contact holes 206-5 are provided along the second direction D2 to expose both end portions of the bridge electrode 202-3. A plurality of contact holes 206-7 are provided along the second direction D2 to expose the relay electrodes 202-5 to 202-8.

[0089] In Figure 4 andFigure 10 In [description], conductive layers 208-1 to 208-4 are provided on the insulating layer IL1, which function as source electrodes or drain electrodes of the first transistor Tr1-1n, the second transistor Tr1-2p, and the third transistor Tr1-3n. The conductive layer 208-3 has: a first source electrode portion 208-31 that extends along the first direction D1 and is connected to the first n-type source portion 204-12 via a contact hole 206-4; a contact portion 208-32 that is connected to the bridge electrode 202-3 via a contact hole 206-5 provided at one end of the first source electrode portion 208-31; and a first wiring portion 208-33 that is provided at the other end of the first source electrode portion 208-31 and extends along the second direction D2. In addition, a conductive layer 208-9 that is substantially the same shape as the conductive layer 208-3 except for the shape of the left end is provided at a position adjacent to the second switch circuit BR2 in the second direction D2, and an end portion of such a conductive layer 208-9 is connected to the bridge electrode 202-3 via a contact hole 206-5. That is, two adjacent conductive layers (the conductive layer 208-3 and the conductive layer 208-9 in the above description) are connected to each other via the bridge electrode 202-3. As Figure 10 shown, the same applies to other adjacent switch circuits BR (between the conductive layer 208-9 and the conductive layer 208-10, between the conductive layer 208-10 and the conductive layer 208-11). Thus, the conductive layers 208-3, 208-9 to 11 are at the same potential, and the conductive layer 208 functions as a potential supply line 260 of the switch circuit BR1, and the conductive layers 208-9 to 11 also function as potential supply lines 260 of the respective switch circuits BR2 to BR4.

[0090] In addition, the conductive layer 208-1 has a second source electrode portion 208-11 extending along the first direction D1. The second source electrode portion 208-11 is connected to the p-type source portion 204-16 and the second n-type source portion 204-18 via the contact hole 206-1. Here, the conductive layer 208-1 is in butt contact with these p-type source portion 204-16 and the second n-type source portion 204-18. The butt contact means a structure in which an n-type conductive region and a p-type conductive region having different electrical conductivity characteristics are connected to each other via a conductive layer. Note that, not limited to such a structure, the following structure can also be adopted: contact holes are provided at positions opposed to the p-type source portion 204-16 and at positions opposed to the second n-type source portion 204-18, respectively, and the second source electrode portion 208-11 is connected to the p-type source portion 204-16 and the second n-type source portion 204-18 via the respective contact holes. In addition, the conductive layer 208-1 has a second wiring portion 208-13 extending along the second direction D2 and is connected to one end of the second source electrode portion 208-11. Note that the conductive layers 208-5, 208-6, and 208-7 respectively connected to the switch circuits BR2 to BR4 also have the same structure as the conductive layer 208-1 and function as the potential supply lines 270 for the respective switch circuits BR2 to BR4.

[0091] The conductive layer 208-2 has a first drain electrode portion 208-21, a second drain electrode portion 208-22, and a connection portion 208-23. The first drain electrode portion 208-21 is connected to the first n-type drain portion 204-13 and the p-type drain portion 204-15 via the contact hole 206-3. The second drain electrode portion 208-22 is connected to the second n-type drain portion 204-19 via the contact hole 206-2. The connection portion 208-23 connects two adjacent first drain electrode portions 208-21 and the second drain electrode portion 208-22.

[0092] The conductive layer 208-4 has: an opposed electrode portion 208-41 that is opposed to the second gate electrode 202-12 via the semiconductor layer 204-1 (p-type channel portion 204-14); and a contact portion 208-42 that is connected to the conductive layer 202-1 via the contact hole 206-6.

[0093] In addition, on the insulating layer IL1, first intermediate electrodes 208-5 to 208-8 are provided along the second wiring portion 208-13 of the fourth switch circuit BR4. The first intermediate electrode 208-5 is connected to the relay electrode 202-5 via the contact hole 206-7. The same applies to the other first intermediate electrodes 208-6 to 208-8. Note that, as Figure 4As shown, in the pixel region, an oxide semiconductor layer OS is provided between an insulating layer IL1 and a gate insulating layer GI2. In addition, a gate wiring GL2 is provided opposite to the oxide semiconductor layer OS. A gate insulating layer GI2 is provided between the oxide semiconductor layer OS and the gate wiring GL2. The conductive layers 208-1 to 208-4 and the first intermediate electrodes 208-5 to 208-8 are formed of the same conductive layer as the gate wiring GL2 of the transistor Tr2. An insulating layer IL2 is provided on the conductive layers 208-1 to 208-4 and the first intermediate electrodes 208-5 to 208-8.

[0094] Figure 11 In [the structure], contact holes 212-1 to 212-3 are provided in the insulating layer IL2. A plurality of the contact holes 212-1 are provided along a first direction D1, exposing a second source electrode portion 208-11 of the conductive layer 208-1. It should be noted that these contact holes 212-1 are provided between the contact holes 206-1 in a plan view. A plurality of the contact holes 212-2 are provided along the first direction D1, exposing a second drain electrode portion 208-22 of the conductive layer 208-2. A plurality of the contact holes 212-3 are provided along a second direction D2, exposing the first intermediate electrodes 208-5 to 208-8.

[0095] In addition, a conductive layer 214-1 is provided on the insulating layer IL2. The conductive layer 214-1 has: a long strip-shaped contact portion 214-11 that extends along the x direction and is connected to the second source electrode portion 208-11 of the conductive layer 208-1 via the contact hole 212-1; and a third wiring portion 214-12 that extends along the second direction D2 and is connected to the contact portion 214-11. The third wiring portion 214-12 overlaps with the second wiring portion 208-13.

[0096] In addition, a strip-shaped electrode 214-2 (also referred to as an electrode portion) that is adjacent to the contact portion 214-11 of the conductive layer 214-1 in the second direction D2 is provided on the insulating layer IL2. The strip-shaped electrode 214-2 is connected to the second drain electrode portion 208-22 of the conductive layer 208-2 via the contact hole 212-2.

[0097] In addition, as Figure 11 and Figure 12 shown, on the insulating layer IL2, second intermediate electrodes 214-5 to 214-8 are provided at positions opposite to the first intermediate electrodes 208-5 to 208-8. The second intermediate electrodes 214-5 to 214-8 are respectively connected to the first intermediate electrodes 208-5 to 208-8 via the contact holes 212-3.

[0098] In addition, on the insulating layer IL2, a fourth wiring portion 214-3 is provided that extends in the second direction D2 and overlaps with the first wiring portion 208-33.

[0099] The conductive layer 214-1, the strip electrode 214-2, and the fourth wiring portion 214-3 are formed of the same conductive layer as the wiring W2 that functions as one of the source electrode or the drain electrode of the transistor Tr2. An insulating layer IL3 is provided on the conductive layer 214-1, the strip electrode 214-2, and the fourth wiring portion 214-3.

[0100] As Figure 4 , Figure 11 and Figure 12 shown, contact holes 216-1 and 216-2 are provided in the insulating layer IL3. The contact hole 216-1 exposes the strip electrode 214-2 of each switch circuit BR. In a plan view, the contact hole 216-1 and the contact hole 212-2 are arranged along the first direction D1, but the width in the first direction D1 is larger than that of the contact hole 212-2. In addition, the contact hole 216-1 is provided between the contact holes 212-2. In addition, the contact hole 216-2 exposes the second intermediate electrodes 214-5 to 214-8. The width of the contact hole 216-2 in the first direction D1 (the length in the first direction D1) is also larger than that of the contact hole 212-3 located nearby in a plan view.

[0101] In addition, transparent intermediate electrodes 218-1, 218-5 to 218-8 are provided on the insulating layer IL3. The transparent intermediate electrode 218-1 is formed in a rectangular shape and provided at a position overlapping with the strip electrode 214-2, and is connected to the strip electrode 214-2 via the contact hole 216-1. The width of the transparent intermediate electrode 218-1 in the second direction D2 (the length in the second direction D2) is smaller than the width of the strip electrode 214-2 in the second direction D2.

[0102] In addition, the transparent intermediate electrodes 218-5 to 218-8 are formed in a rectangular shape and provided at positions overlapping with the second intermediate electrodes 214-5 to 214-8, and are connected to these second intermediate electrodes 214-5 to 214-8 via the contact hole 216-2. The widths of the transparent intermediate electrodes 218-5 to 218-8 in the first direction D1 and the second direction D2 are smaller than the widths of the second intermediate electrodes 214-5 to 214-8, respectively.

[0103] In addition, the transparent intermediate electrode 218-1 of the first switch circuit BR1 and the transparent intermediate electrode 218-5 are at positions where the coordinate positions in the second direction D2 at the center are almost the same. As a result, the transparent intermediate electrode 218-1 and the transparent intermediate electrode 218-5 are on an imaginary straight line parallel to the first direction D1 ( Figure 11(It is illustrated by a double-dashed line.) Overlap. The relationship between the transparent intermediate electrode 218-1 and the transparent intermediate electrodes 218-6 to 218-8 of the other switch circuit BR is the same.

[0104] The transparent intermediate electrodes 218-1 and 218-2 are formed of the same transparent conductive layer as the connection electrode ZTCO. An insulating layer IL4 is provided on the transparent intermediate electrodes 218-1 and 218-2.

[0105] In Figure 4 , Figure 13 and Figure 14 In, contact holes 222-1 and 222-2 are provided in the insulating layer IL4 made of an organic insulating material. The contact holes 222-1 and 222-2 are arranged along the first direction D1. At least a part of the contact hole 222-1 overlaps with the contact hole 216-1 in a plan view, and the transparent intermediate electrode 218-1 is exposed. In addition, at least a part of the contact hole 222-2 overlaps with the contact hole 216-2 in a plan view, and the transparent intermediate electrode 218-5 is exposed. The relationship between the transparent intermediate electrodes 218-2 to 218-4 of the other second switch circuit BR2 to the fourth switch circuit BR4 and the contact hole 222-1 and the relationship between the contact hole 222-2 and the transparent intermediate electrodes 218-6 to 218-8 are the same. It should be noted that Figure 14 is a cross-sectional view when cut along the Figure 13 A1-A2 line shown.

[0106] In addition, strip-shaped transparent electrodes 224-1 to 224-4 (also called wiring electrodes) are provided on the insulating layer IL4. The transparent electrode 224-1 is formed by extending along the first direction D1, one end overlaps with the transparent intermediate electrode 218-1, and the other end overlaps with the transparent intermediate electrode 218-5. One end of the transparent electrode 224-1 is connected to the transparent intermediate electrode 218-1 via the contact hole 222-1. In addition, the other end of the transparent electrode 224-1 is connected to the transparent intermediate electrode 218-5 via the contact hole 222-2. In other words, the transparent intermediate electrode 218-1 and the transparent intermediate electrode 218-5 are electrically connected through the transparent electrode 224-1, and further, the first switch circuit BR1 is connected to the relay electrode 202-5. Similarly, the second switch circuit BR2 is connected to the relay electrode 202-6 via the transparent electrode 224-2. The relationships between the other third switch circuit BR3 and the fourth switch circuit BR4 and the relay electrodes 202-7 and 202-8 are the same. The transparent electrodes 224-1 to 224-4 are formed of the same conductive layer as the pixel electrode PTCO2.

[0107] In addition, as Figure 4As shown, an insulating layer IL5 is provided on the transparent electrode 224-1. A contact hole 226-1 is provided in the insulating layer IL5 and at a position opposed to the transparent electrode 224-1. Similarly, contact holes 226-1 are respectively provided at positions opposed to the transparent electrodes 224-2 to 224-4. The contact holes 226-1 and the contact holes 222-2 to 226-4 are arranged along the first direction D1.

[0108] In addition, auxiliary electrodes 228-1 to 228-4 (also referred to as metal wirings) are provided on the insulating layer IL5. The auxiliary electrode 228-1 extends along the first direction D1 and is overlapped with the transparent electrode 224-1. One end is connected to the transparent electrode 224-1 via the contact hole 226-1, and the other end is similarly connected to the transparent electrode 224-1 via the contact hole 226-3. A conductive layer having light transmissivity such as a transparent electrode tends to have a high resistance. Therefore, by connecting the transparent electrode 224-1 to the auxiliary electrode 228-1 made of a metal with low resistance, the wiring resistance can be reduced.

[0109] In addition, a strip-shaped protection electrode 232-1 is further provided on the auxiliary electrode 228-1. The protection electrode 232-1 is slightly larger than the auxiliary electrode 228-1, has substantially the same width as the transparent electrode 224-1, and extends along the first direction D1. In addition, for the protection electrode 232-1, the length in the first direction D1 is slightly longer than that of the auxiliary electrode 228-1, and both end portions are connected to the transparent electrode 224-1 via the contact hole 226-2 and the contact hole 226-4. In addition, the middle portion between both end portions of the protection electrode 232-1 is in direct contact with the auxiliary electrode 228-1. Similarly, protection electrodes 232-2 to 232-4 are further provided on the auxiliary electrodes 228-2 to 228-4.

[0110] The transparent electrode 224-1, the auxiliary electrode 228-1, and the protection electrode 232-1 are respectively overlapped with each other and extend along the first direction D1, and are connected to each other via the contact holes 226-1 to 226-4, functioning as a connection wiring 250-1 (also referred to as the first connection wiring). When viewed from above, the connection wiring 250-1 intersects with the second switch circuit BR2, the third switch circuit BR3, and the fourth switch circuit BR4 in the first direction D1. In addition, one end of the connection wiring 250-1 is electrically connected to the strip-shaped electrode 214-2 constituting the output portion of the first switch circuit BR1 via the transparent intermediate electrode 218-1, and the other end of the connection wiring 250-1 is electrically connected to the relay electrode 202-5 via the transparent intermediate electrode 218-5, the second intermediate electrode 214-5, and the first intermediate electrode 208-5.

[0111] In addition, as Figure 13As shown, a connection wiring 250-2 (also referred to as the second connection wiring) having the same structure as the connection wiring 250-1 is provided at a position adjacent to the connection wiring 250-1 in the second direction D2. When viewed from above, the connection wiring 250-2 intersects with the third switch circuit BR3 and the fourth switch circuit BR4 in the first direction D1. One end thereof is connected to the output portion of the second switch circuit BR2, i.e., the strip electrode 214-2, and the other end is connected to the relay electrode 202-6.

[0112] Similarly, a connection wiring 250-3 having the same structure as the connection wiring 250-1 is provided at a position adjacent to the connection wiring 250-2 in the second direction D2. When viewed from above, the connection wiring 250-3 intersects with the fourth switch circuit BR4 in the first direction D1. One end thereof is connected to the output portion of the third switch circuit BR3, i.e., the strip electrode 214-2, and the other end is connected to the relay electrode 202-7.

[0113] Similarly, a connection wiring 250-4 having the same structure as the connection wiring 250-1 is provided at a position adjacent to the connection wiring 250-3 in the second direction D2. The connection wiring 250-4 extends in the first direction, one end thereof is connected to the output portion of the fourth switch circuit BR4, i.e., the strip electrode 214-2, and the other end is connected to the relay electrode 202-8.

[0114] It should be noted that the interval L1 between adjacent connection wirings is smaller than the width of the connection wiring, i.e., the length L2 (or width) of the transparent electrodes 224-1 and 224-2 in the second direction D2.

[0115] It should be noted that in the above structure, the connection wiring 250 is formed by the transparent electrode 224-1, the auxiliary electrode 228-1, and the protection electrode 232-1, but a structure that does not use any one or two electrodes can also be adopted.

[0116] In addition, the above-mentioned first wiring portion 208-33 and second wiring portion 208-13, and the fourth wiring portion 214-3 and third wiring portion 214-12 overlapping them function as potential supply lines. More specifically, the first wiring portion 208-33 and the fourth wiring portion 214-3 overlapping the first wiring portion 208-33 are in contact with each other at one or more positions in the wiring path, and function as a single potential supply line 260. Here, a fixed potential for fixing the pixel transistor of the pixel circuit 350 to the off state is supplied to the potential supply line 260. In addition, as Figure 10As shown, the potential supply line 260 extends along the first direction D1 via the conductive layer 208-3 and the bridge electrode 202-3, whereby this fixed potential is supplied to the second switch circuit BR2 to the fourth switch circuit BR4.

[0117] In addition, the second wiring portion 208-13 and the third wiring portion 214-12 overlapping with the second wiring portion 208-13 are in contact with each other at one or more positions in the wiring path, etc., and function as a single signal supply line 270. A pulse wave that turns on the pixel transistor is supplied to the signal supply line 270 at a predetermined period. It should be noted that the signal supply line 270 is provided for each switch circuit BR, and as the order in which the pulse wave is supplied to each switch circuit BR, it becomes the first switch circuit BR1, then the second switch circuit BR2, the second switch circuit BR2, then the third switch circuit BR3, and the third switch circuit BR3, then the fourth switch circuit BR4.

[0118] The above is the structure around the first switch circuit BR1 to the fourth switch circuit BR4 of the gate drive circuit. Here, with reference to Figure 7 , the operation until the switch circuit BR receives a signal from the shift register SR and supplies a signal to the relay electrode will be described. It should be noted that the operations of the first switch circuit BR1 to the fourth switch circuit BR4 are almost the same, so here, the operation of the first switch circuit BR1 will be described.

[0119] First, output signals from the shift register SR are supplied to the connection part 202-13 of the first switch part SW1 and the third gate electrode 202-21 of the second switch part SW2 almost simultaneously. As described above, these input signals are complementary. Here, a case where a high signal is input to the third gate electrode 202-21 and a low signal is input to the connection part 202-13 will be described. In this case, since the first transistor Tr1-1n is an n-type transistor, it becomes a cut-off state, and the potential from the signal supply line 270 (the first source electrode part 208-31) is not supplied to the first drain electrode part 208-21. In contrast, since the second transistor Tr1-2p is a p-type transistor, it becomes a conducting state, and thereby, the signal supply line 270 (the second source electrode part 208-11) is connected to the first drain electrode part 208-21 via the p-type channel part 204-14. In addition, since the third transistor Tr1-3n is an n-type transistor and a high signal is input to the third gate electrode 202-21 of the third transistor Tr1-3n, the third transistor Tr1-3n also becomes a conducting state, and thereby, the signal supply line 270 (the second source electrode part 208-11) is connected to the second drain electrode part 208-22 via the second n-type channel part 204-17. As a result, a pulse wave from the signal supply line 270 is supplied to the strip electrode 214-2, which is the output part of the first switch circuit BR1. The pulse wave is supplied to the relay electrode 202-5 via the connection wiring 250-1, and then, is supplied from the relay electrode 202-5 to the gate wiring GL2 in the display area 22. As a result, the transistor Tr2 in each pixel circuit 350 becomes a conducting state, and pixel signals are rewritten in each pixel circuit 350.

[0120] Next, a case where a low signal is input to the third gate electrode 202-21 and a high signal is input to the connection portion 202-13 will be described. In this case, since the first transistor Tr1-1n is of the n-type, it becomes conductive, and the potential from the potential supply line 260 (the first source electrode portion 208-31) is supplied to the first drain electrode portion 208-21 via the first n-type channel portion 204-11. In contrast, since the second transistor Tr1-2p is of the p-type, it becomes non-conductive, and the connection between the signal supply line (the second source electrode portion 208-11) and the first drain electrode portion 208-21 becomes non-conductive. Further, since the third transistor Tr1-3n is of the n-type and a low signal enters the third gate electrode 202-21 of the third transistor Tr1-3n, the third transistor Tr1-3n also becomes non-conductive, whereby the connection between the signal supply line (the second source electrode portion 208-11) and the second drain electrode portion 208-22 becomes non-conductive. Further, since the first drain electrode portion 208-21 and the second drain electrode portion 208-22 are connected via the connection portion 208-23, a fixed potential from the potential supply line 260 (the first source electrode portion 208-31) is supplied to the output portion of the first switch circuit BR1, i.e., the strip electrode 214-2. Then, this fixed potential is supplied to the relay electrode 202-5 via the connection wiring 250-1, and thereafter, it is supplied from the relay electrode 202-5 to the gate line of the display area 22, and each pixel transistor Tr2 is fixed to the non-conductive state.

[0121] In this way, each transistor included in the switch circuit BR is controlled to be conductive or non-conductive according to the output from the shift register SR, whereby the potentials (signals) from the potential supply line 260 and the signal supply line 270 are alternately supplied to the gate wiring. Thus, the gate signal GATE is formed.

[0122] It should be noted that the output signal from the shift register SR that drives the above-described switch circuit BR is synchronized with the supply of the pulse wave to the signal supply line 270, whereby, by one output from the shift register SR, the pulse wave is sequentially supplied from the four first switch circuits BR1 to the fourth switch circuit BR4 to the gate wiring GL of the display area 22. Further, in the above description, it is configured to supply a fixed potential from the potential supply line 260 and supply a pulse wave from the potential supply line 270 at a predetermined time, but a configuration in which the supply time of the pulse wave is changed and they are interchanged can also be employed.

[0123] In a display device such as a head-mounted display, a high-definition display with an increased number of pixels is desired. When the number of pixels increases (high definition), the number of wirings for peripheral circuits (gate drive circuit and source drive circuit) for driving the pixels increases. For example, when the gate wiring and source wiring of the transistors of the gate drive circuit are connected to the output of the switch circuit BR of the gate drive circuit and the gate wiring GL1 of the pixel circuit 350, it is necessary to wind the gate wiring and source wiring in the gate drive circuit. Therefore, the occupied area of the peripheral circuit in the substrate increases, and it is difficult to realize a narrow bezel of the display device.

[0124] In the display device 10 according to an embodiment of the present invention, in the gate drive circuit 330, each switch circuit BR is connected to the relay electrodes 202-5 to 202-8 via the respective connection wirings 250-1 to 250-4. The above-mentioned respective connection wirings 250-1 to 250-4 include a transparent conductive layer PTCO1 formed by patterning the same conductive layer as the pixel electrode PTCO2 for the pixel circuit 350. The output from each switch circuit BR is supplied to the relay electrodes 202-5 to 202-8. Here, for example, there are the second switch circuit BR2 to the fourth switch circuit BR4 between the first switch circuit BR1 and the relay electrode 202-5. However, by connecting the first switch circuit BR1 and the relay electrode 202-5 via the connection wiring 250-1 passing above the second switch circuit BR2 to the fourth switch circuit BR4, the mutual wirings are prevented from crossing on the same plane, and the output portion of the first switch circuit BR1 and the first relay portion are arranged on the same straight line parallel to the first direction D1.

[0125] Generally, the size of the non-pixel region in the display area corresponding to high-definition in the second direction D2 is smaller than the size of the switching circuit BR in the second direction D2. Therefore, for a structure in which the switching circuit BR is simply arranged only along the second direction D2, it is difficult to arrange the switching circuit BR for the gate wiring on the extension line of each gate wiring 331. In contrast, by adopting the structure of the present embodiment, although the size of the pixel region in the second direction D2 is smaller than the size of the switching circuit BR in the second direction D2, the gate wiring 331 and the switching circuit BR of the gate wiring are still arranged horizontally along the first direction D1. Thereby, the length of the wiring is shortened. Therefore, when viewed from above, the switching circuit BR and the connection wiring 250 are overlapped and arranged, so that the area of the gate drive circuit 330 when viewed from above is reduced, and the narrow bezel of the display device is realized. In addition, the length of the wiring to be routed can be shortened, so that the resistance of the wiring can be reduced. In addition, between the connection wiring 250 and each switching circuit BR below the connection wiring 250, an insulating layer made of an organic insulating material is included, and a plurality of insulating layers are interposed therebetween, and the interval is sufficiently large. Therefore, the capacitance between these connection wirings 250 and the switching circuit BR is also suppressed as much as possible. Thereby, the delay of the gate signal output from the switching circuit BR is also suppressed.

[0126] [Structure of Terminal Portion]

[0127] Next, with reference to Figure 15 and Figure 16 the structure of the terminal portion 333 will be described. Figure 15 is the layout of the terminal portion 333 when viewed from above. In addition, Figure 16 is a cross-sectional view when cut along the line B1 - B2 of Figure 15

[0128] When viewed from above, the wirings 202-51 to 202-54 extend along the second direction D2. In addition, the wiring 202-52 and the wiring 202-51 are adjacent to each other in the first direction D1. In addition, the wiring 202-52 and the wiring 202-54 are adjacent to each other in the first direction D1. In addition, the wiring 202-53 is adjacent to the wiring 202-51 and the wiring 202-54 in the first direction D1. It should be noted that the wirings 202-51 to 202-54 are in the same layer as the first gate electrode 202-11 of the switching circuit BR.

[0129] A gate insulating layer GI1, an insulating layer IL1, and a gate insulating layer GI2 are provided on the wirings 202-51 to 202-54. In these gate insulating layer GI1, insulating layer IL1, and gate insulating layer GI2, a plurality of contact holes 205-1 are provided at positions overlapping the wiring 202-51, and a plurality of contact holes 205-2 are provided at positions overlapping the wiring 202-54. ​

[0130] On the gate insulating layer GI2, island electrodes 208-51 are provided at positions overlapping with the wiring 202-51, and island electrodes 208-54 are provided at positions overlapping with the wiring 202-54. In addition, the island electrode 208-51 is connected to the wiring 202-51 via the contact hole 205-1. The island electrode 208-54 is also connected to the wiring 202-54 via the contact hole 205-2.

[0131] In addition, an insulating layer IL2 is provided on the island electrodes 208-51 and 208-52. In the insulating layer IL2, contact holes 212-11 and 212-12 are provided at positions overlapping with the island electrodes 208-51 and 208-54, respectively. It should be noted that in a plan view, the contact holes 212-11 and 205-1 are arranged differently along the second direction D2, and the contact holes 212-12 and 205-2 are also arranged differently along the second direction D2.

[0132] A terminal electrode 214-20 is provided on the insulating layer IL2. In addition, the terminal electrode 214-20 overlaps with the island electrodes 208-51 and 208-54, and is connected to these island electrodes 208-15 and 208-54 via the contact holes 212-11 and 212-12. An insulating layer IL3 is provided on the terminal electrode 214-20. An opening 216-3 is provided in the insulating layer IL3 to expose the peripheral portion of the terminal electrode 214-20 except for the peripheral portion. It should be noted that the width of the terminal electrode in the first direction D1 is larger than the width of the wiring 202-51, and in a plan view, it overlaps with both the wiring 202-52 and the wiring 202-53.

[0133] Three-layer protection electrodes 218-20, 224-20, and 232-20 covering the exposed terminal electrode 214-20 are stacked and provided on the insulating layer IL3. In addition, a region where these protection electrodes 232-20, protection electrode 224-20, protection electrode 218-20, and the terminal electrode 214-20 overlap forms a terminal portion 333 that is electrically connected to the FPC600 via anisotropic conductive particles. Figure 15 In [description], it is shown that in a plan view, the area of the protection electrode 232-20 is larger than the areas of the other protection electrodes 224-20 and 218-20, but it is not limited to this structure. The area of the protection electrode 232-20 may also be the same as the areas of the protection electrode 224-20 and the protection electrode 218-20. In addition, a structure in which any two layers or one layer of the three-layer protection electrodes 218-20, 224-20, and 232-20 is not provided can also be adopted.

[0134] According to such a structure, wirings and terminal portions are formed on different layers. Therefore, other wirings (for example, wiring 202-52 and wiring 202-53 in this embodiment) that are not connected to the terminal portion can be routed under the terminal portion, and the arrangement density of the wirings in the wiring layer is increased. In addition, a plurality of insulating layers including an organic insulating layer are provided between the terminal portion and the other wirings. Therefore, the terminal portion and the wirings are sufficiently separated in the vertical direction, and thus, the capacitance between these terminal portions and the wirings is minimized as much as possible.

[0135] As an embodiment of the present invention, as long as the above-described embodiments do not contradict each other, they can be appropriately combined and implemented. For example, the structure of the gate drive circuit 330 is shown in the above embodiment, but such a structure can also be adopted for the source drive circuit 320. In addition, those skilled in the art, as long as they have the gist of the present invention, in a manner of appropriately adding, deleting, or changing the design of components or in a manner of adding, omitting, or changing conditions of processes based on the display device of each embodiment, are included in the scope of the present invention.

[0136] Even for other effects different from those brought about by the above-described embodiments, effects that are clear from the description of this specification or easily predictable by those skilled in the art should of course be understood to be brought about by the present invention.

Claims

1. A display device having: a display area; a border area surrounding the display area; a plurality of pixel circuits disposed in the display area; peripheral circuits disposed in the border area; and wiring connecting the pixel circuits and the peripheral circuits, wherein the peripheral circuits include: a plurality of switch circuits arranged along a direction away from the display area; a plurality of relay electrodes disposed between the display area and the plurality of switch circuits; and a plurality of connection wirings respectively connecting the plurality of relay electrodes and the plurality of switch circuits, wherein the plurality of relay electrodes are connected to the wiring, and one of the plurality of connection wirings connecting one of the plurality of switch circuits and one of the plurality of relay electrodes crosses other switch circuits in a top view, wherein the switch circuits and the relay electrodes are covered by an insulating layer, the connection wirings are disposed on the insulating layer, and are connected to the switch circuits and the relay electrodes via contact holes formed in the insulating layer.

2. The display device according to claim 1, wherein the pixel circuit includes a pixel switch connected to the wiring and a pixel electrode connected to the pixel switch, the pixel electrode is formed on the insulating layer, the connection wiring has at least a wiring electrode formed on the same layer as the pixel electrode.

3. The display device according to claim 1, wherein the insulating layer includes an organic insulating film and at least one or more inorganic insulating films overlapping the organic insulating film.

4. The display device according to claim 1, wherein the switch circuit includes: a gate electrode; a gate insulating layer covering the gate electrode; a semiconductor layer disposed on the gate insulating layer; a first insulating film covering the semiconductor layer; a source electrode and a drain electrode disposed on the first insulating film and connected to the semiconductor layer via a contact hole formed in the first insulating film; a second insulating film covering the source electrode and the drain electrode; and an electrode portion overlapping the drain electrode via the second insulating film, wherein the electrode portion is connected to the drain electrode via a contact hole formed in the second insulating film, thereby constituting an output portion of the switch circuit.

5. The display device according to claim 4, wherein the output portion is further covered by the insulating layer, and the connection wiring is formed on the insulating layer and connected to the output portion via a contact hole.

6. The display device according to claim 4, wherein the gate electrodes of the respective switch circuits are connected to each other.

7. The display device according to claim 6, wherein the peripheral circuit includes a shift register, and an output from the shift register is supplied to the gate electrodes of the switch circuits disposed at positions farthest from the display area.

8. The display device according to claim 1, wherein the connection wiring includes at least a transparent electrode and a metal wiring electrically connected to the transparent electrode.

9. The display device according to claim 1, wherein each switch circuit is respectively connected to a signal supply line, and a potential supply line is shared, and the potential supply line crosses at least one signal supply line in a top view.

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