Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a substrate with an active structure and a gate structure formed above the substrate; an etch stop layer formed between the two gate structures; the etch stop layer and the active structure are spaced apart to form an expansion space, wherein the expansion space is filled with a contact structure. In the manufacturing method, a pseudo dielectric layer is formed between the etch stop layer and the active structure and then removed by etching. This creates an expansion space between the etch stop layer and the active structure into which the contact structure can extend, thereby increasing the contact area between the active structure and the contact structure and reducing contact resistance.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices capable of simultaneously supporting more complex and sophisticated functionalities. Consequently, there is a continuing trend within the semiconductor industry to manufacture integrated circuits (ICs) with low cost, high performance, and low power consumption. To date, these goals have been largely achieved by scaling down semiconductor IC size (e.g., minimum component size), thereby increasing production efficiency and reducing associated costs.

[0003] However, the current method of reducing costs by simply reducing feature size has reached a bottleneck. As device sizes gradually shrink, problems such as short channel effects and leakage current in semiconductor devices are becoming increasingly serious. Therefore, chip manufacturers are developing more efficient three-dimensional transistors, such as FinFETs, which can better adapt to the requirements of device size scaling and have the advantage of reducing short channel effects.

[0004] The manufacturing process of existing FinFET devices generally includes the following steps: S1, providing a substrate with a gate structure and an active structure, depositing an etch stop layer and a first dielectric layer between the gate structure, and then depositing a SiN barrier layer and a second dielectric layer above the gate structure, the etch stop layer and the first dielectric layer; S2, etching the second dielectric layer, the SiN barrier layer, the first dielectric layer and part of the etch stop layer to form a contact opening for depositing a metal contact structure; S3, generating a silicon nitride sidewall layer on the sidewall of the contact opening; S4, depositing a metal contact structure in the contact opening to finally obtain a FinFET device. It should be pointed out that in the above manufacturing process, since the etch stop layer covering the surface of the active structure is difficult to completely remove, the contact area between the contact structure and the active structure in the final FinFET device is limited (see Figure 5A and Figure 5B , Figure 5A is a schematic lateral cross-sectional view of an existing FinFET device, Figure 5B This is a schematic longitudinal cross-sectional view of an existing FinFET device. The transverse cross-sectional view is a plane parallel to the extension direction of the gate structure and passing through the active structure, and the longitudinal cross-sectional view is a plane perpendicular to the extension direction of the gate structure and passing through the active structure).

[0005] In particular, on the one hand, the top of the fin structure in the FinFET device is generally strained by epitaxial growth of material, resulting in various irregular structures such as bowl-shaped, Sigma-shaped, and rhombus-shaped on the top of the fin structure; on the other hand, fin structures of different sizes often exist in the same device. The above two factors will further increase the difficulty of removing the etch stop layer, resulting in the exposed fin structure area being limited, thereby affecting the contact area between the fin structure and the contact structure. Furthermore, due to the alignment of lithography or etching, the contact structure formed is prone to deviation from the preset position, resulting in a reduction in the load area of the contact structure and the active contact. Moreover, as the overall size of the FinFET device gradually decreases, the contact surface between the contact structure and the active structure will also decrease, resulting in a gradual increase in contact resistance, which in turn leads to a larger parasitic capacitance, which will significantly reduce the speed of the entire circuit. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a semiconductor device. Compared with the prior art, the contact area between the contact structure and the active structure of the semiconductor device is larger, so as to help reduce the contact resistance.

[0007] Another technical problem to be solved by the present invention is to provide a method for manufacturing the semiconductor device as described above.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is to provide a semiconductor device, which includes:

[0009] a substrate, with an active structure and a gate structure formed on the substrate;

[0010] An etch stop layer is formed between the two gate structures; the etch stop layer is spaced apart from the active structure to form an expansion space, and the expansion space is filled with a contact structure.

[0011] In the semiconductor device provided by the present invention, a dummy dielectric layer is formed between the substrate and the etching stop layer.

[0012] In the semiconductor device provided by the present invention, the pseudo dielectric layer extends into the expansion space.

[0013] In the semiconductor device provided by the present invention, the material of the pseudo dielectric layer is different from the material of the etching stop layer.

[0014] To solve the above-mentioned another technical problem, the technical solution adopted by the present invention is to provide a method for manufacturing a semiconductor device, the manufacturing method comprising the following steps:

[0015] Step S1, providing a substrate having a gate structure and an active structure, wherein the gate structure is formed above the active structure;

[0016] Step S2: forming a first dielectric layer covering the substrate, the active structure and the gate structure;

[0017] Step S3, etching the first dielectric layer into a dummy dielectric layer covering only the active structure and the substrate;

[0018] Step S4, depositing an etch stop layer over the substrate, the active structure, the gate structure and the dummy dielectric layer;

[0019] Step S5, depositing a second dielectric layer on the etching stop layer;

[0020] Step S6: planarizing the gate structure, the etching stop layer, and the second dielectric layer to obtain a first intermediate product;

[0021] Step S8: forming a covering layer on the upper surface of the first intermediate product;

[0022] Step S9, removing a portion of the cover layer, the second dielectric layer, and the etching stop layer by etching, forming a contact opening above the active structure, and obtaining a second intermediate product;

[0023] Step S12: removing the dummy dielectric layer by etching to form an expansion space for the contact structure to extend into;

[0024] Step S13: filling the contact opening and the expansion space with metal material to form a contact structure.

[0025] In the method for manufacturing a semiconductor device provided by the present invention, in step S3, the first dielectric layer is etched into a dummy dielectric layer that only covers the active structure and the substrate and is spaced apart from the gate structure.

[0026] In the method for manufacturing a semiconductor device provided by the present invention, step S3 includes the following steps:

[0027] Step S3a, depositing a patterned photoresist layer on the active structure and the first dielectric layer corresponding to the substrate;

[0028] Step S3b, removing the first dielectric layer exposed outside the photoresist layer;

[0029] Step S3c, removing the first dielectric layer between the photoresist layer and the sidewall of the gate structure;

[0030] Step S3d, removing the first dielectric layer between the sidewall of the gate structure and the active structure;

[0031] Step S3e: removing the photoresist layer.

[0032] In the method for manufacturing a semiconductor device provided by the present invention, in step S3d, the first dielectric layer between the sidewall of the gate structure and the active structure is removed along the sidewall of the gate structure by atomic etching technology to ensure that the first dielectric layer at the bottom of the photolithography layer is not etched.

[0033] In the method for manufacturing a semiconductor device provided by the present invention, the method further includes the following steps implemented between step S9 and step S12:

[0034] Step S10: forming a fourth dielectric layer on the upper surface of the second intermediate product;

[0035] Step S11 , removing the fourth dielectric layer above the cover layer and the fourth dielectric layer at the bottom of the contact opening by etching to form a sidewall layer, and removing the etching stop layer above the dummy dielectric layer by etching to expose the dummy dielectric layer.

[0036] In the method for manufacturing a semiconductor device provided by the present invention, the cover layer includes a stop layer, a third dielectric layer and a dielectric film stacked in sequence from bottom to top, and an etching selectivity ratio between the dielectric film and the third dielectric layer is greater than 50.

[0037] In the method for manufacturing a semiconductor device provided by the present invention, in step S12, the exposed dummy dielectric layer is completely removed, and at least a portion of the dummy dielectric layer sandwiched between the active structure and the etching stop layer is removed to form the expansion space.

[0038] The implementation of the present invention can at least achieve the following beneficial effects: by forming a pseudo dielectric layer between the etch stop layer and the active structure and then removing it by etching, an expansion space for the contact structure to extend into can be formed between the etch stop layer and the active structure, thereby expanding the contact area between the active structure and the contact structure and reducing the contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the invention. Those skilled in the art can also derive other drawings based on the provided drawings without inventive effort:

[0040] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided in Example 1;

[0041] Figure 2A-2L Schematic cross-sectional views of semiconductor devices at different manufacturing stages during the manufacturing process of the semiconductor device according to the method for manufacturing the semiconductor device proposed in the first embodiment;

[0042] Figure 3A-Figure 3Q Schematic longitudinal cross-sectional views of semiconductor devices at different manufacturing stages during the manufacturing process of the semiconductor device according to the method for manufacturing the semiconductor device proposed in the first embodiment;

[0043] Figure 4A-4B Schematic diagrams of horizontal cross-sections of semiconductor devices at different manufacturing stages during the manufacturing process of the semiconductor device according to the method for manufacturing the semiconductor device proposed in the first embodiment;

[0044] Figure 5A is a schematic lateral cross-sectional view of a conventional FinFET device;

[0045] Figure 5B is a schematic longitudinal cross-sectional view of a conventional FinFET device;

[0046] Figure 6 This is a schematic structural diagram of the semiconductor device provided in Example 2.

[0047] Description of the accompanying drawings in the specific implementation manner:

[0048] substrate 1 Active structure 2 Gate structure 3 Fin structure 21 sidewall 31 Dummy gate material layer 32 hard mask layer 33 First dielectric layer 4 Part 1 41 Part 2 42 Part 3 43 Horizontal part 431 vertical part 432 photolithography layer 5 gap 100 Pseudo dielectric layer 44 Etch stop layer 6 Second dielectric layer 7 Metal gate layer 34 Covering 8 Stop layer 81 The third dielectric layer 82 dielectric film 83 Contact opening 200 Fourth dielectric layer 9 Sidewall layer 91 Expansion space 300 Contact structure 10 Extended gap 301 DETAILED DESCRIPTION

[0049] To facilitate understanding of the invention, the invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate exemplary embodiments of the invention. However, the invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the invention.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the invention pertains. The terms used in the specification of the invention herein are for the purpose of describing specific embodiments only and are not intended to limit the invention.

[0051] See also Figure 1 , Figure 1 The flowchart of the method for preparing the semiconductor device provided in this embodiment is used to briefly illustrate the process of the entire manufacturing process. Figure 1 As shown, the preparation method comprises the following steps:

[0052] Step S1, providing a substrate 1 having a gate structure 3 and an active structure 2, wherein the gate structure 3 spans the active structure 2;

[0053] Step S2, forming a first dielectric layer 4 covering the substrate 1, the active structure 2 and the gate structure 3;

[0054] Step S3, etching the first dielectric layer 4 into a dummy dielectric layer 44 that only covers the active structure 2 and the substrate 1 and is spaced apart from the gate structure 3;

[0055] Step S4, depositing an etching stop layer 6 over the substrate 1, the active structure 2, the gate structure 3 and the dummy dielectric layer 44;

[0056] Step S5, depositing a second dielectric layer 7 on the etching stop layer 6;

[0057] Step S6: planarizing the gate structure 3, the etching stop layer 6, and the second dielectric layer 7 to expose the dummy gate material layer 32 in the gate structure 3, thereby obtaining a first intermediate product;

[0058] Step S7: replacing the dummy gate material layer 32 in the gate structure 3 in the first intermediate product with a metal gate layer 34 to obtain a transitional product;

[0059] Step S8, forming a covering layer 8 on the upper surface of the transition product;

[0060] Step S9: Partially remove the cover layer 8, the second dielectric layer 7, and the etching stop layer 6 by etching to form a contact opening 200, thereby obtaining a second intermediate product;

[0061] Step S10: forming a fourth dielectric layer 9 on the upper surface of the second intermediate product;

[0062] Step S11, removing the fourth dielectric layer 9 above the cover layer 8, the fourth dielectric layer 9 at the bottom of the contact opening 200, and a portion of the etching stop layer 6 by etching to form a sidewall layer 91 and expose the dummy dielectric layer 44;

[0063] Step S12: removing the dummy dielectric layer 44 by etching to form an expansion space 300 into which the contact structure 10 can extend;

[0064] Step S13 : filling the contact opening 200 and the expansion space 300 with metal material to form a contact structure 10 .

[0065] Example 1

[0066] This embodiment provides a FinFET device and a method for manufacturing the same. Figure 2A-2L 、 Figure 3A-Figure 3Q and Figure 4A-4B The detailed steps of the method for preparing the semiconductor device (FinFET device) proposed in this embodiment are described. Figure 2A-2L Schematic cross-sectional views of semiconductor devices at different manufacturing stages during the manufacturing process of the semiconductor device according to the method for manufacturing the semiconductor device proposed in this embodiment; Figure 3A-Figure 3QSchematic longitudinal cross-sectional views of semiconductor devices at different manufacturing stages during the manufacturing process of a semiconductor device according to the method for manufacturing a semiconductor device proposed in this embodiment. The transverse cross-sectional view is a plane parallel to the extension direction of the gate structure 3 and passing through the active structure 2, and the longitudinal cross-sectional view is a plane perpendicular to the extension direction of the gate structure 3 and passing through the active structure 2. In addition, Figure 2A-2L 、 Figure 3A-Figure 3Q and Figure 4A-4B , the X direction, the Y direction, and the Z direction respectively refer to the width direction, the length direction, and the thickness direction of the semiconductor device.

[0067] In step S1, an active structure 2 and a gate structure 3 are provided on a provided substrate 1. The active structure 2 may be a fin structure 21 provided along a first direction of the substrate 1, and the gate structure 3 may be provided along a second direction intersecting the first direction and intersecting the fin structure 21 via a gate dielectric layer.

[0068] Specifically, see Figure 2A The active structure 2 includes three fin structures 21, each of which extends from the substrate 1 in the Z direction and is spaced apart from each other in the Y direction. Figure 3A , each fin structure 21 extends in the X direction. It should be known to those skilled in the art that the number of fin structures 21 formed on the substrate 1 is not limited to 3, and can be 1, 2, 4 or more. The fin structure 21 can be formed by using appropriate processes such as photolithography and etching. In some embodiments, the fin structure 21 can be etched from the substrate 1 using a dry etching process, and the substrate includes an STI isolation layer. Of course, in some other embodiments, the fin structure 21 can be formed by a double patterning lithography (DPL) process. DPL is a method of constructing a pattern on the substrate 1 by dividing the pattern into two staggered patterns. DPL allows for enhanced density of devices (e.g., fins). The fin structure 21 also includes epitaxially grown strained material (SiGe / SiP), which can (together with part of the fin structure 21) serve as the source / drain of the ultimately formed semiconductor device. Continue to see Figure 3A , two gate structures 3 are provided on the upper side of the substrate 1, each gate structure 3 extends from the substrate 1 in the Z direction and is spaced apart from each other in the X direction. Figure 4A Each gate structure 3 extends in the Y direction, and the gate structure 3 surrounds both sides and the top of the fin structure 21 to form a surrounding channel. Figure 3AThe gate structure 3 includes a gate and a sidewall spacer 31 covering the sidewalls of the gate. In some embodiments, the material of the sidewall spacer 31 may include at least one of SiN, SiON, SiOC, SiOCN, SiCN, and SiC, and the sidewall spacer 31 may include a single layer or a multilayer structure. The gate may be a dummy gate material layer 32. In some embodiments, the dummy gate material layer 32 may include polysilicon, and the dummy gate material layer 32 may be formed by a deposition process such as a chemical vapor deposition (CVD) process. The gate structure 3 also includes a hard mask layer 33 formed on the dummy gate material layer 32. In some embodiments, the hard mask layer 33 may be formed on the dummy gate material layer 32 by a deposition process such as a CVD process. In some embodiments, the hard mask layer 33 may include a hard mask such as silicon nitride (SiN), silicon oxide, or a combination thereof. In some embodiments, the hard mask layer 33 may be a multilayer structure. For example, the hard mask layer 33 may include a silicon nitride layer formed on the dummy gate material layer 32 and a silicon oxide layer formed on the silicon nitride layer.

[0069] In step S2, a first dielectric layer 4 covering the substrate 1, the active structure 2 and the gate structure 3 is formed. It should be noted that the process for forming the first dielectric layer 4 can be a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The material of the first dielectric layer 4 can be selected from silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride or silicon oxynitride. Here, the material of the first dielectric layer 4 is preferably silicon oxide. Combined with Figure 2B and 3B It can be seen that the first dielectric layer 4 formed in step S2 completely covers the substrate 1, the active structure 2, and the gate structure 3. For the convenience of subsequent description, the portion of the first dielectric layer 4 covering the surface of the substrate 1 is referred to as the first portion 41, the portion of the first dielectric layer 4 covering the surface of the active structure 2 is referred to as the second portion 42, and the portion of the first dielectric layer 4 covering the surface of the gate structure 3 is referred to as the third portion 43. Here, the third portion 43 of the first dielectric layer 4 can be further divided into a horizontal portion 431 covering the surface of the hard mask layer 33 of the gate structure 3 and a vertical portion 432 covering the sidewall 31 of the gate structure 3.

[0070] In step S3, the first dielectric layer 4 is etched into a dummy dielectric layer 44 covering only the active structure 2 and the substrate 1 and spaced apart from the gate structure 3. In this embodiment, the dummy dielectric layer 44 is formed specifically through steps S3a to S3e as described below.

[0071] In step S3a, a patterned photoresist layer 5 is deposited on the first dielectric layer 4 corresponding to the active structure 2 and the substrate 1. It should be noted that the photoresist layer 5 can be deposited using methods familiar to those skilled in the art, such as spin coating. As mentioned above, the first dielectric layer 4 is divided into a first portion 41, a second portion 42, and a third portion 43. The third portion 43 is divided into a horizontal portion 431 and a vertical portion 432. Figure 2C and 3C It can be seen that the photolithography layer 5 covers the entire first portion 41 and the entire second portion 42, and abuts a portion of the third portion 43. In other words, a portion of the third portion 43 of the first dielectric layer 4 is exposed outside the photolithography layer 5. At the same time, because the upper surface of the photolithography layer 5 is lower than the upper surface of the horizontal portion 431, the two opposite sides of the photolithography layer 5 in the X direction only contact the lower portion of the vertical portion 432. In this way, the lower portion of the vertical portion 432 abuts the photolithography layer 5, while the upper portion is exposed outside the photolithography layer 5. At the same time, the horizontal portion 431 is completely exposed outside the photolithography layer 5. In the solution of the present invention, adjacent gate structures 3 and the active structure 2 between the adjacent gate structures 3 form a recessed groove. As a result, the patterned photolithography layer 5 involved is directly deposited on the first dielectric layer 4 corresponding to the recessed groove, which reduces the process difficulty and improves efficiency.

[0072] In step S3b, the first dielectric layer 4 exposed outside the photoresist layer 5 is removed by an isotropic etching method. Figure 3D After step S3b, the third portion 43 of the first dielectric layer 4 is partially removed. Specifically, the horizontal portion 431 and the upper portion of the vertical portion 432 are removed. The lower portion of the vertical portion 432, the entire first portion 41, and the entire second portion 42 are retained.

[0073] In step S3c, the first dielectric layer 4 between the photoresist layer 5 and the sidewall spacer 31 of the gate structure 3 is removed by an anisotropic etching method. Figure 3E After step S3c, the lower portion of the vertical portion 432 of the first dielectric layer 4 is partially removed, thereby forming a gap 100 between the photoresist layer 5 and the sidewall spacer 31. The entire first portion 41 and the entire second portion 42 are retained.

[0074] In step S3d, the first dielectric layer 4 between the sidewall 31 of the gate structure 3 and the active structure 2 is removed along the sidewall 31 of the gate structure 3 by atomic etching technology to ensure that the first dielectric layer 4 at the bottom of the photoresist layer 5 is not etched. Figure 3FAfter the step S3d, the first dielectric layer 4 located directly below the gap 100 is removed, and the first dielectric layer 4 located directly below the photoresist layer 5 is retained. The first dielectric layer 4 retained after the step S3d is the pseudo dielectric layer 44. Figure 3F As can be seen in FIG, both ends of the dummy dielectric layer 44 in the X direction are spaced apart from the sidewalls 31 .

[0075] In step S3e, the photoresist layer 5 is removed. It should be noted that the photoresist layer 5 can be removed by using a photoresist layer 5 removal process commonly used in the art, for example, by using a dry etching process and / or a wet etching process to remove the photoresist layer 5. Figure 3G After the processing in step S3e, the photoresist layer 5 is completely removed.

[0076] Through the above steps SS3a to S3e, multiple etching processes are combined to avoid removing the first dielectric layer 4 corresponding to the patterned photoresist layer 5 as much as possible, and finally form a pseudo dielectric layer 44 that only covers the active structure 2 and the substrate 1 and is separated from the gate structure 3.

[0077] In step S4, an etch stop layer 6 is deposited over the substrate 1, the active structure 2, the gate structure 3, and the dummy dielectric layer 44. It should be noted that the process for forming the etch stop layer 6 can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. The material of the etch stop layer 6 has good etching selectivity with the material of the first dielectric layer. The material of the etch stop layer 6 may include silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride, or silicon oxynitride. Figure 2D and Figure 3H The etching stop layer 6 formed in step S4 completely covers the substrate 1 , the active structure 2 , the gate structure 3 and the dummy dielectric layer 44 .

[0078] In step S5, a second dielectric layer 7 is deposited on the etching stop layer 6. It should be noted that the process for forming the second dielectric layer 7 can be a chemical vapor deposition process or a physical vapor deposition process. The material of the second dielectric layer 7 can be selected from silicon oxide, silicon nitride, silicon carbide, silicon boronitride, silicon oxycarbon nitride or silicon oxynitride. Figure 2E and Figure 3I The second dielectric layer 7 formed in step S5 covers the surface of the etching stop layer 6.

[0079] In step S6, the gate structure 3, the etching stop layer 6 and the second dielectric layer 7 are planarized to obtain a first intermediate product. Figure 2F and Figure 3JIn this step, the gate structure 3 , the etching stop layer 6 and the second dielectric layer 7 are planarized until the dummy gate material layer 32 of the gate structure 3 is exposed.

[0080] In step S7, see Figure 3K The dummy gate material layer 32 in the gate structure 3 of the first intermediate product is replaced with a metal gate layer 34 to obtain a transition product. The method of forming the metal gate layer 34 is well known in the art and will not be described in detail here.

[0081] In step S8, a covering layer 8 is formed on the upper surface of the transition product. Figure 2G and Figure 3L Here, a stop layer 81, a third dielectric layer 82, and a dielectric film 83 are sequentially deposited on the upper surface of the transition product. That is, the cap layer 8 includes the stop layer 81, the third dielectric layer 82, and the dielectric film 83 stacked in sequence from bottom to top. It should be noted that the process for forming the stop layer 81, the third dielectric layer 82, and the dielectric film 83 can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. The material of the stop layer 81 can be selected from silicon nitride, silicon carbide nitride, silicon boron nitride, silicon nitride carbon oxide, or silicon oxynitride. The material of the third dielectric layer 82 can be silicon oxide. The material of the dielectric film 83 can be selected from silicon nitride, silicon carbide nitride, silicon carbide, silicon oxycarbon, silicon nitride carbon oxide, silicon oxynitride, or a metal oxide, wherein the metal oxide is selected from, for example, aluminum oxide, titanium oxide, hafnium oxide, and zirconium oxide. The dielectric film material should have good etching selectivity (e.g., an etching selectivity greater than 50) with the third dielectric layer (e.g., silicon oxide) to protect the third dielectric layer and ensure the simplicity of subsequent dielectric film removal. In step S9, a portion of the dielectric film 83, the third dielectric layer 82, the stop layer 81, the second dielectric layer 7, and the etch barrier layer 6 are etched away to form a contact opening 200 in the middle and above the active structure 2. Figure 2H and Figure 3M The middle portions of dielectric film 83, third dielectric layer 82, stop layer 81, and second dielectric layer 7 are etched through, exposing the middle portion of etch stop layer 6. Dummy dielectric layer 44 remains covered by etch stop layer 6. It should be noted that dielectric film 83 protects third dielectric layer 82. Specifically, it 1) prevents damage to third dielectric layer 82 during etching of the fourth dielectric layer to form sidewall layer 91, and 2) prevents damage to third dielectric layer 82 during removal of dummy dielectric layer 44.

[0082] In step S10, a fourth dielectric layer 9 is formed on the upper surface of the intermediate product obtained in step S9. It should be noted that the process for forming the fourth dielectric layer 9 can be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. The material of the fourth dielectric layer 9 needs to have a high etching selectivity with the material of the first dielectric layer 4. The material of the fourth dielectric layer 9 can be selected from silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride, or silicon oxynitride. Figure 2I and Figure 3N The fourth dielectric layer 9 formed in step S10 covers the dielectric film 83 and the entire inner wall of the contact opening 200 .

[0083] In step S11, the fourth dielectric layer 9 above the dielectric film 83 and the fourth dielectric layer 9 at the bottom of the opening are removed by etching to form a sidewall layer 91, and the dummy dielectric layer 44 is exposed by etching a portion of the etching stop layer 6. Figure 2J and Figure 3O In step S11, the fourth dielectric layer 9 covering the dielectric film 83 and the fourth dielectric layer 9 covering the dummy dielectric layer 44 are removed, and the remaining fourth dielectric layer 9 covering the inner wall of the contact opening 200 is the sidewall layer 91. In addition, in step S11, the etching stop layer 6 covering the dummy dielectric layer 44 is also partially removed, so that the dummy dielectric layer 44 covering the active structure 2 is exposed through the contact opening.

[0084] In step S12, the dummy dielectric layer 44 is removed by etching to form an expansion space 300 into which the contact structure 10 can extend. Figure 2K and Figure 3P In step S12, the exposed pseudo dielectric layer 44 is removed. At the same time, at least a portion of the pseudo dielectric layer 44 sandwiched between the active structure 2 and the etching stop layer 6 is also removed to form the expansion space 300. The pseudo dielectric layer 44 is removed by an isotropic etching scheme (such as chemical etching) to remove as much material of the pseudo dielectric layer 44 as possible. Preferably, the material of the pseudo dielectric layer 44 is different from the material of the etching stop layer 6, which is beneficial for the etching stop layer 6 to provide a better etching stop point for the subsequent formation of the expansion space 300. Figure 2K and Figure 3P As can be seen in FIG, the expansion space 300 includes a plurality of extended gaps 301 respectively connected to the contact openings 200 and located between the active structure 2 and the etching stop layer 6.

[0085] In step S13, metal material is filled in the contact opening 200 and the expansion space 300 to form a contact structure 10. Preferably, the method of depositing the contact structure 10 adopts single atomic layer deposition so that the metal material fills the expansion space. In addition, after forming the contact structure 10, the dielectric film 83 can be removed by planarization to expose the third dielectric layer 82. Figure 2L 、 Figure 3Q and Figure 4B In the final semiconductor device, the contact structure 10 is filled with the contact opening 200 and the extended gap 301, thereby expanding the contact area between the contact structure 10 and the active structure 2. Specifically, the final semiconductor device includes a substrate 1, with an active structure 2 and a gate structure 3 located on both sides of the active structure 2 formed above the substrate 1; an etch stop layer 6 formed between the two gate structures 3 and surrounding the active structure 2; the etch stop layer 6 is connected to a fourth dielectric layer 9, and the fourth dielectric layer 9 and the etch stop layer 6 together enclose the contact opening 200; the fourth dielectric layer 9 and the etch stop layer 6 are surrounded by the second dielectric layer 7, the stop layer 81, and the third dielectric layer 82 from bottom to top. Most importantly, the etch stop layer 6 is separated from the active structure 2 to form an expansion space 300, which is filled with the contact structure 10. A dummy dielectric layer 44 is formed between the substrate 1 and the etching stop layer 6 , and the dummy dielectric layer 44 extends into the expansion space 300 .

[0086] It should be noted that, even if affected by the process, there will be residual pseudo dielectric layer 44 between the bottom of the etching stop layer 6 and the active structure 2. However, compared with the prior art, the contact area between the contact structure 10 and the active structure 2 in the conductor device provided by the present invention is still expanded.

[0087] Example 2

[0088] This embodiment provides a two-dimensional planar structure MOS device and its manufacturing method. The specific manufacturing method can refer to the first embodiment. Figure 6 , Figure 6 A schematic diagram of the structure of the MOS device provided in this embodiment is shown in FIG. Figure 6As shown, the final semiconductor device (i.e., MOS device) includes a substrate 1, with a gate structure 3 and an active structure 2 provided above the substrate 1; an etch stop layer 6, which abuts the sidewall of the gate structure 3 and is partially separated from the active structure 2 to form an expansion space 300; a fourth dielectric layer 9, which is connected to the etch stop layer 6 and is jointly enclosed with the etch stop layer 6 to form a contact opening 200, wherein the periphery of the fourth dielectric layer 9 and the etch stop layer 6 is, from bottom to top, the second dielectric layer 7, the stop layer 81 and the third dielectric layer 82; and a contact structure 10, which fills the contact opening 200 and the expansion space 300.

[0089] In summary, in the manufacturing method provided by the present invention, by forming a pseudo dielectric layer 44 between the etch stop layer 6 and the active structure 2 and then removing it by etching, an expansion space 300 for the contact structure 10 to extend into can be formed between the etch stop layer 6 and the active structure 2, thereby expanding the contact area between the active structure 2 and the contact structure 10 and reducing the contact resistance.

[0090] It should be noted that, in the above-mentioned preparation method, step S7 is an optional step. That is, in some other embodiments, the step of replacing the dummy gate material layer 32 with the metal gate layer 34 may not be included.

[0091] The embodiments of the invention are described above in conjunction with the accompanying drawings, but the invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the inspiration of the invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the invention and the claims, all of which are protected by the invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises the following steps: Step S1, providing a substrate (1) having a gate structure (3) and a plurality of active structures (2), wherein the gate structure (3) is formed above the active structure (2), the tops of the plurality of active structures present an irregular structure, and the plurality of active structures have different volumes; Step S2, forming a first dielectric layer (4) covering the substrate (1), the active structure (2) and the gate structure (3); Step S3, etching the first dielectric layer (4) into a dummy dielectric layer (44) covering only the active structure (2) and the substrate (1); The step S3 comprises the following steps: Step S3a, depositing a patterned photoresist layer (5) above the active structure (2) and the first dielectric layer (4) corresponding to the substrate (1); Step S3b, removing the first dielectric layer (4) exposed outside the photoresist layer (5); Step S3c, removing the first dielectric layer (4) between the photoresist layer (5) and the sidewall (31) of the gate structure (3); Step S3d, removing the first dielectric layer (4) between the sidewall (31) of the gate structure (3) and the active structure (2); Step S3e, removing the photoresist layer (5), forming a pseudo dielectric layer (44) that only covers the active structure (2) and the substrate (1) and is spaced apart from the gate structure (3); Step S4, depositing an etching stop layer (6) above the substrate (1), the active structure (2), the gate structure (3) and the pseudo dielectric layer (44); Step S5, depositing a second dielectric layer (7) on the etching stop layer (6); Step S6, planarizing the gate structure (3), the etching stop layer (6) and the second dielectric layer (7) to obtain a first intermediate product; Step S8, forming a covering layer (8) on the upper surface of the first intermediate product; Step S9, removing a portion of the cover layer (8), the second dielectric layer (7), and the etching stop layer (6) by etching, forming a contact opening (200) above the active structure, and obtaining a second intermediate product; Step S12: removing the pseudo dielectric layer (44) by etching to form an expansion space (300) for the contact structure (10) to extend into; the exposed pseudo dielectric layer (44) is completely removed, and at least a portion of the pseudo dielectric layer (44) sandwiched between the active structure (2) and the etching stop layer (6) is removed to form the expansion space (300); Step S13: filling the contact opening (200) and the expansion space (300) with metal material to form a contact structure (10).

2. The method for manufacturing a semiconductor device according to claim 1, wherein: In the step S3d, the first dielectric layer (4) between the sidewall (31) of the gate structure (3) and the active structure (2) is removed along the sidewall (31) of the gate structure (3) by using an atomic etching technique.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The manufacturing method further includes the following steps implemented between step S9 and step S12: Step S10, forming a fourth dielectric layer (9) on the upper surface of the second intermediate product; Step S11: removing the fourth dielectric layer (9) above the cover layer (8) and the fourth dielectric layer (9) at the bottom of the contact opening (200) by etching to form a sidewall layer (91), and removing the etching stop layer (6) above the dummy dielectric layer (44) by etching to expose the dummy dielectric layer (44).

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The covering layer (8) comprises a stop layer (81), a third dielectric layer (82) and a dielectric film (83) stacked in sequence from bottom to top, and an etching selectivity ratio of the dielectric film (83) to the third dielectric layer (82) is greater than 50.

5. A semiconductor device, characterized in that: Obtained by the manufacturing method according to any one of claims 1 to 4, the semiconductor device comprises: A substrate (1), wherein a plurality of active structures (2) and a gate structure (3) are formed on the substrate (1), the tops of the plurality of active structures present irregular structures, and the plurality of active structures have different volumes; an etch stop layer (6) formed between the two gate structures (3); the etch stop layer (6) is spaced apart from the active structure (2) to form an expansion space (300); the expansion space (300) comprises a plurality of extended gaps (301) respectively connected to the contact openings (200) and located between the active structure (2) and the etch stop layer (6); the expansion space (300) is filled with a contact structure (10); A pseudo dielectric layer (44) is formed between the substrate (1) and the etching stop layer (6), and the pseudo dielectric layer (44) extends into the expansion space (300).

6. The semiconductor device according to claim 5, wherein The material of the pseudo dielectric layer (44) is different from the material of the etching stop layer (6).

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