A monitoring circuit monitors the performance of a transistor

Abstract

The present disclosure relates to a monitoring circuit that monitors performance of a transistor. The monitoring circuit according to an embodiment of the present disclosure includes a booster configured to amplify an amount of current between a terminal to which a power supply voltage is applied and a ground terminal to generate a sensing voltage, and an oscillator configured to output a sensing signal, a frequency of the sensing signal being adjusted in response to the sensing voltage, wherein the booster includes a transistor having a first size and a transistor having a second size larger than the first size, and wherein the oscillator includes a plurality of transistors having a third size larger than the first size.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0055659, filed on April 29, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a monitoring circuit for monitoring the performance of a transistor, and more particularly, to a monitoring circuit capable of monitoring the performance of a PMOS transistor or an NMOS transistor. Background Technology

[0004] An electronic system can be composed of multiple transistors and can perform various functions depending on the connection configuration of these transistors. For example, depending on the connection configuration of the multiple transistors, an electronic system can be configured to store data, perform various logical operations, or perform various other functions.

[0005] As mentioned above, because electronic systems can be configured to perform various functions through the interconnection of multiple transistors, the performance of an electronic system can vary depending on the performance of the multiple transistors. Summary of the Invention

[0006] Embodiments of this disclosure provide a monitoring circuit that can improve the reliability of a monitoring circuit for monitoring transistor performance by increasing the amount of frequency change of a signal that varies according to transistor performance.

[0007] In an embodiment of this disclosure, a monitoring circuit includes: a boost converter configured to amplify the amount of current between a terminal to which a power supply voltage is applied and a ground terminal to generate a sense voltage; and an oscillator configured to output a sense signal, the frequency of which is adjusted in response to the sense voltage, wherein the boost converter includes a transistor having a first size and a transistor having a second size larger than the first size, and wherein the oscillator includes a plurality of transistors having a third size larger than the first size.

[0008] In embodiments of this disclosure, a monitoring circuit includes: a first sensing circuit including PMOS transistors of different sizes and configured to output a first sensing signal, the frequency of which is adjusted according to the current generated by the PMOS transistors; and a second sensing circuit including NMOS transistors of different sizes and configured to output a second sensing signal, the frequency of which is adjusted according to the current generated by the NMOS transistors.

[0009] In embodiments of this disclosure, an electronic system includes: a boost converter including a first boost transistor and a second boost transistor connected in series between a power supply voltage terminal and a ground terminal, and configured to output a sense voltage corresponding to the characteristics of the first boost transistor and the second boost transistor through a first node; and an oscillator including a plurality of stages of a ring structure, and configured to output a sense signal in response to the sense voltage through a second node, the frequency of the sense signal being adjusted proportionally to the sense voltage, wherein each of the plurality of stages includes a pair of third transistors and an inverter connected in series between the power supply voltage terminal and the ground terminal, wherein the first boost transistor has a first size, the second boost transistor has a second size larger than the first size, the third transistor has a third size larger than the first size, and each of the first to third sizes indicates the length of a channel formed between two adjacent junction regions in a substrate.

[0010] This technique allows for precise monitoring of transistor performance by amplifying frequencies that vary according to the transistor's performance. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating an electronic system according to an embodiment of the present disclosure.

[0012] Figure 2 This is a diagram illustrating a monitoring circuit according to an embodiment of the present disclosure.

[0013] Figure 3 This is a diagram illustrating a first sensing circuit according to an embodiment of the present disclosure.

[0014] Figure 4 This is a diagram used to compare the sizes of transistors included in a first sensing circuit according to an embodiment of the present disclosure.

[0015] Figure 5 This is a cross-sectional view showing the size of the transistors included in a first sensing circuit according to an embodiment of the present disclosure.

[0016] Figure 6 This is a diagram illustrating a second sensing circuit according to an embodiment of the present disclosure.

[0017] Figure 7 This is a diagram illustrating the size of the transistors included in a second sensing circuit according to an embodiment of the present disclosure.

[0018] Figure 8 This is a cross-sectional view showing the size of the transistors included in a second sensing circuit according to an embodiment of the present disclosure.

[0019] Figure 9 This is a graph showing the gain relative to the width of the transistor according to an embodiment of the present disclosure.

[0020] Figure 10 and Figure 11 This is a diagram illustrating the frequency of a voltage that varies based on the width of a transistor according to an embodiment of the present disclosure. Detailed Implementation

[0021] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification are shown only to illustrate embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0022] Figure 1 This is a diagram illustrating an electronic system 1000 according to an embodiment of the present disclosure.

[0023] Reference Figure 1 The electronic system 1000 may include electronic devices 1100 and monitoring circuits 1200.

[0024] The electronic system 1000 can be activated in response to an electrical signal and can be configured to perform various operations according to the function of the electronic device 1100.

[0025] In one embodiment, electronic device 1100 may be a device that performs a specific function, such as a sensor, display device, or communication device. In another embodiment, electronic device 1100 may be a controller that performs functions to control devices such as sensors, display devices, or communication devices. In yet another embodiment, electronic device 1100 may be a storage device for storing and outputting data.

[0026] Electronic device 1100 may include various types of transistors. For example, electronic device 1100 may include multiple PMOS transistors and NMOS transistors. The transistors can be configured to electrically connect the source and drain by forming a channel according to the voltage applied to the gate. Therefore, the electrical characteristics of electronic device 1100 can vary depending on the electrical characteristics of the transistors. Because the electrical characteristics of the transistors can vary depending on the manufacturing process of electronic device 1100, electronic device 1100 can set the current, voltage, etc., for internal operation according to the electrical characteristics of the transistors.

[0027] The monitoring circuit 1200 can be configured to sense the electrical characteristics of the transistors in the configuration electronics 1100 and output a first sensing signal SIG_P and a second sensing signal SIG_N. In some embodiments, even if the power supply voltage VDD decreases, the monitoring circuit 1200 can adjust the frequencies of the first sensing signal SIG_P and the second sensing signal SIG_N to easily sense the electrical characteristics of the transistors. For example, the monitoring circuit 1200 may include a transistor for sensing current. The monitoring circuit 1200 can be configured to increase the current and amplify the frequencies of the first sensing signal SIG_P and the second sensing signal SIG_N by changing the size of the transistor.

[0028] Electronic device 1100 may include an arithmetic unit 1110 for calculating the frequencies of a first sensing signal SIG_P and a second sensing signal SIG_N output from monitoring circuit 1200. Electronic device 1100 may set current, voltage, etc., suitable for internal operation based on the values ​​calculated by arithmetic unit 1110.

[0029] That is, when the power supply voltage VDD is low, the current flowing through the monitoring circuit 1200 also decreases, and therefore the frequencies of the first sensing signal SIG_P and the second sensing signal SIG_N generated by the current decrease. When the frequency decreases, the arithmetic unit 1110 may have difficulty accurately calculating the frequencies of the first sensing signal SIG_P and the second sensing signal SIG_N. The monitoring circuit 1200 of the embodiment can be configured to adjust the frequencies of the first sensing signal SIG_P and the second sensing signal SIG_N.

[0030] Figure 2 This is a diagram illustrating a monitoring circuit 1200 according to an embodiment of the present disclosure.

[0031] Reference Figure 2 The monitoring circuit 1200 may include a first sensing circuit 210 and a second sensing circuit 220 configured to sense the performance of different types of transistors.

[0032] The first sensing circuit 210 can be configured to sense the performance of a first type of transistor. For example, the first sensing circuit 210 can be configured to sense the performance of a PMOS transistor. The performance of the PMOS transistor can be determined by the amount of current Ip flowing between its source SC and drain DR. In embodiments, the performance of the PMOS transistor can increase as the current Ip increases, and the performance of the PMOS transistor can decrease as the current Ip decreases. For example, the first sensing circuit 210 can output a first sensing signal SIG_P with a higher frequency due to the higher performance of the PMOS transistor, and output a first sensing signal SIG_P with a lower frequency due to the lower performance of the PMOS transistor.

[0033] The second sensing circuit 220 can be configured to sense the performance of a second type of transistor, different from the first type. For example, the second sensing circuit 220 can be configured to sense the performance of an NMOS transistor. The performance of an NMOS transistor can be determined by the amount of current In flowing between its source SC and drain DR. In embodiments, the performance of an NMOS transistor can increase as the current In increases, and the performance of an NMOS transistor can decrease as the current In decreases. For example, the second sensing circuit 220 can output a second sensing signal SIG_N with a higher frequency due to the higher performance of the NMOS transistor, and output a second sensing signal SIG_N with a lower frequency due to the lower performance of the NMOS transistor.

[0034] Figure 3 This is a diagram illustrating a first sensing circuit according to an embodiment of the present disclosure, for example... Figure 2 A diagram of the first sensing circuit 210.

[0035] Reference Figure 3 The first sensing circuit 210 may include a first boost converter 1BST and a first oscillator 1OSC. The first boost converter 1BST may be configured to increase the frequency of the first sensing voltage Vps generated by the PMOS transistor. The first oscillator 1OSC may be configured to output a first sensing signal SIG_P in response to the first sensing voltage Vps. The configuration of the first boost converter 1BST and the first oscillator 1OSC is described below.

[0036] The first boost converter 1BST may include a first boost transistor 1B and a second boost transistor 2B connected in series between a terminal to which a power supply voltage VDD is applied and a ground terminal GND. The first boost transistor 1B and the second boost transistor 2B may be implemented as PMOS transistors. The first boost transistor 1B may be adjacent to the terminal to which the power supply voltage VDD is applied, and the second boost transistor 2B may be adjacent to the ground terminal GND. The gate of the first boost transistor 1B may be connected to a first node N1, which may also be connected to a node between the first boost transistor 1B and the second boost transistor 2B. Therefore, the conduction level of the first boost transistor 1B can be adjusted in response to a voltage determined based on the current Ip between the first boost transistor 1B and the second boost transistor 2B. The gate of the second boost transistor 2B may be connected to a second node N2, which may also be connected to the ground terminal GND.

[0037] To amplify the current Ip between the first boost transistor 1B and the second boost transistor 2B, the size of the second boost transistor 2B can be made larger than the size of the first boost transistor 1B. For example, the size of the second boost transistor 2B can be made M times the size of the first boost transistor 1B (where M is a positive rational number greater than 1). As the size difference between the first boost transistor 1B and the second boost transistor 2B increases, the current Ip at the first node N1 can increase. Furthermore, as the current Ip increases, the frequency of the first sense voltage Vps, which is the voltage at the first node N1, can increase.

[0038] [Equation 1]

[0039] Ip = (M / (M+1)) × GM × VDD

[0040] Referring to Equation 1, the current Ip can be determined by M, which corresponds to the size of the second boost transistor 2B, the transistor gain GM, and the supply voltage VDD. Since an increase in the transistor gain GM indicates improved transistor performance, it is preferable to set a larger value for M to enhance transistor performance. For example, when M is 10, approximately 90% of the gain GM is reflected in the transistor's performance, and when M is 100, approximately 99% of the gain GM is reflected in the transistor's performance. That is, the gain GM is proportional to the transistor size, and the current Ip is proportional to the gain GM.

[0041] The first oscillator 1OSC can be implemented as a ring oscillator. For example, the first oscillator 1OSC may include a first stage 1ST to a j-th stage jST connected in series with each other. Here, j can be an odd number greater than or equal to 3. The first stage 1ST to the j-th stage jST can operate together in response to a first sense voltage Vps, and can be operated by feeding back a first sense signal SIG_P in clock form from the j-th stage jST to the first stage 1ST. Because the first stage 1ST to the j-th stage jST are configured with the same structure, the structure of the first stage 1ST is described as an example below.

[0042] The first stage 1ST may include a first PMOS transistor 1P and a first inverter I1 connected in series between a terminal to which a power supply voltage VDD is applied and a ground terminal GND. The first PMOS transistor 1P can be turned on or off in response to a first sensed voltage Vps. When the first PMOS transistor 1P is on, the power supply voltage VDD can be output as a first sub-voltage 1Vsd, and the first sub-voltage 1Vsd can be supplied as the operating power for the first inverter I1; that is, the first inverter I1 receives the first sub-voltage 1Vsd as a voltage source. The first sensed signal SIG_P output from the j-th stage jST can be input to the input terminal of the first inverter I1. The signal output from the first inverter I1 can be input to the input terminal of the second inverter I2 in the second stage 2ST. The size of the first PMOS transistor 1P can be implemented as m times the size of the first boost transistor 1B (where m is a positive rational number greater than 1), and is independent of the size of the second boost transistor 2B. When the size of the first PMOS transistor 1P is larger than the size of the first boost transistor 1B, the current flowing through the first PMOS transistor 1P and the first inverter I1 can be increased. Furthermore, when the current increases, the frequency of the first sub-voltage 1Vsd can be increased.

[0043] That is, in the first oscillator 1OSC, the number of the first stage 1ST to the jth stage jST can adjust the delay time of the first sensing signal SIG_P, the size of the first PMOS transistor 1P to the jth PMOS transistor jP being greater than the size of the first boost transistor 1B can increase the frequency of the first sub-voltage 1Vsd, and the frequency of the first sensing signal SIG_P can be increased by the configuration of the first oscillator 1OSC.

[0044] Figure 4 This is a diagram used to compare the sizes of transistors included in a first sensing circuit according to an embodiment of the present disclosure, for example... Figure 3 A diagram showing the size of the transistors included in the first sensing circuit 210.

[0045] Reference Figure 3 and Figure 4 The size of the transistors included in the first sensing circuit 210 represents the width WT of each transistor. Here, the width WT of the transistor represents the length of the channel CH. For example, the width of the first boost transistor 1B is 1, the width of the second boost transistor 2B can be greater than 1M, and the width of each of the first PMOS transistor 1P to the j-th PMOS transistor jP can be greater than 1m.

[0046] Figure 5 This is a cross-sectional view showing the size of the transistors included in a first sensing circuit according to an embodiment of the present disclosure, for example... Figure 3A cross-sectional view of the size of the transistors included in the first sensing circuit 210.

[0047] Reference Figure 5 The first boost transistor 1B and the second boost transistor 2B can be configured by junction regions JT formed in a substrate SUB and insulating layers IS and gates 1GT and 2GT stacked on the substrate SUB. The size of the first boost transistor 1B can be defined as the length of the channel CH formed between two adjacent junction regions JT. For example, the first boost transistor 1B can have a first width 1WT, and the first width 1WT is the same as the channel length of the first boost transistor 1B. The size of the second boost transistor 2B, which is larger than the size of the first boost transistor 1B, can be defined as the length of the channel CH formed between two adjacent junction regions JT. For example, the second boost transistor 2B can have a Mth width MWT that is wider than the first width 1WT, and the Mth width MWT is the same as the channel length of the second boost transistor 2B. For example, the Mth width MWT is M times the first width 1WT.

[0048] Although Figure 5 Not shown in the image, but Figure 3 Each of the first PMOS transistor 1P to the j-th PMOS transistor jP shown can have a width of M, and the width MWT is M times the width 1WT of the first PMOS transistor.

[0049] Figure 6 This is a diagram illustrating a second sensing circuit according to an embodiment of the present disclosure, for example... Figure 2 A diagram of the second sensing circuit 220.

[0050] Reference Figure 6 The second sensing circuit 220 may include a second boost converter 2BST and a second oscillator 2OSC. The second boost converter 2BST may be configured to increase the frequency of the second sensing voltage Vns generated by the NMOS transistor. The second oscillator 2OSC may be configured to output a second sensing signal SIG_N in response to the second sensing voltage Vns. The configuration of the second boost converter 2BST and the second oscillator 2OSC is described below.

[0051] The second boost converter 2BST may include a third boost transistor 3B and a fourth boost transistor 4B connected in series between a terminal to which a power supply voltage VDD is applied and a ground terminal GND. The third boost transistor 3B and the fourth boost transistor 4B may be implemented as NMOS transistors. The fourth boost transistor 4B may be adjacent to the terminal to which the power supply voltage VDD is applied, and the third boost transistor 3B may be adjacent to the ground terminal GND. The gate of the fourth boost transistor 4B may be connected to a third node N3, and the third node N3 may be connected to the terminal to which the power supply voltage VDD is applied. Therefore, the fourth boost transistor 4B can be continuously turned on while the power supply voltage VDD is supplied to the third node N3. The gate of the third boost transistor 3B may be connected to a fourth node N4 between the third boost transistor 3B and the fourth boost transistor 4B. Therefore, the turn-on level of the third boost transistor 3B can be adjusted in response to the voltage determined by the current In between the third boost transistor 3B and the fourth boost transistor 4B.

[0052] To amplify the current In between the third boost transistor 3B and the fourth boost transistor 4B, the size of the fourth boost transistor 4B can be made larger than the size of the third boost transistor 3B. For example, the size of the fourth boost transistor 4B can be N times the size of the third boost transistor 3B (where N is a positive rational number greater than 1). As the size difference between the third boost transistor 3B and the fourth boost transistor 4B increases, the current In at the fourth node N4 can increase. Furthermore, as the current In increases, the frequency of the second sense voltage Vns, which is the voltage at the fourth node N4, can be increased.

[0053] The current In can be determined by N, corresponding to the size of the fourth boost transistor 4B, the transistor gain GM, and the supply voltage VDD. The relationship between the current In, gain, and transistor size is similar to that in Equation 1 above. Therefore, since an increase in transistor gain indicates improved transistor performance, it is preferable to set the value of N to be large to improve transistor performance. Setting a large value for N means that the fourth boost transistor 4B is formed as N times the size of the third boost transistor 3B during the manufacturing process.

[0054] The second oscillator 2OSC can be implemented as a ring oscillator. For example, the second oscillator 2OSC may include a first stage 1ST to a j-th stage jST connected in series. The first stage 1ST to the j-th stage jST of the second oscillator 2OSC can be connected with... Figure 3The first stages 1ST to jST of the first oscillator 1OSC are physically configured differently. In the first stages 1ST to jST of the second oscillator 2OSC, j can be an odd number greater than or equal to 3. The first stages 1ST to jST can operate together in response to the second sense voltage Vns, and can be operated by feeding back the second sense signal SIG_N, which is in the form of a clock, from the output of jST to the first stage 1ST. Because the first stages 1ST to jST are configured with the same structure, the structure of the first stage 1ST is described as an example below.

[0055] The first stage 1ST may include a first inverter I1 and a first NMOS transistor 1N connected in series between a terminal to which the power supply voltage VDD is applied and a ground terminal GND. The first inverter I1 can form a current path between the terminal to which the power supply voltage VDD is applied and the first NMOS transistor 1N. A second sensing signal SIG_N output from the j-th stage jST can be input to the input of the first inverter I1. The signal output from the first inverter I1 can be input to the input of a second inverter I2 included in the second stage 2ST. The first NMOS transistor 1N can be configured to receive a second sub-voltage 2Vsd generated by the current from the first inverter I1 and turned on or off in response to the second sensing voltage Vns. When the first NMOS transistor 1N is turned on, the terminal to which the second sub-voltage 2Vsd is applied and the ground terminal GND can be connected, thus reducing the second sub-voltage 2Vsd.

[0056] The size of the first NMOS transistor 1N can be implemented as n times the size of the third boost transistor 3B (where n is a positive rational number greater than 1), and is independent of the size of the fourth boost transistor 4B. When the size of the first NMOS transistor 1N is greater than the size of the third boost transistor 3B, the amount of current flowing between the first inverter I1 and the first NMOS transistor 1N increases. Furthermore, as the current increases, the frequency of the second sub-voltage 2Vsd can increase.

[0057] That is, in the second oscillator 2OSC, the number of the first stage 1ST to the jth stage jST can adjust the delay time of the second sensing signal SIG_N, the fact that the first NMOS transistor 1N to the jth NMOS transistor jN is greater than the size of the third boost transistor 3B can increase the frequency of the second sub-voltage 2Vsd, and the frequency of the second sensing signal SIG_N can be increased by the configuration of the second oscillator 2OSC.

[0058] Figure 7 This is a diagram illustrating the size of the transistors included in a second sensing circuit according to an embodiment of the present disclosure, for example... Figure 6 A diagram showing the size of the transistors included in the second sensing circuit 220.

[0059] Reference Figure 6 and Figure 7 The size of the transistors included in the second sensing circuit 220 represents the width WT of each transistor. Here, the width WT of the transistor represents the length of the channel CH. For example, the width of the third boost transistor 3B is 1, the width of the fourth boost transistor 4B can be greater than 1 / N, and the width of each of the first NMOS transistors 1N to j-th NMOS transistors jN can be greater than 1 / n.

[0060] Figure 8 This is a cross-sectional view showing the size of the transistors included in a second sensing circuit according to an embodiment of the present disclosure, for example... Figure 6 A cross-sectional view of the size of the transistors included in the second sensing circuit 220.

[0061] Reference Figure 8 The third boost transistor 3B and the fourth boost transistor 4B may include junction regions JT formed in the substrate SUB and insulating layers IS and gates 3GT and 4GT stacked on the substrate SUB. The size of the third boost transistor 3B may be defined as the length of the channel CH formed between two adjacent junction regions JT. For example, the third boost transistor 3B may have a first width 1WT, and the first width 1WT is the same as the channel length of the third boost transistor 3B. The size of the fourth boost transistor 4B, which is larger than the size of the third boost transistor 3B, may be defined as the length of the channel CH formed between two adjacent junction regions JT. For example, the fourth boost transistor 4B may have an Nth width NWT wider than the first width 1WT, and the Nth width NWT is the same as the channel length of the fourth boost transistor 4B. For example, the Nth width NWT is N times the first width 1WT.

[0062] Although Figure 8 Not shown in the image, but Figure 6 Each of the first NMOS transistor 1N to the jNth NMOS transistor jN shown can have an Nth width, and the Nth width NWT is N times the first width 1WT.

[0063] Figure 9 This is a graph showing the gain GM relative to the width WT of the transistor according to an embodiment of the present disclosure.

[0064] Reference Figure 9As the width WT of a PMOS or NMOS transistor increases, the carrier mobility within the transistor can increase. Furthermore, as carrier mobility increases, the gain GM, a performance characteristic of the transistor, can increase. Therefore, the transistor gain GM can be proportional to the transistor width WT. For example, since the carriers in a PMOS transistor are holes and the carriers in an NMOS transistor are electrons, in embodiments, the width WT can be adjusted considering the electrical characteristics of the PMOS or NMOS transistor. Here, adjusting the transistor width means adjusting the width based on... Figure 1 The width is set in the manufacturing steps of the monitoring circuit 1200 to manufacture transistors.

[0065] Figure 10 and Figure 11 This is a diagram illustrating the frequency of a voltage that varies based on the width of a transistor according to an embodiment of the present disclosure.

[0066] Reference Figure 10 ,when Figure 3 The second boost transistor 2B or Figure 6 When the width of the fourth boost transistor 4B increases or decreases based on the first width 1WT, from Figure 3 The first oscillator 1OSC or Figure 6 The frequency (MHz) of the first sensing signal SIG_P or the second sensing signal SIG_N output by the second oscillator 2OSC can be increased or decreased according to the width of the transistor. For example, the frequency (MHz) of the signal output by a transistor with a first width of 1WT is 2. In this case, when the width of the transistor decreases from the first width of 1WT, the frequency (MHz) can decrease to 1, and when the width of the transistor increases from the first width of 1WT, the frequency (MHz) can increase to 4. As another example, when the size of some transistors increases as in the above embodiment, a signal with a frequency of 20MHz in the related art can be output as a signal with a frequency of 40MHz in the embodiment, and a signal with a frequency of 40MHz in the related art can be output as a signal with a frequency of 80MHz in the embodiment. When the frequency (MHz) of the first sensing signal SIG_P or the second sensing signal SIG_N increases, the signal output by the transistor can be improved. Figure 1 The reliability of the frequencies of the first sensing signal SIG_P and the second sensing signal SIG_N calculated by the arithmetic unit 1110.

[0067] Reference Figure 11 The electrical characteristics of a transistor with a width WT of 1 are compared with those of a transistor with a width WT greater than 1, M.

[0068] When the transistor width WT is 1, the frequency (MHz) of the signal generated by the slow-speed transistor is A1, the frequency (MHz) of the signal generated by the normal-speed transistor is A2, and the frequency (MHz) of the signal generated by the fast-speed transistor is A3. Since the frequency (MHz) is proportional to the processing speed, A2 is greater than A1, and A3 is greater than A2.

[0069] When the width WT of the transistor is greater than 1M, the frequency (MHz) of the signal generated by the slow-speed transistor is B1, the frequency (MHz) of the signal generated by the normal-speed transistor is B2, and the frequency (MHz) of the signal generated by the fast-speed transistor is B3. Since the frequency (MHz) is proportional to the processing speed, B2 is greater than B1 and B3 is greater than B2.

[0070] As the transistor width WT increases, the frequency can increase simultaneously with the increase in transistor gain. Therefore, B1 is greater than A1, B2 is greater than A2, and B3 is greater than A3.

[0071] That is, generated when the transistor width WT is greater than 1 M. Figure 1 The frequency of the first sensing signal SIG_P or the second sensing signal SIG_N is higher than the frequency when the transistor width WT is 1. Therefore, because for Figure 1 For the arithmetic unit 1110, it becomes easier to calculate the frequency of signals, so the reliability of the calculation can be improved.

[0072] Embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, these are merely for the purpose of describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can exist within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein and the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A monitoring circuit, comprising: A boost converter amplifies the current between the power supply voltage terminal and the ground terminal to generate a sense voltage. as well as An oscillator outputs a sensing signal, the frequency of which is adjusted in response to the sensing voltage. The boost converter includes a first transistor having a first size and a second transistor having a second size larger than the first size, wherein the first transistor and the second transistor are transistors of the same conductivity type. The first transistor and the second transistor are connected in series between the power supply voltage terminal and the ground terminal, and The oscillator includes a plurality of transistors having a third size that is larger than the first size.

2. The monitoring circuit according to claim 1, wherein the boost converter includes a first boost transistor and a second boost transistor, the first boost transistor and the second boost transistor being connected in series between the terminal to which the power supply voltage is applied and the ground terminal.

3. The monitoring circuit of claim 2, wherein the first boost transistor is adjacent to the terminal to which the power supply voltage is applied and has the first size, and the second boost transistor is adjacent to the ground terminal and has the second size.

4. The monitoring circuit of claim 2, wherein the first boost transistor is adjacent to the ground terminal and has the first size, and the second boost transistor is adjacent to the terminal to which the power supply voltage is applied and has the second size.

5. The monitoring circuit of claim 2, wherein the sensing voltage is generated at the gate of the first boost transistor.

6. The monitoring circuit of claim 2, wherein the gate of the first boost transistor is connected to the oscillator and the node between the first boost transistor and the second boost transistor.

7. The monitoring circuit according to claim 2, wherein the gate of the second boost transistor is connected to the ground terminal or the terminal to which the power supply voltage is applied.

8. The monitoring circuit according to claim 1, wherein the oscillator comprises multiple stages, the multiple stages outputting the sensing signal, the frequency of the sensing signal being adjusted in response to the sensing voltage.

9. The monitoring circuit of claim 8, wherein each of the plurality of stages includes a third transistor and an inverter, the third transistor and the inverter being connected in series between a terminal to which the power supply voltage is applied and the ground terminal.

10. The monitoring circuit of claim 9, wherein the third transistor has the third size and outputs a sub-voltage in response to the sensed voltage.

11. The monitoring circuit of claim 10, wherein the inverter receives the sub-voltage as a voltage source and receives a signal output from the inverter included in the preceding stage as an input signal.

12. The monitoring circuit of claim 11, wherein the inverter included in the last stage of the plurality of stages outputs the sensing signal, and The sensed signal is fed back to an inverter included in the first of the plurality of stages.

13. A monitoring circuit, comprising: A first sensing circuit includes PMOS transistors with channels of different lengths and outputs a first sensing signal, the first frequency of which is adjusted according to the current generated by the PMOS transistors. The first sensing circuit includes a first boost converter, which includes PMOS transistors with channels of different lengths. as well as The second sensing circuit includes NMOS transistors with channels of different lengths and outputs a second sensing signal, the second frequency of which is adjusted according to the current generated by the NMOS transistors. The second sensing circuit also includes a second boost converter, which includes NMOS transistors with channels of different lengths.

14. The monitoring circuit of claim 13, wherein the first sensing circuit comprises: The first boost converter includes a first boost transistor having a first length and a second boost transistor having a second length longer than the first length, and outputs a first sense voltage generated based on the amount of current between the first boost transistor and the second boost transistor; as well as A first oscillator outputs the first sensing signal, and the first frequency of the first sensing signal is adjusted in response to the first sensing voltage.

15. The monitoring circuit according to claim 14, wherein the first oscillator has a ring oscillator structure.

16. The monitoring circuit of claim 15, wherein the first oscillator comprises: Multiple PMOS transistors having a third length that is longer than the first length; as well as Multiple inverters receive sub-voltages output from the multiple PMOS transistors as voltage sources and output the first sensing signal in response to an input signal.

17. The monitoring circuit of claim 13, wherein the second sensing circuit comprises: The second boost converter includes a third boost transistor having a fourth length and a fourth boost transistor having a fifth length longer than the fourth length, and outputs a second sense voltage generated based on the amount of current between the third boost transistor and the fourth boost transistor; as well as The second oscillator outputs the second sensing signal, and the second frequency of the second sensing signal is adjusted in response to the second sensing voltage.

18. The monitoring circuit of claim 17, wherein the second oscillator has a ring oscillator structure.

19. The monitoring circuit of claim 18, wherein the second oscillator comprises: Multiple inverters receive the power supply voltage as a voltage source and output the second sensing signal in response to the input signal; as well as Multiple NMOS transistors form a current path between the inverter and the ground terminal, and have a sixth length that is longer than the fourth length.

20. An electronic system comprising: A boost converter includes a first transistor and a second transistor of the same conductivity type connected in series between a power supply voltage terminal and a ground terminal, and outputs a sense voltage corresponding to the characteristics of the first transistor and the second transistor through a first node; as well as An oscillator comprising multiple stages of a ring structure, and responding to the sensed voltage by outputting a sensed signal through a second node, the frequency of which is adjusted proportionally to the sensed voltage. Each of the plurality of stages includes a pair of third transistors and an inverter connected in series between the power supply voltage terminal and the ground terminal. The first transistor has a first size, the second transistor has a second size larger than the first size, the third transistor in each of the plurality of stages has a third size larger than the first size, and each of the first to the third sizes indicates the length of a channel formed between two adjacent junction regions in the substrate.

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