High-precision current acquisition circuit and electronic device

Abstract

A high-precision current acquisition circuit provided by the present invention, the high-precision current acquisition circuit includes: a control module, a first acquisition module, a second acquisition module, and an operational amplifier module; the first acquisition module and the second acquisition module form a mirror acquisition current structure; the second acquisition module includes a second power transistor; the first acquisition module includes N first power transistors, and the sizes of the N first power transistors are different, so that the ratio K value of the size of each first power transistor to the size of the second power transistor is different; wherein, N is a positive integer, and N≥2; the control module is used to select any one of the N first power transistors as the selected power transistor; and is used to control the working states of the second power transistor and the selected power transistor; the control module adjusts the K value by switching different first power transistors as the selected power transistor, so as to weaken the acquisition error caused by the input offset voltage of the operational amplifier and improve the acquisition accuracy.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and in particular, to a high-precision current acquisition circuit and an electronic device. Background Art

[0002] Current acquisition technology refers to the method of using a proportional mirror tube to acquire the current information on a target device for subsequent signal processing. In order to accurately acquire the current signal on the target device, an operational amplifier plus mirror acquisition structure is usually adopted, and the virtual short characteristic of the operational amplifier is used to make the three-terminal voltages of the mirror acquisition tube and the target device the same.

[0003] However, since the offset voltage of the operational amplifier is fixed, there is always an error of the input offset voltage of the operational amplifier between the voltages va and vb on the mirror acquisition tube. At the same time, the proportional K value is fixed, and usually this fixed K value is relatively large. If a relatively small current is acquired and the mirror current is still reduced according to the same ratio, then under the same input offset voltage Vos, the Vos of this operational amplifier will account for a large proportion in the acquired current, ultimately resulting in poor accuracy of the acquired current.

[0004] In the prior art, the method to improve the current acquisition accuracy is to improve the accuracy of the operational amplifier for stabilizing the voltage, so that the values of va and vb are as close as possible, or to reduce the Vos of the operational amplifier as much as possible. However, this method of improving the accuracy is difficult to implement and costly in the case of acquiring small currents; and it has very high requirements for the accuracy of the operational amplifier, and reducing the Vos will make the design of the operational amplifier extremely complex. Once the design of the operational amplifier becomes complex, the stability and reliability of the system will be reduced; Summary of the Invention

[0005] The present invention provides a high-precision current acquisition circuit and an electronic device to solve the problem of difficult improvement of current acquisition accuracy in the case of relatively small currents; and at the same time, it can accurately acquire currents with wide-range variations.

[0006] According to a first aspect of the present invention, there is provided a high-precision current acquisition circuit and an electronic device, a high-precision current acquisition circuit, the high-precision current acquisition circuit includes: a control module, a first acquisition module, a second acquisition module, and an operational amplifier module; the high-precision current acquisition circuit is used to acquire the current information flowing through the first acquisition module; the first acquisition module and the second acquisition module form a mirror acquisition current structure; the second acquisition module includes a second power transistor; the first acquisition module includes N first power transistors with different sizes, so that the ratio of the size of each first power transistor to the size of the second power transistor is different; where N is a positive integer and N≥2;

[0007] The output end of the control module is connected to the first input end of the first acquisition module. The second input end of the control module is connected to the second input end of the first acquisition module and the input end of the second acquisition module. The output end of the first acquisition module is connected to the first input end of the operational amplifier module. The output end of the second acquisition module is connected to the second input end of the operational amplifier module;

[0008] The control module is used to select several first power tubes among the N first power tubes as the selected power tubes; and to control the working states of the second power tube and the selected power tubes;

[0009] Wherein, the first current reference information I1 flowing through the first acquisition module and the first current reference information I2 flowing through the second acquisition module satisfy:

[0010] I2 = I1 / k; where k is the size ratio of the selected power tubes to the second power tube;

[0011] There is an input offset voltage between the voltages at the first input end and the second input end of the operational amplifier module. The control module adjusts the K value by switching different first power tubes as the selected power tubes to weaken the acquisition error caused by the input offset voltage and improve the acquisition accuracy.

[0012] Optionally, the second current reference information flowing through the second acquisition module satisfies:

[0013] I3 = I2 + V os / R2;

[0014] Wherein, V os is the input offset voltage, and R2 is the internal resistance of the second acquisition module.

[0015] Optionally, the N first power tubes are arranged in sequence, and the size of the first power tube ranked as the i-th one satisfies: S i = X i where, S i is the size of the i-th first power tube, X is a natural number, and X ≥ 2, 1 ≤ i ≤ N.

[0016] Optionally, the control module includes: a first control unit and a second control unit. The first control unit includes a first control signal input end, and the second control unit includes a second control signal input end;

[0017] Wherein, the output end of the first control unit is connected to the input end of the second control unit;

[0018] The first control unit is used to select several first power tubes among the N first power tubes as the selected power tubes;

[0019] The second control unit is configured to control the operating states of the second power transistor and the selected power transistor.

[0020] Optionally, the first acquisition module includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor;

[0021] Wherein, the sources and drains of the first MOS transistor to the seventh MOS transistor are respectively connected to the source and drain of the second power transistor, the gates of the first MOS transistor to the seventh MOS transistor are all connected to the output terminal of the control module, and the gate of the second power transistor is connected to the second control signal input terminal.

[0022] Optionally, the first control unit includes an encoder, and the second control unit includes a switching circuit;

[0023] The control module is configured to:

[0024] The encoder generates the first control signal through different permutations and combinations and sends it to the switching circuit to select several first power transistors among the N first power transistors as the selected power transistors;

[0025] The switching circuit receives the first control signal and the second input control signal to control the operating state of the selected power transistor and drive the second power transistor.

[0026] Optionally, the switching circuit includes a first switch to a seventh switch;

[0027] The control module is further configured to:

[0028] The first switch to the seventh switch respectively control the operating state of any one of the first MOS transistor to the seventh MOS transistor.

[0029] Optionally, the control module is further configured to:

[0030] Obtain a k value based on the ratio of the size of the selected power transistor in the first acquisition module to the size of the second power transistor.

[0031] Optionally, the first acquisition module is configured to:

[0032] Obtain a first current reference information I1 flowing through the first acquisition module;

[0033] Based on I1 and k, determine a first current reference information I2 flowing through the second acquisition module;

[0034] Transmit the first current reference information I2 = I1 / k flowing through the second acquisition module to the second acquisition module and the operational amplifier module.

[0035] Optionally, the second acquisition module is configured to:

[0036] Obtain the first current reference information I2 = I1 / k flowing through the second acquisition module;

[0037] Based on the first current reference information I2, V flowing through the second acquisition module os and R2, determine the second current reference information I3 = I2 + V flowing through the second acquisition module os / R2.

[0038] Optionally, the first acquisition module further includes a zero-th MOS transistor, the source and drain of the zero-th MOS transistor are connected in parallel to the second power transistor, and the gate of the zero-th MOS transistor is connected to the second control signal input terminal of the control module;

[0039] The control module is further configured to:

[0040] Based on the ratio of the size of the zero-th MOS transistor to the size of the second power transistor, obtain the minimum value of k, and the minimum value of k represents the value that satisfies the minimum current acquisition accuracy.

[0041] Optionally, the types of the first power transistor and the second power transistor are the same.

[0042] According to the second aspect of the present invention, there is provided an electronic device including the high-precision current acquisition circuit of the first aspect and its options.

[0043] For the high-precision current acquisition circuit and the electronic device provided by the present invention, the control module is used to select several first power transistors among the N first power transistors as the selected power transistors, and control the selected power transistors, so as to obtain the size ratio of the selected power transistors to the second power transistor as k. Since the sizes of the N first power transistors are all different, the values of k are also different. Furthermore, the control module can adjust the value of k by controlling the working states of different first power transistors, so as to weaken the acquisition error caused by the input offset voltage and improve the acquisition accuracy.

[0044] In addition, the present invention does not improve the acquisition accuracy by reducing V os Therefore, the operational amplifier module remains unchanged, avoiding the complexity of the operational amplifier design caused by reducing V os on. Description of the Drawings

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figure 1 is a schematic diagram of the structure of the current acquisition circuit of the prior art in an example of the present invention Figure 1 ;

[0047] Figure 2 is a schematic diagram of the structure of the current acquisition circuit of the prior art in an example of the present invention Figure 2 ;

[0048] Figure 3 is a schematic diagram of the structure of the high-precision current acquisition circuit in an example of the present invention Figure 1 ;

[0049] Figure 4 is a schematic diagram of the structure of the high-precision current acquisition circuit in an example of the present invention Figure 2 .

[0050] Explanation of reference numerals:

[0051] 1 - Control module;

[0052] 101 - First control unit;

[0053] 102 - Second control unit;

[0054] 2 - First acquisition module;

[0055] 200 - Zeroth MOS transistor;

[0056] 201 - First MOS transistor;

[0057] 202 - Second MOS transistor;

[0058] 203 - Third MOS transistor;

[0059] 204 - Fourth MOS transistor;

[0060] 205 - Fifth MOS transistor;

[0061] 206 - Sixth MOS transistor;

[0062] 207 - Seventh MOS transistor;

[0063] 3 - Second acquisition module;

[0064] 301 - Second power transistor;

[0065] 4-Op Amp Module Specific Embodiment

[0066] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0067] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0068] The following will detail the technical solutions of the present invention with specific embodiments. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0069] Before filing this application, the applicant conducted a full study on the current acquisition circuit and gave based on the study Figure 1 the current acquisition circuit in the prior art shown, for Figure 1 the current acquisition circuit shown, the existing problems are as follows:

[0070] Since the offset voltage of the op amp is fixed, there is always an input offset voltage V OS error of the op amp between Va and Vb. In addition, since the proportional K value is fixed, usually this fixed K value is relatively large. When collecting a small current, if the mirror current is still reduced according to the same ratio, it will make the Vos of this op amp occupy a large proportion in the collected current under the same input offset voltage Vos, and ultimately lead to poor accuracy of the collected current.

[0071] Regarding the influence of the input offset voltage V OS of the op amp, specifically, please refer to Figure 1, M2 is the acquisition mirror tube with an internal resistance of R2, and M0 is the target tube for collecting current with an internal resistance of R0. The internal resistance calculation formula of the MOS tube is

[0072] Specifically, in the ideal state, V a = V b . In practice, V a - V b = V OS , that is, the input offset voltage V OS of the operational amplifier. According to the internal resistance formula of the MOS tube, we can get: K = R2 / R0 = (W / L)0 / (W / L)2. It can be seen that the value of K depends on the size ratio of the power tube.

[0073] According to V a - V b = V OS , I0 = (Vin - V b ) / R0, I2 = (Vin - V a ) / R2, we can get:

[0074] I2 = [Vin - (V b - V OS )] / R2

[0075] = [(Vin - V b ) + V OS / R2

[0076] = (I0 R0 / R2) + (V OS / R2)

[0077] = I0 / K + V OS / R2;

[0078] From the above formula, it can be seen that when the collected current I0 is small, if the value of K is large, the error caused by the input offset voltage V OS of the operational amplifier has a greater impact on the collected current I2, which will further lead to a deterioration of the acquisition accuracy.

[0079] In an example, if K = 1000 and I0 = 1A, then I2 = 1mA + V OS / R2; if K = 100 and I0 = 1A, then I2 = 10mA + V OS / R2;

[0080] It can be seen that when the value of K is small, the proportion of V OS / R2 in the collected current value I2 is small, and the impact on the acquisition accuracy is small.

[0081] It can be seen that when collecting small currents, if the K value remains large, the collection accuracy will be very low, making the error caused by Vos dominant; while reducing the K value can weaken the error caused by Vos and improve the collection accuracy.

[0082] Please refer to Figure 2 , Figure 2 The current collection circuit shown mainly uses R1 to convert the current on Q1 into voltage V+, and then obtains the voltage VOUT containing current information through an operational amplifier, and finally uses VOUT as the subsequent signal source for processing.

[0083] For Figure 2 the current collection circuit in the prior art shown, the existing problems are as follows:

[0084] 1. When the output current is large, the power consumption of the collection circuit is large;

[0085] 2. The collection accuracy is mainly determined by the internal collection resistor, and the resistance value of this resistor is greatly affected by the process and is not suitable for integration inside the chip.

[0086] 3. The requirement for the accuracy of the operational amplifier is higher than that of the Figure 1 operational amplifier used in

[0087] In view of this, the present invention proposes a new current collection circuit, which can achieve the above effects without overly demanding the accuracy of the operational amplifier.

[0088] Regarding the solution of the present invention, the specific description is as follows:

[0089] Please refer to Figure 3 , the present invention provides a high-precision current collection circuit, and the high-precision current collection circuit includes: a control module 1, a first collection module 2, a second collection module 3, and an operational amplifier module 4; the high-precision current collection circuit is used to collect the current information flowing through the first collection module 2; the first collection module 2 and the second collection module 3 form a mirror current collection structure; the second collection module 3 includes a second power transistor 301; the first collection module 2 includes N first power transistors, and the sizes of the N first power transistors are different so that the ratio of the size of each first power transistor to the size of the second power transistor 301 is different; where N is a positive integer and N≥2.

[0090] The output end of the control module 1 is connected to the first input end of the first collection module 2, the second input end of the control module 1 is connected to the second input end of the first collection module 2 and the input end of the second collection module 3, the output end of the first collection module 2 is connected to the first input end of the operational amplifier module 4, and the output end of the second collection module 3 is connected to the second input end of the operational amplifier module 4.

[0091] Among them, the control module 1 is used to select several first power tubes among the N first power tubes as the selected power tubes; and is used to control the working states of the second power tube 301 and the selected power tubes.

[0092] Among them, the first current reference information I1 flowing through the first acquisition module 2 and the first current reference information I2 flowing through the second acquisition module 3 satisfy:

[0093] I2 = I1 / k; where k is the size ratio of the selected power tube to the second power tube.

[0094] There is an input offset voltage between the voltages of the first input terminal and the second input terminal of the operational amplifier module 4. The control module 1 adjusts the K value by switching different first power tubes as the selected power tubes, so as to weaken the acquisition error caused by the input offset voltage and improve the acquisition accuracy.

[0095] Among them, the second current reference information flowing through the second acquisition module 3 satisfies: I3 = I2 + V os / R2; V os is the input offset voltage, and R2 is the internal resistance of the second acquisition module 3.

[0096] In a specific embodiment, the second current reference information I3 flowing through the second acquisition module 3 and the first current reference information I2 flowing through the second acquisition module 3 are the same type of current reference information. Specifically, I2 is the signal in the ideal state and is not affected by the offset voltage V os of the operational amplifier, while I3 is affected by the offset voltage V os of the operational amplifier and is the second current reference information in the actual situation.

[0097] In a preferred implementation manner, the current collected by the first acquisition module 2 is the acquisition current value in the ideal state, and the current collected by the second acquisition module 3 is the acquisition current value in the actual situation.

[0098] In other preferred embodiments, the types of the first power tube and the second power tube 301 are the same.

[0099] Regarding the operational amplifier module 4, in an example, the operational amplifier module 4 adopts a five-transistor operational amplifier.

[0100] Of course, the present invention is not limited thereto, and other forms of operational amplifiers are within the protection scope of the present invention.

[0101] In the above solution, when the operational amplifier V os remains unchanged, by changing the K value, and then reducing V osThe proportion in the collected current, thereby improving the collection accuracy of the current.

[0102] Regarding the first acquisition module 2, in a preferred embodiment, the N first power tubes are arranged in sequence, and the size of the first power tube ranked as the i-th satisfies: S i = X i , where S i is the size of the i-th first power tube, X is a natural number, and X ≥ 2, 1 ≤ i ≤ N.

[0103] In an example, the first acquisition module 2 and the second acquisition module 3 adopt PMOS devices. Among them, the PMOS size array design of the first acquisition module 2, for example, adopts 2 N , N = 8 design scheme, and other ratios such as 3 N 、4 N etc. are not elaborated here.

[0104] In a specific embodiment, please refer to Figure 4 , the first acquisition module 2 includes: a first MOS tube 201, a second MOS tube 202, a third MOS tube 203, a fourth MOS tube 204, a fifth MOS tube 205, a sixth MOS tube 206, a seventh MOS tube 207;

[0105] Among them, the sources and drains of the first MOS tube 201 to the seventh MOS tube 207 are respectively connected to the source and drain of the second power tube 301, and the gates of the first MOS tube 201 to the seventh MOS tube 207 are all connected to the output end of the control module 1;

[0106] The gate of the second power tube 301 is connected to the second control signal input end.

[0107] In other embodiments, the first acquisition module 2 is configured to:

[0108] Collect the first current reference information I1 flowing through the first acquisition module;

[0109] Based on I1 and k, determine the first current reference information I2 flowing through the second acquisition module;

[0110] Transmit the first current reference information I2 = I1 / k flowing through the second acquisition module to the second acquisition module 3 and the operational amplifier module 4.

[0111] Regarding the selection of the type of power transistor, in other specific cases, the first acquisition module 2 and the second acquisition module 3 use NMOS as the power transistor. The difference between the NMOS transistor and the above PMOS transistor as the power transistor lies in: the gate voltage for driving the NMOS power transistor; the NMOS transistor needs to raise the gate voltage through a charge pump or other boost circuit to ensure the conduction of the power transistor, that is, the GC (i.e., the second control signal input terminal) for controlling the gate signal of the power transistor requires an additional boost circuit compared to the above PMOS transistor as the power transistor; where GC represents the main control line signal.

[0112] Regarding the first acquisition module, in other preferred embodiments, the first acquisition module 2 further includes a zero MOS transistor 200. The source and drain of the zero MOS transistor 200 are connected in parallel to the second power transistor 301, and the gate of the zero MOS transistor 200 is connected to the second control signal input terminal of the control module 1 to control the operating state of the zero MOS transistor 200 through the signal at the second control signal input terminal.

[0113] In other embodiments not shown, the gate of the zero MOS transistor 200 can also be connected to the output terminal of the control module 1 to perform selective control on the zero MOS transistor 200 through the control module 1.

[0114] Of course, the present invention is not limited thereto. Other connection methods of the gate of the zero MOS transistor 200 or other methods capable of controlling the zero MOS transistor 200 are within the protection scope of the present invention.

[0115] Thus, it can be seen that the control module 1 is used to control the operating states of the second power transistor 301, the zero MOS transistor 200, and the first MOS transistor 201 to the seventh MOS transistor 207.

[0116] The control module 1 is further configured to: obtain the minimum value of k based on the ratio of the size of the zero MOS transistor 200 to the size of the second power transistor 301, and the minimum value of k represents the value that satisfies the minimum current acquisition accuracy.

[0117] Regarding the control module 1, please refer to Figure 4 , the control module 1 includes: a first control unit 101 and a second control unit 102. The first control unit 101 includes a first control signal input terminal, and the second control unit 102 includes a second control signal input terminal;

[0118] Among them, the output end of the first control unit 101 is connected to the input end of the second control unit 102; the first control unit 101 is used to select some of the N first power tubes as the selected power tubes; the second control unit 102 is used to control the operating states of the second power tube 301 and the selected power tubes.

[0119] In a preferred embodiment, the first control unit 101 includes an encoder, and the second control unit 102 includes a switching circuit;

[0120] The control module 1 is configured as follows: the encoder generates the first control signal through different permutations and combinations and sends it to the switching circuit to select some of the N first power tubes as the selected power tubes; the switching circuit receives the first control signal and the second input control signal to control the operating states of the selected power tubes and the zero MOS tube and drive the second power tube 301.

[0121] Among them, the number of the first control signals is determined by the number of power tubes in the first acquisition module 2.

[0122] Of course, the present invention is not limited thereto, and other circuits capable of controlling the first acquisition module 2 and the second acquisition module 3 are within the protection scope of the present invention.

[0123] In other preferred embodiments, the switching circuit includes a first switch to a seventh switch.

[0124] Of course, the present invention is not limited thereto, the number of the switching circuits is the same as the number of the first power tubes, and other numbers of the switching circuits are within the protection scope of the present invention.

[0125] The control module 1 is further configured as follows: the second input control signal controls the operating states of the second power tube 301 and the zero MOS tube, and the first switch to the seventh switch respectively control the operating states of the first MOS tube 201 to the seventh MOS tube 207.

[0126] Specifically, the control module 1 is further configured to obtain a k value based on the ratio of the size of the selected power tubes in the first acquisition module 2 to the size of the second power tube 301.

[0127] Regarding the k value, in a specific embodiment, the k value is the ratio result of the sum of the aspect ratios of the zero MOS tube 200 and some of the selected power tubes among the first MOS tube 201 to the seventh MOS tube 207 to the aspect ratio of the second power tube; specifically, k = [(W / L) M0 +(W / L)M1～M 7] / (W / L) 第二功率管 。

[0128] Regarding the second acquisition module 3, please refer to Figure 4 , the second acquisition module 3 is configured to:

[0129] Obtain the first current reference information I2 = I1 / k flowing through the second acquisition module;

[0130] Based on the first current reference information I2, V flowing through the second acquisition module os and R2, determine the second current reference information I3 = I2 + V os / R2.

[0131] Regarding the second input control signal, in a preferred embodiment, the second input control signal is the main control line signal GC, and the main control line signal GC is generated by other control circuits, and this control circuit can adjust the GC signal value according to the system state, thereby adjusting the current flowing through the power tube in the first acquisition module 2.

[0132] In an example, the main control line signal GC is characterized by the states of 0 and 1 in a digital circuit.

[0133] Of course, the present invention is not limited thereto, and all analog values adjusted by other analog control circuits according to the system state are within the protection scope of the present invention.

[0134] In a specific embodiment, the first control signal is Iset. If the first control signal Iset is 0000001, it means that the first control unit 101 selects the first switch, and transmits the above-mentioned second input control signal GC to the output end of the control module 1, that is, the output signal of the control module 1 is 1111 11GC. Therefore, the selected power tube is the first MOS tube M1;

[0135] The devices actually and effectively participating in current acquisition are M1, the zero MOS tube M0, and the second power tube 301.

[0136] Based on the ratio of the sizes of the second power tube 301 and M1, M0, the K value is obtained.

[0137] In the above scheme, GC is the gate voltage for the first acquisition module 2 and the second acquisition module 3, where 1 represents a high level and can completely turn off the power tube.

[0138] It can be seen that in the above solution, the control module selects several first power transistors among the N first power transistors as the selected power transistors and controls the operating states of the selected power transistors, so as to obtain the size ratio k between the selected power transistors and the second power transistor. Since the sizes of the N first power transistors are all different and the value of k is also different, the control module can adjust the value of k by controlling different first power transistors to conduct, so as to weaken the acquisition error caused by the input offset voltage and improve the acquisition accuracy.

[0139] The present invention also provides an electronic device, including the high-precision current acquisition circuit described above.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-precision current acquisition circuit, characterized in that, The high-precision current acquisition circuit includes: a control module, a first acquisition module, a second acquisition module, and an operational amplifier module; the high-precision current acquisition circuit is used to acquire the current information flowing through the first acquisition module; the first acquisition module and the second acquisition module form a mirror acquisition current structure; the second acquisition module includes a second power transistor; the first acquisition module includes N first power transistors with different sizes, so that the ratio of the size of each first power transistor to the size of the second power transistor is different; where N is a positive integer and N≥2; The output end of the control module is connected to the first input end of the first acquisition module, the second input end of the control module is connected to the second input end of the first acquisition module and the input end of the second acquisition module, the output end of the first acquisition module is connected to the first input end of the operational amplifier module, and the output end of the second acquisition module is connected to the second input end of the operational amplifier module; The control module is used to select several of the N first power transistors as selected power transistors; and to control the working states of the second power transistor and the selected power transistors; Wherein, the first current reference information I1 flowing through the first acquisition module and the first current reference information I2 flowing through the second acquisition module satisfy: I2 = I1 / k; where k is the size ratio of the selected power transistor to the second power transistor; There is an input offset voltage between the voltages at the first input end and the second input end of the operational amplifier module. The control module adjusts the K value by switching different first power transistors as the selected power transistors to weaken the acquisition error caused by the input offset voltage and improve the acquisition accuracy; Among them, the second current reference information flowing through the second acquisition module satisfies: I3 = I2 + V os / R2; where V os is the input offset voltage, and R2 is the internal resistance of the second acquisition module; Among them, the N first power tubes are arranged in sequence in order, and the size of the first power tube ranked as the i-th satisfies: S i = X i , where S i is the size of the i-th first power tube, X is a natural number, and X ≥ 2, 1 ≤ i ≤ N.

2. The high-precision current acquisition circuit according to claim 1, wherein The control module includes: a first control unit and a second control unit. The first control unit includes a first control signal input end, and the second control unit includes a second control signal input end; Wherein, the output end of the first control unit is connected to the input end of the second control unit; The first control unit is used to select several of the N first power transistors as selected power transistors; The second control unit is used to control the working states of the second power transistor and the selected power transistors.

3. The high-precision current acquisition circuit according to claim 2, wherein The first acquisition module includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; Wherein, the source and drain of the first MOS transistor to the seventh MOS transistor are respectively connected to the source and drain of the second power transistor, the gates of the first MOS transistor to the seventh MOS transistor are all connected to the output end of the control module, and the gate of the second power transistor is connected to the second control signal input end of the control module.

4. The high-precision current acquisition circuit according to claim 3, characterized in that, The first control unit includes an encoder, and the second control unit includes a switching circuit; The control module is configured as: The encoder generates the first control signal through different permutations and combinations and sends it to the switching circuit to select several of the N first power transistors as selected power transistors; The switching circuit receives the first control signal and the second control signal to control the operating state of the selected power transistor and drive the second power transistor.

5. The high-precision current acquisition circuit according to claim 4, characterized in that The switching circuit includes a first switch to a seventh switch; The control module is further configured to: The first switch to the seventh switch respectively control the operating states of several MOS transistors among the first MOS transistor to the seventh MOS transistor.

6. The high-precision current acquisition circuit according to claim 5, wherein, The control module is further configured to: Based on the ratio of the size of the selected power transistor to the size of the second power transistor in the first acquisition module, obtain the k value.

7. The high-precision current acquisition circuit according to claim 6, wherein The first acquisition module is configured to: Obtain the first current reference information I1 flowing through the first acquisition module; Based on I1 and k, determine the first current reference information I2 flowing through the second acquisition module; Transmit the first current reference information I2 = I1 / k flowing through the second acquisition module to the second acquisition module and the operational amplifier module.

8. The high-precision current acquisition circuit according to claim 7, wherein The second acquisition module is configured to: Obtain the first current reference information I2 = I1 / k flowing through the second acquisition module; Based on the first current reference information I2 and V flowing through the second acquisition module os and R2, determine the second current reference information I3 = I2 + V os / R2 flowing through the second acquisition module.

9. The high-precision current acquisition circuit according to claim 8, wherein The first acquisition module further includes a zero MOS transistor, the source and drain of the zero MOS transistor are connected in parallel to the second power transistor, and the gate of the zero MOS transistor is connected to the second control signal input terminal of the control module; The control module is further configured to: Based on the ratio of the size of the zero MOS transistor to the size of the second power transistor, obtain the minimum value of k, and the minimum value of k represents the value that satisfies the minimum current acquisition accuracy.

10. The high-precision current acquisition circuit according to claim 9, characterized in that The types of the first power transistor and the second power transistor are the same.

11. An electronic device, characterized in that, Including the high-precision current acquisition circuit according to any one of claims 1 to 10.

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