Power supply voltage detector, power supply voltage detection device, system and medium

Abstract

Provided are a power supply voltage detection device, system, detector, and detection method. The device is connected to an integrated circuit power supply network and includes: a power supply voltage detector comprising: N buffers, wherein the input of a first buffer is connected to a clock signal, and the outputs of the other buffers are interconnected with the inputs of adjacent buffers; N latch chains, each comprising M latches, wherein the clock input of each latch is connected to the clock signal, the D terminal of the first latch of each latch chain is connected to the output of the corresponding buffer, and the Q terminals of the other latches are interconnected with the D terminals of the adjacent latches, M and N being positive integers, the VDD terminal of each latch being connected to a region in the integrated circuit power supply network where the power supply voltage is to be detected, and the ground terminal of each latch being connected to ground; and a voltage regulation module connected to the Q terminal of each latch and configured to detect the data output of each latch to determine the magnitude of the power supply voltage.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more particularly, to a supply voltage detector, a supply voltage detection device, a system, and a computer-readable medium. Background Art

[0002] Integrated circuits (ICs) require an external voltage source via voltage pins to operate. This external voltage source is connected to various latch circuits via the IC's internal power network. ICs fabricated at 55nm and below often incorporate hundreds of millions of latch circuits. When a large number of latch circuits in a single region of the IC flip simultaneously or when the operating frequency increases, the load on that region increases, potentially causing the supply voltage in that region to drop below expectations. Furthermore, when the IC is subject to power supply noise, its supply voltage can also fluctuate.

[0003] Voltage droop is a term used to describe the drop in voltage from the expected level when a power supply is driving a load. In integrated circuits, the output voltage may drop when the load increases suddenly and rapidly. For example, transient load conditions can cause voltage droop. If the voltage droop is too severe, it can lead to circuit failure.

[0004] Therefore, it is necessary to monitor the supply voltage inside the integrated circuit in real time and issue a warning signal in time when the voltage is lower than expected, prompting the voltage regulation module to adjust the voltage. Of course, there is also a need to adjust the voltage when the voltage is higher than expected. Summary of the Invention

[0005] According to one or more embodiments of the present disclosure, a power supply voltage detection device is provided, which is connected to an integrated circuit power supply network, comprising: a power supply voltage detector, comprising a buffer string, comprising N buffers, wherein the input terminal of the first buffer is connected to the clock signal, the output terminal of the first buffer is connected to the input terminal of the second buffer, and the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, where N and n are positive integers, and n is greater than 1 and less than N; N latch chains, each latch chain comprising M latches, the clock input terminal of each latch being connected to the clock signal, and the data input terminal of the first latch of each latch chain being connected to the N buffers. The output end of a corresponding buffer in the latch chain is connected, the data output end of the first latch is connected to the data input end of the second latch, the data output end of the mth latch is connected to the data input end of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power input VDD end of each latch is connected to the area where the power supply voltage is to be detected in the power supply network of the integrated circuit, and the ground end of each latch is connected to the ground; and a voltage regulation module is connected to the data output end of each latch of each latch in each latch chain, and is configured to detect the data output of each latch to determine the size of the power supply voltage of the area where the power supply voltage is to be detected in the power supply network of the integrated circuit.

[0006] According to one or more embodiments of the present disclosure, a power supply voltage detection system is provided, comprising: a plurality of power supply voltage detection devices according to embodiments of the present disclosure connected to multiple regions of an integrated circuit power network.

[0007] According to one or more embodiments of the present disclosure, a power supply voltage detector is provided, comprising a buffer string including N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain including M latches, a clock input terminal of each latch is connected to a clock signal, a data input terminal of a first latch in each latch chain is connected to an output terminal of a corresponding buffer in the N buffers, a data output terminal of the first latch is connected to a data input terminal of a second latch, and a data output terminal of the mth latch is connected to a data input terminal of an m+1th latch, M and m are positive integers, m is greater than 1 and less than M, a power supply input VDD terminal of each latch is connected to a region in a power supply network of an integrated circuit where a power supply voltage is to be detected, and a ground terminal of each latch is connected to ground.

[0008] According to one or more embodiments of the present disclosure, a power supply voltage detection method is provided, including: providing a power supply voltage detector, including a buffer string, including N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain including M latches, a clock input terminal of each latch is connected to a clock signal, a data input terminal of a first latch in each latch chain is connected to an output terminal of a corresponding buffer in the N buffers, a data output terminal of the first latch is connected to a data input terminal of a second latch, and a data output terminal of an mth latch is connected to a data input terminal of an m+1th latch, M and m are positive integers, m is greater than 1 and less than M, a power supply input VDD terminal of each latch is connected to a region in a power supply network of an integrated circuit where a power supply voltage is to be detected, and a ground terminal of each latch is connected to ground; and detecting the data output of each latch to determine the magnitude of the power supply voltage of the region in the power supply network of the integrated circuit where the power supply voltage is to be detected.

[0009] According to one or more embodiments of the present disclosure, a computer-readable medium is provided, on which a computer program is stored. When the program is executed by a processor, the power supply voltage detection method of the present disclosure is implemented.

[0010] The advantages of the technical solution of this application compared to the existing technology include but are not limited to:

[0011] 1. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, this structure uses a purely digital structure and can be implemented using devices in the standard cell library. It can be directly synthesized and is very friendly to the integrated circuit design process;

[0012] 2. This structure has a high response frequency and can output a voltage detection result in each clock cycle;

[0013] 3. This structure has high detection accuracy. At an operating frequency of 1.5GHz, it can achieve a voltage change detection accuracy of about 6mV;

[0014] 4. This structure can adapt to different operating frequencies without the need for additional delay adjustment circuits;

[0015] 5. This structure requires only minimal area overhead and has little impact on the original integrated circuit design.

[0016] 6. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, without the need for special access to an ideal power supply, and are easy to integrate in the back end of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A block diagram of a power supply voltage detection system according to an embodiment of the present disclosure is shown.

[0019] Figure 2 A block diagram of a power supply voltage detection device according to an embodiment of the present disclosure is shown.

[0020] Figure 3 A schematic diagram showing the structure of a power supply voltage detector according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A timing diagram of a clock signal and input signals at data input terminals of each latch in a latch chain according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A flow chart of a power supply voltage detection method according to an embodiment of the present disclosure is shown.

[0023] Figure 6A An embodiment of the step of detecting the data output of each latch to determine the magnitude of the supply voltage of the region where the supply voltage is to be detected in the power supply network of the integrated circuit according to an embodiment of the present disclosure is shown.

[0024] Figure 6B Another embodiment of the step of detecting the data output of each latch to determine the magnitude of the supply voltage of the region where the supply voltage is to be detected in the power supply network of the integrated circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 7 A flowchart showing the specific steps of obtaining the delay range of each latch in multiple latch chains based on the logic value strings of multiple latch chains and the high level time length of the clock signal according to an embodiment of the present disclosure is shown.

[0026] Figure 8 A flow chart of a power supply voltage detection method according to another embodiment of the present disclosure is shown.

[0027] Figure 9 A block diagram of an exemplary computer system suitable for implementing embodiments of the present disclosure is shown.

[0028] Figure 10A schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure is shown.

[0029] Figure 11A and Figure 11B The range constraints of the four latch chains and the range constraint of the first latch chain are respectively shown as the representation of the x and y value ranges on the two-dimensional coordinate axis. DETAILED DESCRIPTION

[0030] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that the disclosure is not intended to be limited to the described embodiments. On the contrary, it is intended to cover variations, modifications, and equivalents within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method steps described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0031] Figure 1 FIG. 3 is a block diagram of a power supply voltage detection system according to an embodiment of the present disclosure, wherein the power supply voltage detection system includes power supply voltage detection devices 101 , 102 , . . . , X connected to multiple regions of a power supply network of an integrated circuit chip 100 .

[0032] The power supply voltage detection devices 101, 102, ..., X connected to multiple areas can be distributed in different areas of the power supply network inside the integrated circuit chip 100, and can detect voltage fluctuations in each area in real time. These areas may include different areas in the intellectual property core (IP core) 11, 12 and the customized circuit 13. Generally speaking, if the IP core is relatively large, then the area that is frequently working is more susceptible to interference from power supply noise, and a power supply voltage detection device can be connected to such an area. Alternatively, the area where the power supply voltage detection device is distributed can be obtained through prior simulation. Through simulation, it is understood which areas have a higher workload and may have a larger voltage drop, and then the power supply voltage detection device is connected to these areas.

[0033] Figure 2 FIG. 2 shows a block diagram of a power supply voltage detection device 200 according to an embodiment of the present disclosure.

[0034] The supply voltage detection device 200 is connected to the integrated circuit power supply network 23 , and includes a supply voltage detector 21 and a voltage regulation module 22 .

[0035] The power supply voltage detector 21 includes a buffer string 201, which includes N buffers, wherein the input terminal of the first buffer is connected to the clock signal, the output terminal of the first buffer is connected to the input terminal of the second buffer, and the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains 202, each latch chain includes M latches, the clock input terminal of each latch is connected to the clock signal, the data input terminal of the first latch of each latch chain is connected to the output terminal of a corresponding buffer in the N buffers, the data output terminal of the first latch is connected to the data input terminal of the second latch, and the data output terminal of the mth latch is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power input VDD terminal of each latch is connected to the area where the power supply voltage is to be detected in the integrated circuit power supply network 23, and the ground terminal of each latch is connected to the ground.

[0036] The voltage regulating module 22 is connected to the data output of each latch in each latch chain and is configured to detect the data output of each latch to determine the magnitude of the supply voltage of the region where the supply voltage is to be detected in the integrated circuit power network 23 .

[0037] The structure of the supply voltage detector 21 primarily utilizes a digital circuit device, a latch, to indirectly measure the integrated circuit's supply voltage. A latch is a level-sensitive storage unit circuit. When the latch is triggered and enabled, its output changes with the input. After the enable signal ends, the latch stores the signal at the time of the enable until the next enable. The time delay from the latch's data input (D) to its data output (Q) is also affected by the supply voltage.

[0038] Figure 3 FIG. 1 is a schematic diagram showing the structure of the power supply voltage detector 21 according to an embodiment of the present disclosure.

[0039] like Figure 3 As shown, the supply voltage detector 21 includes a buffer string 201 including N buffers and N latch chains 202 .

[0040] In N buffers, the input of the first buffer is connected to the clock signal. The output of the first buffer is connected to the input of the second buffer. The output of the first buffer is also connected to the data input (D) of the first latch in the first latch chain. Here, the first buffer before the data input of the first latch can delay the clock signal by the delay time of one buffer before inputting it to the data input of the first latch as the data input signal. This is to stagger the rising edge of the data input signal of the first latch and the clock enable signal, avoiding the generation of metastable states due to inconsistent setup time.

[0041] The output of the second buffer is connected to the input of the third buffer, and so on. The output of the nth buffer is connected to the input of the n+1th buffer, where N and n are positive integers, and n is greater than 1 and less than N. The output of the Nth buffer is connected to the data input (D terminal) of the first latch in the Nth latch chain.

[0042] In the N latch chains 202, each latch chain includes M latches, the clock input terminal (CLK terminal) of each latch is connected to the clock signal, the data input terminal (D terminal) of the first latch in each latch chain is connected to the output terminal of a corresponding buffer among the N buffers, the data output terminal (Q terminal) of the first latch is connected to the data input terminal (D terminal) of the second latch, the data output terminal (Q terminal) of the mth latch is connected to the data input terminal (D terminal) of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power input VDD terminal of each latch is connected to the area where the power supply voltage is to be detected in the integrated circuit power network 23, and the ground terminal (GND) of each latch is connected to the ground.

[0043] That is, in a latch chain, the clock inputs of all latches are connected to a clock signal. This same clock signal passes through a buffer and is then connected to the data input of the first latch (here, the first latch is the latch closest to the buffer). The data output of the first latch is connected to the data input of the second latch, the data output of the second latch is connected to the data input of the third latch, and so on. The data output of the (m-1)th latch is connected to the data input of the (m)th latch, the data output of the (m)th latch is connected to the data input of the (m+1)th latch, and so on. The data output of each latch is connected to a voltage regulator module.

[0044] In one embodiment, N is the result of dividing the delay of a single latch by the delay of a single buffer, rounded up. The value of N is determined by considering how many buffers the clock signal can pass through within the delay of a latch. In one embodiment, M is greater than or equal to 1 times the result of dividing the period of the clock signal by the delay of a single latch. In a more preferred embodiment, M is greater than or equal to 1.5 times the result of dividing the period of the clock signal by the delay of a single latch. A larger value of M can show the specific range of the transmission delay of the input signal in the latch chain. Assuming that the delay of a latch at normal voltage (or rated voltage) is about 100ps and the delay of a buffer at normal voltage (or rated voltage) is about 30ps, then N=4 and M=10.

[0045] Note that the RSTB reset terminal of each latch can receive a reset signal to reset the latch. The QN terminal of each latch outputs a signal opposite to the signal output by the data output terminal Q and can be left floating.

[0046] It has been observed that voltage levels affect latch delay. When the voltage is below normal, the latch delay increases, potentially causing it to malfunction. When the voltage is above normal, the latch delay decreases, resulting in increased power consumption. Therefore, consideration has been given to using the number of latches in a latch chain that a clock signal can propagate within a clock cycle to detect voltage levels, indicating whether the voltage has dropped or risen compared to the normal voltage (or a predetermined voltage).

[0047] In one embodiment, the voltage regulation module obtains a logic value according to a comparison between a data output of each latch and a reference level to obtain a logic value string of each latch chain.

[0048] In one embodiment, if the data output of the latch is higher than a reference level, the logic value is a first value, and if the data output of the latch is lower than the reference level, the logic value is a second value.

[0049] Figure 4 A timing diagram of a clock signal and input signals at data input terminals of each latch in a latch chain according to an embodiment of the present disclosure is shown.

[0050] Assume that all latches are enabled at a high level. When the clock signal (clk) is high, the clock signal can be transmitted from the data input of the latch, passing through the data input of the first, second, and pth latches in sequence until the clock signal becomes low. At this time, the values ​​stored and output by the first p latches are high, that is, higher than or equal to the reference level, which is a logic '1' (the first value is 1), while the values ​​stored and output by the last (mp) latches are low, that is, lower than the reference level, which is a logic '0' (the second value is 0). That is, the level output by the data output of the first p latches is higher than or equal to the reference level, while the level output by the data output of the last (mp) latches is lower than the reference level. The logical value string of this latch chain is a string of p 1s and (mp) 0s.

[0051] When the supply voltage of the latch chain fluctuates, the latch delay will also fluctuate. When the voltage is lower than the normal voltage, the latch delay will become longer, and when the voltage is higher than the normal voltage, the latch delay will become shorter. Therefore, for the same clock signal, the number p of latches that store a logical '1' value after one measurement will also change. For example, when the voltage is 1.05V, higher than 1V, the latch delay becomes shorter, and the more latches the clock signal can propagate within one clock cycle, p is 8; and when the voltage is 0.9V, lower than 1V, the latch delay becomes longer, and the fewer latches the clock signal can propagate within one clock cycle, p is 4. Therefore, the present application uses the number of first values ​​in the logical value string composed of the values ​​output by each latch in a latch chain, that is, the change in p, to indirectly reflect the change in the supply voltage.

[0052] In one embodiment, the voltage regulation module determines the supply voltage level of a region in the integrated circuit power network where the supply voltage is to be detected based on the logic value strings of the N latch chains and the relationship between the values ​​of the logic value strings of the N latch chains and the supply voltage level. In one embodiment, the relationship between the values ​​of the logic value strings of the N latch chains and the supply voltage level is obtained through experimental measurement.

[0053] In other words, since it is known that when the supply voltage of a latch chain fluctuates, the latch delay will also fluctuate, causing the number of first values ​​in the logical value string composed of the values ​​output by each latch in a latch chain, i.e., p, to change, a series of experiments can be conducted to measure the relationship between the value of p and the voltage in each of N latch chains. For example, by inputting low voltages, 0.9V, 0.95V, etc., into the latch chain, the value of p in each of the N latch chains at different low voltages can be obtained. The same applies to high voltages. A mapping table can be generated between voltage and the value of p in each of the N latch chains. In this way, the supply voltage of the region in the integrated circuit power network where the supply voltage is to be detected can be quickly determined from the logical value strings of the N latch chains and the relationship between the values ​​of the logical value strings of the N latch chains and the supply voltage (e.g., by generating a mapping table), or the magnitude of the voltage droop can be directly determined.

[0054] Alternatively, in another embodiment, the voltage regulation module obtains the delay range of each latch in the multiple latch chains based on the logic value strings of the multiple latch chains and the time length of the high level of the clock signal; obtains the actual delay range of a single latch based on the delay range of each latch in the multiple latch chains; and determines the size of the power supply voltage of the area in the integrated circuit power network where the power supply voltage is to be detected based on the relationship between the actual delay range of the single latch and the size of the power supply voltage.

[0055] First, according to the logic value strings of the multiple latch chains and the duration of the high level of the clock signal, the delay range of each latch in the multiple latch chains can be obtained in the following manner.

[0056] In a first embodiment, the voltage regulation module is configured to obtain the delay range of each latch in the multiple latch chains according to the logic value strings of the multiple latch chains and the time length of the high level of the clock signal through the following steps: determining the number of first values ​​in the logic value strings in a predetermined latch chain; determining the number of buffers between a predetermined latch chain and the input clock signal; determining the time length of the high level of the clock signal to be greater than the sum of the product of the number of buffers and the delay of a single buffer and the product of the number of first values ​​and the delay of a single latch, and less than the sum of the product of the number of buffers before the latch chain and the delay of a single buffer and the product of the number of first values ​​plus 1 and the delay of a single latch; and calculating to obtain the actual delay range of the single latch.

[0057] Specifically, due to the relatively high latency of a single latch, if only a single latch chain is used for monitoring, the voltage detection accuracy will be relatively low, that is, the value of p will only change when the voltage changes significantly. To improve monitoring accuracy, this application uses N latch chains, all of which are enabled using the same clock signal, so all latches have the same test time, namely one clock cycle.

[0058] In addition, this clock signal is input to the data input terminals of each latch in the first latch chain through a buffer. This buffer is mainly used to prevent metastable states caused by failure to meet the latch setup time. It is then input to the data input terminals of each latch in the second latch chain through a second buffer, and then to the data input terminals of each latch in the third latch chain through a third buffer, and so on. It is input to the data input terminals of each latch in the Nth latch chain through the Nth buffer. In this way, the input signal of each latch chain is delayed by the delay of one buffer.

[0059] Since the voltage level will affect the delay of the latch and the buffer, the following demonstrates the relationship between the high-level duration of the clock signal and the delay of the latch and the buffer, as well as the principle that using N latch chains can achieve higher detection accuracy.

[0060] Assume that the power supply voltage is a certain value (for example, 0.95V), the corresponding delay of a latch is 100ps, the delay of a buffer is 30ps, N = 4, M = 10, and the clock signal enables four latch chains once in one clock cycle. The logical values ​​of the data stored in the four latch chains are 1111110000, 1111110000, 1111100000, and 1111100000. Then, within one clock cycle, the actual transmission delay of the input signal (i.e., the duration of the clock signal's high level) should meet the following conditions:

[0061] For the first latch chain, the actual transmission delay of the input signal (i.e., the duration of the high level of the clock signal) is greater than the sum of the product of the number of buffers and the delay of a single buffer and the product of the number of first values ​​and the delay of a single latch (i.e., >6*100+1*30=630ps), and less than the sum of the product of the number of buffers and the delay of a single buffer before the latch chain and the product of the number of first values ​​plus 1 and the delay of a single latch; the transmission delay of the input signal is calculated to be (i.e., <7*100+1*30=730ps), that is, between 630ps and 730ps. For the second latch chain, the transmission delay of the input signal (i.e., the duration of the high level of the clock signal) (i.e., >6*100+2*30=660ps and <7*100+2*30=760ps) is between 660ps and 730ps. s-760ps, for the third latch chain, the propagation delay of the input signal (i.e., the duration of the high level of the clock signal) (i.e., >5*100+3*30=590ps and <6*100+3*30=690ps) is between 590ps-690ps, and for the fourth latch chain, the propagation delay of the input signal (i.e., the duration of the high level of the clock signal) (i.e., >5*100+4*30=620ps and <6*100+4*30=720ps) is between 620ps-720ps. Since these four latch chains are input with the same input signal, it can be determined that the actual propagation delay of the input signal (i.e., the duration of the high level of the clock signal) is constrained by the four ranges calculated for the four latch chains, that is, ultimately constrained between 660ps-690ps.

[0062] Therefore, compared with using a single latch chain (which can only obtain, for example, between 630ps and 730ps), the accuracy of detecting the actual transmission delay of the input signal (i.e., the duration of the high level of the clock signal) is greatly improved (can obtain, for example, between 660ps and 690ps).

[0063] Of course, the above examples are merely intended to illustrate the relationship between the delay of a single latch, the delay of a single buffer, and the actual transmission delay of the input signal (i.e., the duration of the high level of the clock signal). The present application aims to obtain the delay of a single latch, thereby determining the magnitude of the power supply voltage. Therefore, even when the magnitude of the power supply voltage is unknown, and the delay of a single latch and the delay of the buffer under such a power supply voltage are also unknown, since the duration of the high level of the input clock signal is known, the range of the delay of a single latch can be derived and determined using the same formulas and relationships as in the above examples.

[0064] Specifically, in actual test use, the present application adopts a fixed input signal (clock signal), that is, the time length of the high level of the known input clock signal. By determining the length of the path that the fixed input signal can transmit (corresponding to the time length of the high level of the input clock signal), the delay range of a single latch is determined.

[0065] For example, assume that the high-level enable signal length of the clock signal (i.e., the time length of the high level) is 500 ps (for example, a clock signal with a 50% duty cycle and a period of 1000 ps). Still, taking N = 4 and M = 10 from the relationship between the delay of the latch and the delay of the buffer under normal voltage. Assume that the delay of a single buffer under the current supply voltage is x, and the delay of a single latch is y (at this time, x and y are uncertain because the supply voltage is not necessarily the normal voltage). After the clock signal is enabled once (lasting for the time length of a high level), the data stored in the four latch chains are 1111110000, 1111110000, 1111100000, and 1111100000 respectively.

[0066] Then, according to the relationships obtained from the above example, it can be judged that for the first latch chain, x + 5y < 500 ps < x + 6y; for the second latch chain, 2x + 5y < 500 ps < 2x + 6y; for the third latch chain, 3x + 4y < 500 ps < 3x + 5y; for the fourth latch chain, 4x + 4y < 500 ps < 4x + 5y.

[0067] According to the range constraints of the above four latch chains, after transformation, we get:

[0068]

[0069] where ∧ is the logical AND function. After further transformation, we get:

[0070]

[0071]

[0072]

[0073] It can be obtained that:

[0074]

[0075] where the value ranges of x and y are shown on the two-dimensional coordinate axis as Figure 11A shown:

[0076] It is obtained that the range of the delay y of a single latch is 75 ps < y < 100 ps.

[0077] In contrast, for the first latch chain, the constraints x + 5y < 500ps < x + 6y and x > 0 only give:

[0078]

[0079] The value ranges of x and y are shown on the two-dimensional coordinate axis as Figure 11B shown:

[0080] It is only possible to determine that the range of the delay y of a single latch on the first latch chain is 0ps < y < 100ps.

[0081] Therefore, using multiple latch chains for testing can significantly improve the accuracy of measuring the delay of a single latch.

[0082] At different supply voltages, the delay of the latch will change. In one embodiment, the relationship between the actual delay range of a single latch and the magnitude of the supply voltage can be obtained through experimental measurement. For example, by testing the output results of N latch chains at different supply voltages, the actual delay range of a single latch can be calculated, enabling the tester to establish a lookup table that maps the actual delay range of a single latch to the corresponding supply voltage. In actual use, based on the output results of the N latch chains, the actual delay range of a single latch is calculated, and the current supply voltage is inferred in reverse according to the lookup table, and the voltage regulation unit is made to perform corresponding regulation.

[0083] In one embodiment, the voltage regulation module is configured to: when the determined supply voltage is lower than the predetermined voltage, increase the supply voltage to compensate for voltage droop, or when the determined supply voltage is higher than the predetermined voltage, decrease the supply voltage to compensate for voltage rise. That is to say, in this embodiment, the voltage regulation module can not only detect whether there is voltage droop, but also increase the voltage in the area to compensate for the voltage droop according to the judged magnitude of the voltage droop. Of course, the voltage regulation module can also lower the voltage to maintain the voltage at the target voltage based on the inferred supply voltage being higher than the target voltage.

[0084] Note that the RSTB reset terminal of each latch can receive a reset signal to reset the latch.

[0085] In one embodiment, the N latch chains in the supply voltage detector are enabled on the rising edge of the clock signal and output data on the falling edge of the clock signal. After outputting the data, each latch is reset by the reset signal. Then, it is enabled on the rising edge of the next clock signal, outputs data and is reset on the falling edge of the clock signal, and so on. This structure conducts tests when the clock is high, outputs test results when the clock is low, and resets all latches, waiting for the next test.

[0086] To improve response speed, two latch chains can be used, measuring during the high and low clock periods, respectively, and then outputting test results during the low and high clock periods, so that two test results are output per clock cycle. This allows detection of very short voltage drop or rise pulses. Specifically, in an alternative embodiment, the supply voltage detector further includes N additional latch chains and N additional buffers with the same structure as the N latch chains. The N latch chains are enabled on the rising edge of the clock signal and output data on the falling edge of the clock signal. After the data is output, the latches in these N latch chains are reset by a reset signal. Furthermore, the N additional latch chains are enabled on the falling edge of the clock signal and output data on the rising edge of the clock signal. After the data is output, the latches in these N latch chains are reset by a reset signal.

[0087] The advantages of the technical solution of this application compared to the existing technology include but are not limited to:

[0088] 1. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, this structure uses a purely digital structure and can be implemented using devices in the standard cell library. It can be directly synthesized and is very friendly to the integrated circuit design process;

[0089] 2. This structure has a high response frequency and can output a voltage detection result in each clock cycle;

[0090] 3. This structure has high detection accuracy. At an operating frequency of 1.5GHz, it can achieve a voltage change detection accuracy of about 6mV;

[0091] 4. This structure can adapt to different operating frequencies without the need for additional delay adjustment circuits;

[0092] 5. This structure requires only minimal area overhead and has little impact on the original integrated circuit design.

[0093] 6. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, without the need for special access to an ideal power supply, and are easy to integrate in the back end of the integrated circuit.

[0094] Figure 5A flow chart of a power supply voltage detection method 500 according to an embodiment of the present disclosure is shown. The method 500 includes: step 501, providing a supply voltage detector, comprising a buffer string, including N buffers, wherein the input terminal of the first buffer is connected to the clock signal, the output terminal of the first buffer is connected to the input terminal of the second buffer, and the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain including M latches, the clock input terminal of each latch is connected to the clock signal, the data input terminal of the first latch of each latch chain is connected to the output terminal of a corresponding buffer in the N buffers, the data output terminal of the first latch is connected to the data input terminal of the second latch, and the data output terminal of the mth latch is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power input VDD terminal of each latch is connected to the region in the integrated circuit power network where the power supply voltage is to be detected, and the ground terminal of each latch is connected to ground; and step 502, detecting the data output of each latch to determine the magnitude of the power supply voltage of the region in the integrated circuit power network where the power supply voltage is to be detected.

[0095] Here, the first buffer before the data input terminal of the first latch can delay the clock signal by the delay time of a buffer, and then input it into the data input terminal of the first latch as the data input signal. This is to stagger the rising edge of the data input signal of the first latch and the clock enable signal to avoid metastable state due to failure to meet the setup time.

[0096] Note that the RSTB reset terminal of each latch can receive a reset signal to reset the latch. The QN terminal of each latch is left floating.

[0097] In this way, the size of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network can be determined by detecting the data output of each latch. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a purely digital structure and can be implemented using devices in the standard cell library. It can be directly synthesized and is very friendly to the integrated circuit design process. This structure has a high response frequency and can output a voltage detection result in each clock cycle; this structure has high detection accuracy and can achieve a voltage change detection accuracy of approximately 6mV at an operating frequency of 1.5GHz; this structure can adapt to different operating frequencies without the need for additional delay adjustment circuits; this structure only requires a very small area overhead and has little impact on the original integrated circuit design. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, without the need to specifically connect to an ideal power supply, and are easy to integrate in the back end of the integrated circuit.

[0098] In one embodiment, the relationship between the actual delay range of a single latch and the power supply voltage is obtained through experimental measurement, or the relationship between the values ​​of the logic value strings of N latch chains and the power supply voltage is obtained through experimental measurement.

[0099] In one embodiment, N is the ceiling of the delay of a single latch divided by the delay of a single buffer.

[0100] In one embodiment, M is greater than or equal to one times the result of dividing the period of the clock signal by the delay of a single latch.

[0101] In one embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch.

[0102] Assume that a certain value of the power supply voltage is known, and correspondingly, the delay of a latch is 100 ps, ​​and the delay of a buffer is 30 ps, ​​and N=4 and M=10.

[0103] Figure 6A An embodiment of the step of detecting the data output of each latch to determine the magnitude 502 of the supply voltage of a region in the power supply network of the integrated circuit to be detected according to an embodiment of the present disclosure is shown.

[0104] In this embodiment, the step of detecting the data output of each latch to determine the magnitude of the power supply voltage of the region where the power supply voltage is to be detected in the power supply network of the integrated circuit 502 includes:

[0105] Step 5021, obtaining a logic value according to the comparison between the data output of each latch and the reference level to obtain a logic value string of each latch chain;

[0106] Step 5022: Determine the power supply voltage of the region where the power supply voltage is to be detected in the integrated circuit power network based on the logic value strings of the N latch chains and the relationship between the values ​​of the logic value strings of the N latch chains and the power supply voltage.

[0107] In one embodiment, if the data output of the latch is higher than a reference level, the logic value is a first value, and if the data output of the latch is lower than the reference level, the logic value is a second value. For example, if the data output of the latch is higher than or equal to the reference level, the logic value is a first value (a first value of 1), while if the data output of the latch is lower than the reference level, the logic value is a second value of 0.

[0108] After the clock signal enables the four latch chains once within one clock cycle, the logic values ​​of the data stored in the four latch chains are 1111110000, 1111110000, 1111100000, and 1111100000. If the relationship between the values ​​of the logic value strings of the N latch chains and the power supply voltage is previously determined through experimental measurement, for example, if the logic values ​​of the data stored in the four latch chains are previously determined through experimental measurement to be 1111110000, 11111100000, 1111100000, and 1111100000, the power supply voltage is 0.95V.

[0109] In this way, the supply voltage of the region in the integrated circuit power network where the supply voltage is to be detected can be determined to be 0.95V based directly on the logical value strings of the N latch chains (1111110000, 1111110000, 1111100000, 1111100000) and the relationship between the logical value strings of the N latch chains and the supply voltage. This solution is convenient and quick.

[0110] Figure 6B Another embodiment of the step of detecting the data output of each latch to determine the magnitude 502 of the supply voltage of the region to be detected in the power supply network of the integrated circuit according to an embodiment of the present disclosure is shown.

[0111] In this embodiment, the step of detecting the data output of each latch to determine the magnitude of the power supply voltage of the region where the power supply voltage is to be detected in the power supply network of the integrated circuit 502 includes:

[0112] Step 5021′, obtaining a logic value according to the comparison between the data output of each latch and the reference level to obtain a logic value string of each latch chain;

[0113] Step 5022′, obtaining the delay range of each latch in the multiple latch chains according to the logic value strings of the multiple latch chains and the duration of the high level of the clock signal;

[0114] Step 5023', obtaining the actual delay range of a single latch based on the delay ranges of the respective latches in the multiple latch chains;

[0115] Step 5024': Determine the power supply voltage of the region where the power supply voltage is to be detected in the power supply network of the integrated circuit based on the relationship between the actual delay range of the single latch and the power supply voltage.

[0116] Figure 7A flowchart showing the specific steps of obtaining the delay range 5022' of each latch in multiple latch chains according to the logical value string of the multiple latch chains and the duration of the high level of the clock signal in accordance with an embodiment of the present disclosure.

[0117] The step 5022' of obtaining the delay range of each latch in multiple latch chains according to the logical value string of the multiple latch chains and the duration of the high level of the clock signal includes:

[0118] Step 50221', determining the number of first values in the logical value string in a predetermined latch chain;

[0119] Step 50222', determining the number of buffers existing between a predetermined latch chain and the input clock signal;

[0120] Step 50223', determining that the duration of the high level of the clock signal is greater than the sum of the product of the number of buffers and the delay of a single buffer and the product of the number of first values and the delay of a single latch, and less than the sum of the product of the number of buffers before this latch chain and the delay of a single buffer and the product of the number of first values plus 1 and the delay of a single latch;

[0121] Step 50224', calculating to obtain the actual delay range of a single latch.

[0122] For example, assume that the high level enable signal length of the clock signal (i.e., the duration of the high level) is 500 ps. N = 4, M = 10, assume that the delay of a single buffer under the current supply voltage is x, and the delay of a single latch is y. After the clock signal is enabled once (lasting for the duration of a high level), the data stored in the 4 latch chains are 1111110000, 1111110000, 1111100000, 1111100000 respectively.

[0123] Then, according to the relationships obtained from the above example, it can be judged that for the first latch chain, x + 5y < 500 ps < x + 6y; for the second latch chain, 2x + 5y < 500 ps < 2x + 6y; for the third latch chain, 3x + 4y < 500 ps < 3x + 5y; for the fourth latch chain, 4x + 4y < 500 ps < 4x + 5y.

[0124] The obtained range of the delay y of a single latch is 75 ps < y < 100 ps.

[0125] If the relationship between the actual delay range of a single latch and the magnitude of the supply voltage is measured through experiments in advance, for example, when the actual delay range of a single latch is 75 ps < y < 100 ps and the supply voltage is 0.95 V, then the magnitude of the supply voltage in the area where the supply voltage needs to be detected in the integrated circuit power network can be directly determined according to the relationship between the actual delay range of the single latch and the magnitude of the supply voltage as 0.95 V. This method is convenient and fast.

[0126] Figure 8 FIG. 4 shows a flowchart of a supply voltage detection method 500 according to another embodiment of the present disclosure.

[0127] In this embodiment, in addition to steps 501 and 502, the supply voltage detection method 500 may further include: step 503, according to the determined magnitude of the supply voltage, when the determined supply voltage is lower than the predetermined voltage, raising the supply voltage to compensate for voltage droop, or when the determined supply voltage is higher than the predetermined voltage, lowering the supply voltage to compensate for voltage rise.

[0128] Thus, not only can the magnitude of the supply voltage be detected, but also voltage regulation can be performed according to the magnitude relationship between the supply voltage and the predetermined voltage to stabilize the supply voltage at the predetermined voltage. Of course, this solution is not limited thereto. After detecting the magnitude of the supply voltage, other voltage regulations may also be performed, or other processes may be carried out using the magnitude of the supply voltage, which will not be elaborated here one by one.

[0129] In one embodiment, the N latch chains in the supply voltage detector are enabled on the rising edge of the clock signal and output data and are reset on the falling edge of the clock signal. Thus, within one clock cycle, one detection and output can be performed.

[0130] Alternatively, in another embodiment, the supply voltage detector further includes another N latch chains and another N buffers having the same structure as the N latch chains, and the N latch chains are enabled on the rising edge of the clock signal, output data and are reset on the falling edge of the clock signal, and the other N latch chains are enabled on the falling edge of the clock signal and output data and are reset on the rising edge of the clock signal. In this way, two sets of latch chains are used to measure during the high and low levels of the clock respectively, and then the test results are output during the low and high levels of the clock, so as to output two test results within each clock cycle, which can improve the response speed and can also detect voltage droop pulses or voltage rise pulses with very short durations.

[0131] In summary, the advantages of the technical solution of the present application compared with the prior art include but are not limited to:

[0132] 1. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, this structure uses a purely digital structure and can be implemented using devices in the standard cell library. It can be directly synthesized and is very friendly to the integrated circuit design process;

[0133] 2. This structure has a high response frequency and can output a voltage detection result in each clock cycle;

[0134] 3. This structure has high detection accuracy. At an operating frequency of 1.5GHz, it can achieve a voltage change detection accuracy of about 6mV;

[0135] 4. This structure can adapt to different operating frequencies without the need for additional delay adjustment circuits;

[0136] 5. This structure requires only minimal area overhead and has little impact on the original integrated circuit design.

[0137] 6. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, without the need for special access to an ideal power supply, and are easy to integrate in the back end of the integrated circuit.

[0138] Figure 9 A block diagram of an exemplary computer system suitable for implementing embodiments of the present disclosure is shown.

[0139] The computer system may include a processor (H1); a memory (H2) coupled to the processor (H1) and storing computer-executable instructions therein for performing the steps of various methods of the embodiments of the present disclosure when executed by the processor.

[0140] The processor (H1) may include, but is not limited to, one or more processors or microprocessors, etc.

[0141] The memory (H2) may include, but is not limited to, for example, random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (such as hard disk, floppy disk, solid-state drive, removable disk, CD-ROM, DVD-ROM, Blu-ray disc, etc.).

[0142] In addition, the computer system may also include a data bus (H3), an input / output (I / O) bus (H4), a display (H5), and input / output devices (H6) (eg, keyboard, mouse, speakers, etc.).

[0143] The processor (H1) can communicate with external devices (H5, H6, etc.) through an I / O bus (H4) via a wired or wireless network (not shown).

[0144] The memory (H2) may also store at least one computer-executable instruction for executing various functions and / or steps of methods in the embodiments described in the present technology when the processor (H1) executes the instruction.

[0145] In one embodiment, the at least one computer executable instruction can also be compiled into or constitute a power supply voltage detection software product, wherein the one or more computer executable instructions are executed by a processor to perform the various functions and / or method steps in the embodiments described in this technology.

[0146] Figure 10 A schematic diagram of a non-transitory computer-readable storage medium according to an embodiment of the present disclosure is shown.

[0147] like Figure 10 As shown, instructions are stored on the computer-readable storage medium 1020, and the instructions are, for example, computer-readable instructions 1010. When the computer-readable instructions 1010 are executed by the processor, the power supply voltage detection method described with reference to the above figures can be executed. The computer-readable storage medium includes, but is not limited to, for example, volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. For example, the computer-readable storage medium 1020 can be connected to a computing device such as a computer, and then, when the computing device executes the computer-readable instructions 1010 stored on the computer-readable storage medium 1020, the power supply voltage detection method described above can be performed.

[0148] Of course, the above-mentioned specific embodiments are merely examples and not limitations, and those skilled in the art can, based on the concept of the present disclosure, merge and combine some steps and devices from the various embodiments described separately above to achieve the effects of the present disclosure. Such merged and combined embodiments are also included in the present disclosure, and such merges and combinations are not described one by one here.

[0149] Note that the advantages, strengths, and effects mentioned in this disclosure are merely examples and not limitations, and should not be construed as necessarily possessed by each embodiment of this disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, not limitations, and the aforementioned details do not necessarily limit this disclosure to the use of these specific details.

[0150] According to one or more embodiments of the present disclosure, a power supply voltage detection device is provided, which is connected to an integrated circuit power supply network, comprising: a power supply voltage detector, comprising a buffer string, comprising N buffers, wherein the input terminal of the first buffer is connected to the clock signal, the output terminal of the first buffer is connected to the input terminal of the second buffer, and the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, where N and n are positive integers, and n is greater than 1 and less than N; N latch chains, each latch chain comprising M latches, the clock input terminal of each latch being connected to the clock signal, and the data input terminal of the first latch of each latch chain being connected to the N buffers. The output end of a corresponding buffer in the latch chain is connected, the data output end of the first latch is connected to the data input end of the second latch, the data output end of the mth latch is connected to the data input end of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power input VDD end of each latch is connected to the area where the power supply voltage is to be detected in the power supply network of the integrated circuit, and the ground end of each latch is connected to the ground; and a voltage regulation module is connected to the data output end of each latch of each latch in each latch chain, and is configured to detect the data output of each latch to determine the size of the power supply voltage of the area where the power supply voltage is to be detected in the power supply network of the integrated circuit.

[0151] In one embodiment, the voltage regulation module is configured to: obtain a logic value based on a comparison between the data output of each latch and a reference level to obtain a logic value string for each latch chain; determine the magnitude of the supply voltage of an area in the integrated circuit power supply network where the supply voltage is to be detected based on the logic value strings of the N latch chains and the relationship between the values ​​of the logic value strings of the N latch chains and the magnitude of the supply voltage; or the voltage regulation module is configured to: obtain a logic value based on a comparison between the data output of each latch and a reference level to obtain a logic value for each latch chain; obtain a delay range of each latch in the multiple latch chains based on the logic value strings of the multiple latch chains and the duration of the high level of the clock signal; obtain an actual delay range of a single latch based on the delay ranges of the respective latches in the multiple latch chains; and determine the magnitude of the supply voltage of an area in the integrated circuit power supply network where the supply voltage is to be detected based on the relationship between the actual delay range of the single latch and the magnitude of the supply voltage.

[0152] In one embodiment, if the data output of the latch is higher than a reference level, the logical value is a first value; if the data output of the latch is lower than the reference level, the logical value is a second value. The voltage regulation module is configured to obtain the delay range of each latch in the multiple latch chains according to the logical value strings of the multiple latch chains and the high level time length of the clock signal through the following steps: determining the number of first values ​​in the logical value strings in a predetermined latch chain; determining the number of buffers between a predetermined latch chain and the input clock signal; determining the high level time length of the clock signal to be greater than the sum of the product of the number of buffers and the delay of a single buffer and the product of the number of first values ​​and the delay of a single latch, and less than the sum of the product of the number of buffers before the latch chain and the delay of a single buffer and the product of the number of first values ​​plus 1 and the delay of a single latch; and calculating the actual delay range of a single latch.

[0153] In one embodiment, the voltage regulation module is configured to: based on the size of the determined supply voltage, increase the supply voltage to compensate for voltage sag when the determined supply voltage is lower than a predetermined voltage, or reduce the supply voltage to compensate for voltage rise when the determined supply voltage is higher than the predetermined voltage.

[0154] In one embodiment, the relationship between the actual delay range of a single latch and the power supply voltage is obtained through experimental measurement, or the relationship between the values ​​of the logic value strings of N latch chains and the power supply voltage is obtained through experimental measurement.

[0155] In one embodiment, N is the ceiling of the delay of a single latch divided by the delay of a single buffer.

[0156] In one embodiment, M is greater than or equal to one times the result of dividing the period of the clock signal by the delay of a single latch.

[0157] In one embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch.

[0158] In one embodiment, the N latch chains in the supply voltage detector are enabled at the rising edge of the clock signal and output data and reset at the falling edge of the clock signal; or the supply voltage detector further includes another N latch chains and another N buffers having the same structure as the N latch chains, and the N latch chains are enabled at the rising edge of the clock signal and output data and reset at the falling edge of the clock signal, and the other N latch chains are enabled at the falling edge of the clock signal and output data and reset at the rising edge of the clock signal.

[0159] According to one or more embodiments of the present disclosure, a power supply voltage detection system is provided, comprising: a plurality of power supply voltage detection devices according to embodiments of the present disclosure connected to multiple regions of an integrated circuit power network.

[0160] According to one or more embodiments of the present disclosure, a power supply voltage detector is provided, comprising a buffer string including N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain including M latches, a clock input terminal of each latch is connected to a clock signal, a data input terminal of a first latch in each latch chain is connected to an output terminal of a corresponding buffer in the N buffers, a data output terminal of the first latch is connected to a data input terminal of a second latch, and a data output terminal of the mth latch is connected to a data input terminal of an m+1th latch, M and m are positive integers, m is greater than 1 and less than M, a power supply input VDD terminal of each latch is connected to a region in a power supply network of an integrated circuit where a power supply voltage is to be detected, and a ground terminal of each latch is connected to ground.

[0161] According to one or more embodiments of the present disclosure, a power supply voltage detection method is provided, including: providing a power supply voltage detector, including a buffer string, including N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain including M latches, a clock input terminal of each latch is connected to a clock signal, a data input terminal of a first latch in each latch chain is connected to an output terminal of a corresponding buffer in the N buffers, a data output terminal of the first latch is connected to a data input terminal of a second latch, and a data output terminal of an mth latch is connected to a data input terminal of an m+1th latch, M and m are positive integers, m is greater than 1 and less than M, a power supply input VDD terminal of each latch is connected to a region in a power supply network of an integrated circuit where a power supply voltage is to be detected, and a ground terminal of each latch is connected to ground; and detecting the data output of each latch to determine the magnitude of the power supply voltage of the region in the power supply network of the integrated circuit where the power supply voltage is to be detected.

[0162] In one embodiment, detecting the data output of each latch to determine the magnitude of the power supply voltage of the area in the integrated circuit power supply network where the power supply voltage is to be detected includes: obtaining a logic value based on a comparison of the data output of each latch with a reference level to obtain a logic value string for each latch chain; and determining the magnitude of the power supply voltage of the area in the integrated circuit power supply network where the power supply voltage is to be detected based on the logic value strings of the N latch chains and the relationship between the values ​​of the logic value strings of the N latch chains and the magnitude of the power supply voltage.

[0163] Alternatively, in another embodiment, detecting the data output of each latch to determine the magnitude of the power supply voltage of the area in the integrated circuit power network where the power supply voltage is to be detected includes: obtaining a logic value based on a comparison of the data output of each latch with a reference level to obtain a logic value string for each latch chain; obtaining a delay range of each latch in the multiple latch chains based on the logic value strings of the multiple latch chains and the time length of the high level of the clock signal; obtaining an actual delay range of a single latch based on the delay range of each latch in the multiple latch chains; and determining the magnitude of the power supply voltage of the area in the integrated circuit power network where the power supply voltage is to be detected based on a relationship between the actual delay range of the single latch and the magnitude of the power supply voltage.

[0164] In one embodiment, if the data output of the latch is higher than a reference level, the logical value is a first value; if the data output of the latch is lower than the reference level, the logical value is a second value. The voltage regulation module is configured to obtain the delay range of each latch in the multiple latch chains according to the logical value strings of the multiple latch chains and the high level time length of the clock signal through the following steps: determining the number of first values ​​in the logical value strings in a predetermined latch chain; determining the number of buffers between a predetermined latch chain and the input clock signal; determining the high level time length of the clock signal to be greater than the sum of the product of the number of buffers and the delay of a single buffer and the product of the number of first values ​​and the delay of a single latch, and less than the sum of the product of the number of buffers before the latch chain and the delay of a single buffer and the product of the number of first values ​​plus 1 and the delay of a single latch; and calculating the actual delay range of a single latch.

[0165] In one embodiment, the method further includes: according to the magnitude of the determined supply voltage, increasing the supply voltage to compensate for voltage sag when the determined supply voltage is lower than a predetermined voltage, or decreasing the supply voltage to compensate for voltage rise when the determined supply voltage is higher than the predetermined voltage.

[0166] In one embodiment, the relationship between the actual delay range of a single latch and the power supply voltage is obtained through experimental measurement, or the relationship between the values ​​of the logic value strings of N latch chains and the power supply voltage is obtained through experimental measurement.

[0167] In one embodiment, N is the ceiling of the delay of a single latch divided by the delay of a single buffer.

[0168] In one embodiment, M is greater than or equal to one times the result of dividing the period of the clock signal by the delay of a single latch.

[0169] In one embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch.

[0170] In one embodiment, the N latch chains in the supply voltage detector are enabled at the rising edge of the clock signal and output data and reset at the falling edge of the clock signal; or the supply voltage detector further includes another N latch chains and another N buffers having the same structure as the N latch chains, and the N latch chains are enabled at the rising edge of the clock signal and output data and reset at the falling edge of the clock signal, and the other N latch chains are enabled at the falling edge of the clock signal and output data and reset at the rising edge of the clock signal.

[0171] According to one or more embodiments of the present disclosure, a computer-readable medium is provided, on which a computer program is stored. When the program is executed by a processor, the power supply voltage detection method of the present disclosure is implemented.

[0172] The block diagrams of the devices, devices, equipment, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "include," "comprise," "have," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0173] The step flow charts and the above method descriptions in this disclosure are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order given. As will be appreciated by those skilled in the art, the order of the steps in the above embodiments can be performed in any order. Words such as "thereafter," "then," "next," and the like are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods. In addition, any reference to an element in the singular, such as using the articles "a," "an," or "the," is not to be construed as limiting the element to the singular.

[0174] In addition, the steps and devices in the various embodiments of this document are not limited to being implemented in a certain embodiment. In fact, according to the concepts of this disclosure, relevant partial steps and partial devices in the various embodiments of this document can be combined to conceive new embodiments, and these new embodiments are also included in the scope of this disclosure.

[0175] Each operation of the method described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including but not limited to hardware circuits, application specific integrated circuits (ASICs) or processors.

[0176] The various illustrated logic blocks, modules, and circuits may be implemented or described using a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but as an alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a microprocessor cooperating with a DSP core, or any other such configuration.

[0177] The steps of the method or algorithm described in conjunction with the present disclosure can be directly embedded in hardware, in a software module executed by a processor, or in a combination of the two. The software module can exist in any form of tangible storage medium. Some examples of storage media that can be used include random access memory (RAM), read-only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, etc. A storage medium can be coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative embodiment, the storage medium can be integral to the processor. A software module can be a single instruction or many instructions and can be distributed over several different code segments, between different programs, and across multiple storage media.

[0178] The methods disclosed herein include actions for implementing the described methods. Methods and / or actions may be interchangeable with one another without departing from the scope of the claims. In other words, unless a specific order of actions is specified, the order and / or use of specific actions may be modified without departing from the scope of the claims.

[0179] The above functions can be implemented by hardware, software, firmware or any combination thereof. If implemented in software, the functions can be stored as instructions on a tangible computer-readable medium. The storage medium can be any available tangible medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices or any other tangible medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy discs and Blu-ray discs, wherein disks usually reproduce data magnetically, while discs reproduce data optically using lasers.

[0180] Thus, a computer program product can perform the operations presented herein. For example, such a computer program product can be a computer-readable tangible medium having instructions tangibly stored (and / or encoded) thereon, the instructions being executable by a processor to perform the operations described herein. The computer program product can include packaging materials.

[0181] Software or instructions may also be transmitted via a transmission medium. For example, software may be transmitted from a website, server, or other remote source using a transmission medium such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, or microwave.

[0182] In addition, the modules and / or other appropriate means for carrying out the methods and techniques described herein can be downloaded and / or otherwise obtained by the user terminal and / or base station when appropriate. For example, such a device can be coupled to a server to facilitate the transmission of the means for carrying out the methods described herein. Alternatively, the various methods described herein can be provided via a storage component (e.g., RAM, ROM, a physical storage medium such as a CD or a floppy disk) so that the user terminal and / or base station can obtain the various methods when being coupled to the device or providing a storage component to the device. In addition, any other appropriate technology for providing the methods and techniques described herein to a device can be utilized.

[0183] Other examples and implementations are within the scope and spirit of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software performed by a processor, hardware, firmware, hardwiring, or any combination of these. Features that implement the functions can also be physically located in various locations, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein, including as used in the claims, "or" used in a list of items that begin with "at least one" indicates a separate list, so that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). In addition, the wording "exemplary" does not mean that the example described is preferred or better than other examples.

[0184] Various changes, substitutions, and modifications of the technology described herein may be made without departing from the teachings of the appended claims. Moreover, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, compositions of things, means, methods, and actions described above. Currently existing or later developed processes, machines, manufactures, compositions of things, means, methods, or actions that perform substantially the same function or achieve substantially the same results as the corresponding aspects described herein may be utilized. Accordingly, the appended claims include within their scope such processes, machines, manufactures, compositions of things, means, methods, or actions.

[0185] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0186] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A power supply voltage detection device connected to an integrated circuit power supply network, comprising: Supply voltage detector, including A buffer string comprising N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an (n+1)th buffer, where N and n are positive integers, and n is greater than 1 and less than N; N latch chains, each latch chain comprising M latches, a clock input terminal of each latch connected to the clock signal, a data input terminal of a first latch in each latch chain connected to an output terminal of a corresponding one of the N buffers, a data output terminal of the first latch connected to a data input terminal of a second latch, a data output terminal of the mth latch connected to a data input terminal of the m+1th latch, M and m being positive integers, m being greater than 1 and less than M, wherein M is greater than or equal to 2, a power input terminal VDD of each latch connected to a region of a power supply network of the integrated circuit where a supply voltage is to be detected, and a ground terminal of each latch connected to ground; and The voltage regulating module is connected to the data output terminal of each latch of each latch chain and is configured to detect the data output of each latch to determine the magnitude of the supply voltage of the area where the supply voltage is to be detected in the power supply network of the integrated circuit.

2. The power supply voltage detection device according to claim 1, wherein: The voltage regulation module is configured to: Obtaining a logic value according to the comparison between the data output of each latch and a reference level to obtain a logic value string of each latch chain; determining the magnitude of the supply voltage of the region in the power supply network of the integrated circuit where the supply voltage is to be detected based on the logic value strings of the N latch chains and a relationship between the values ​​of the logic value strings of the N latch chains and the magnitude of the supply voltage; or The voltage regulation module is configured to: Obtaining a logic value according to a comparison between the data output of each latch and the reference level to obtain a logic value string of each latch chain; Obtaining a delay range of each latch in the plurality of latch chains according to the logic value strings of the plurality of latch chains and the duration of the high level of the clock signal; Obtaining an actual delay range of a single latch according to the delay ranges of respective latches in the plurality of latch chains; The magnitude of the power supply voltage of the region where the power supply voltage is to be detected in the power supply network of the integrated circuit is determined according to the relationship between the actual delay range of the single latch and the magnitude of the power supply voltage.

3. The power supply voltage detection device according to claim 2, wherein: If the data output of the latch is higher than the reference level, the logic value is a first value; if the data output of the latch is lower than the reference level, the logic value is a second value. The voltage regulating module is configured to obtain a delay range of each latch in the plurality of latch chains according to the logic value strings of the plurality of latch chains and the duration of the high level of the clock signal through the following steps: determining the number of first values ​​in a predetermined string of logic values ​​in a latch chain; determining the number of buffers existing between the predetermined latch chain and the input clock signal; Determine that the length of time during which the clock signal remains at a high level is greater than the sum of the product of the number of buffers and the delay of a single buffer and the product of the number of first values ​​and the delay of a single latch, and is less than the sum of the product of the number of buffers before the latch chain and the delay of the single buffer and the product of the number of the first values ​​plus 1 and the delay of the single latch; The actual delay range of the single latch is obtained by calculation.

4. The power supply voltage detection device according to claim 2, wherein: The voltage regulation module is configured to: According to the magnitude of the determined supply voltage, the supply voltage is increased to compensate for voltage sag when the determined supply voltage is lower than a predetermined voltage, or the supply voltage is decreased to compensate for voltage rise when the determined supply voltage is higher than a predetermined voltage.

5. The power supply voltage detection device according to claim 2, wherein: The relationship between the actual delay range of the single latch and the magnitude of the power supply voltage is obtained through experimental measurement, or the relationship between the values ​​of the logic value strings of the N latch chains and the magnitude of the power supply voltage is obtained through experimental measurement.

6. The power supply voltage detection device according to claim 1, wherein: N is the ceiling of the delay of a single latch divided by the delay of a single buffer.

7. The power supply voltage detection device according to claim 1, wherein: M is greater than or equal to one times the result of dividing the period of the clock signal by the delay of a single latch.

8. The power supply voltage detection device according to claim 1, wherein: M is greater than or equal to 1.5 times the result of dividing the period of the clock signal by the delay of a single latch.

9. The power supply voltage detection device according to claim 1, wherein: The N latch chains in the supply voltage detector are enabled at a rising edge of a clock signal, and output data and are reset at a falling edge of the clock signal; or The supply voltage detector also includes another N latch chains and another N buffers having the same structure as the N latch chains, and the N latch chains are enabled at the rising edge of the clock signal, and output data and reset at the falling edge of the clock signal, and the another N latch chains are enabled at the falling edge of the clock signal, and output data and reset at the rising edge of the clock signal.

10. A power supply voltage detection system, comprising: A plurality of supply voltage detection devices according to claim 1 are connected to a plurality of regions of an integrated circuit power network.

11. A power supply voltage detector comprising A buffer string comprising N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an (n+1)th buffer, where N and n are positive integers, and n is greater than 1 and less than N; There are N latch chains, each latch chain includes M latches, the clock input terminal of each latch is connected to the clock signal, the data input terminal of the first latch of each latch chain is connected to the output terminal of a corresponding buffer among the N buffers, the data output terminal of the first latch is connected to the data input terminal of the second latch, and the data output terminal of the mth latch is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, where M is greater than or equal to 2, the power input VDD terminal of each latch is connected to the area of ​​the integrated circuit power network where the power supply voltage is to be detected, and the ground terminal of each latch is connected to the ground.

12. A method for detecting a power supply voltage, comprising: Provides supply voltage detectors, including A buffer string comprising N buffers, wherein an input terminal of a first buffer is connected to a clock signal, an output terminal of the first buffer is connected to an input terminal of a second buffer, and an output terminal of an nth buffer is connected to an input terminal of an (n+1)th buffer, where N and n are positive integers, and n is greater than 1 and less than N; N latch chains, each latch chain comprising M latches, a clock input terminal of each latch connected to the clock signal, a data input terminal of a first latch in each latch chain connected to an output terminal of a corresponding one of the N buffers, a data output terminal of the first latch connected to a data input terminal of a second latch, a data output terminal of the mth latch connected to a data input terminal of the m+1th latch, M and m being positive integers, m being greater than 1 and less than M, wherein M is greater than or equal to 2, a power input terminal VDD of each latch connected to a region of a power supply network of the integrated circuit where a supply voltage is to be detected, and a ground terminal of each latch connected to ground; and The data output of each latch is detected to determine the magnitude of the power supply voltage of the region where the power supply voltage is to be detected in the power supply network of the integrated circuit.

13. A computer-readable medium having a computer program stored thereon, wherein: When the program is executed by a processor, the power supply voltage detection method according to claim 12 is implemented.

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