Testing method and system

Abstract

The present invention provides a test method, which includes configuring the input delay attribute of the signal input interface and the output delay attribute of the signal output interface to be both empty, obtaining a first time delay difference between the first output clock signal and the input initial clock signal, configuring the input delay attribute of the signal input interface, obtaining a second time delay difference between the second output clock signal and the input initial clock signal, calculating the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference and the input delay attribute, configuring the output delay attribute of the signal output interface, obtaining a third time delay difference between the third output clock signal and the input initial clock signal, and calculating the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference and the output delay attribute, thereby avoiding errors caused by time delay differences of test boards and the like and improving the test accuracy. The present invention also discloses a test system.

Description

Technical Field

[0001] The present invention relates to the field of testing technologies, and particularly to a testing method and system. Background Art

[0002] Each IO module of a Field Programmable Gate Array (FPGA) device includes a programmable delay unit IODELAY. The IODELAY is a surrounding delay unit with fixed taps and has a calibrated tap resolution for adjusting the delay of input and output signals. The IODELAY can be used for a combinational input path, a register input path, a combinational output path, or a register output path, and can also be used in internal resources. It is used to change the independent delay or combinational delay of input and output signals. In practical applications, by using EDA software, a first path from IO input to output is established, tested and recorded as the first delay value T1, and through IO attribute constraints, the input delay attribute INDEL or the output delay attribute OUTDEL is modified to establish a second path, tested and recorded as the second delay T2, and the average delay of multiple taps can be obtained through calculation.

[0003] With the increase in the scale of FPGAs and the continuous improvement of IO interface rates, to meet the timing adjustment under various interface rates, the calibrated tap resolution of IODELAY has become smaller and smaller, reaching the ps level, and the number of delay switch stages that can be interconnected has also reached hundreds. Therefore, it is impossible to ensure the accuracy of input and output delay tests at each tap level.

[0004] Chinese Patent with publication number CN113848455A discloses a method for testing the delay of internal interconnections in an FPGA, including: for a selected area, determining input IOs and output IOs; configuring the FPGA for the first time to establish a first path between the input IOs and the output IOs, and then testing the time delay between the input IOs and the output IOs, denoted as the first time delay value T1. The first path is composed of M interconnected switches in cascade; configuring the FPGA for the second time to establish a second path between the input IOs and the output IOs, and then testing the time delay between the input IOs and the output IOs, denoted as the second time delay value T2. The second path is composed of N interconnected switches in cascade; calculating the average time delay of the interconnected switches in the selected area by the following formula: (T1 - T2) / (M - N), where both M and N are positive integers and M ≠ N. However, the delay of the internal interconnections in the FPGA is usually at the ns level, and the number of levels of the interconnected wiring can be read through EDA software. However, with the increase in the working frequency, the design of IODELAY is usually at the ps level. In the application of high-speed serial-to-parallel conversion, in order to adjust the sampling timing, the tap design specification of IODELAY is usually within 10 ps. For a time delay with such precision, EDA can no longer accurately report it. Moreover, the input and output time delay values of the FPGA IODELAY will change with the chip process, the working temperature, and the working voltage state. When the overall path T1 and T2 are much larger than the IODELAY value, EDA cannot obtain the actual working state of the chip, and the obtained T1 and T2 will have a large error, resulting in low test accuracy.

[0005] Therefore, it is necessary to provide a new testing method and system to solve the above problems existing in the prior art. Summary of the Invention

[0006] The purpose of the present invention is to provide a testing method and system, which improves the accuracy of testing.

[0007] To achieve the above purpose, the testing method of the present invention includes:

[0008] Instancing a signal input interface and a signal output interface on a test board, and inputting an initial clock signal to the signal input interface;

[0009] Instancing a connection line connecting the signal input interface and the signal output interface;

[0010] Configuring both the input delay attribute of the signal input interface and the output delay attribute of the signal output interface to be empty, receiving a first output clock signal from the signal output interface, and then obtaining a first time delay difference between the first output clock signal and the input initial clock signal;

[0011] Configure the input delay attribute of the signal input interface, receive the second output clock signal from the signal output interface, then obtain the second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute;

[0012] Configure the output delay attribute of the signal output interface, receive the third output clock signal from the signal output interface, then obtain the third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute.

[0013] The beneficial effect of the test method is as follows: Configure both the input delay attribute of the signal input interface and the output delay attribute of the signal output interface to be empty, receive the first output clock signal from the signal output interface, then obtain the first time delay difference between the first output clock signal and the input initial clock signal, configure the input delay attribute of the signal input interface, receive the second output clock signal from the signal output interface, then obtain the second time delay difference between the second output clock signal and the input initial clock signal, calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute, configure the output delay attribute of the signal output interface, receive the third output clock signal from the signal output interface, then obtain the third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute, avoiding errors caused by time delay differences such as test boards and improving the accuracy of the test.

[0014] Optionally, the signal input interface is a global clock signal input interface.

[0015] Optionally, the signal output interface is a global clock signal output interface.

[0016] Optionally, the connection directly connects the signal input interface and the signal output interface.

[0017] Optionally, the calculating the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute includes:

[0018] Obtain the difference between the second time delay difference and the first time delay difference to obtain a first difference, and then divide the first difference by the input delay attribute to obtain the average delay of the delay unit of the signal input interface.

[0019] Optionally, calculating the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute includes:

[0020] Obtaining the difference between the third time delay difference and the first time delay difference to obtain a second difference, and then dividing the second difference by the output delay attribute to obtain the average delay of the delay unit of the signal output interface.

[0021] The present invention also provides a test system, including:

[0022] An instantiation unit, configured to instantiate a signal input interface and a signal output interface on a test board, input an initial clock signal to the signal input interface; and also configured to instantiate a connection line connecting the signal input interface and the signal output interface;

[0023] A configuration unit, configured to configure the input delay attribute of the signal input interface and the delay output attribute of the signal output interface;

[0024] A calculation unit, configured to, when the input delay attribute of the signal input interface and the output delay attribute of the signal output interface configured by the configuration unit are both empty, receive a first output clock signal from the signal output interface, and then obtain a first time delay difference between the first output clock signal and the input initial clock signal; and also configured to, when the configuration unit configures the input delay attribute of the signal input interface, receive a second output clock signal from the signal output interface, and then obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute; and also configured to, when the configuration unit configures the output delay attribute of the signal output interface, receive a third output clock signal from the signal output interface, and then obtain a third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute.

[0025] The beneficial effects of the test system are as follows: When the input delay attribute of the signal input interface and the output delay attribute of the signal output interface configured by the configuration unit are both empty, the calculation unit receives the first output clock signal from the signal output interface, and then obtains the first time delay difference between the first output clock signal and the input initial clock signal; when the configuration unit configures the input delay attribute of the signal input interface, the calculation unit receives the second output clock signal from the signal output interface, and then obtains the second time delay difference between the second output clock signal and the input initial clock signal, and calculates the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute; when the configuration unit configures the output delay attribute of the signal output interface, the calculation unit receives the third output clock signal from the signal output interface, and then obtains the third time delay difference between the third output clock signal and the input initial clock signal, and calculates the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute, avoiding errors caused by time delay differences such as test boards and improving the accuracy of testing.

[0026] Optionally, the instantiation unit includes a first instantiation subunit and a second instantiation subunit. The first instantiation subunit is used to instantiate a signal input interface and a signal output interface on the test board, and the second instantiation subunit is used to instantiate a connection connecting the signal input interface and the signal output interface.

[0027] Optionally, the instantiation unit includes a signal generation unit for inputting an initial clock signal to the signal input interface.

[0028] Optionally, the calculation unit includes a signal receiving unit, a first calculation subunit, a second calculation subunit, and a third calculation subunit, which are used to receive the first output clock signal, the second output clock signal, and the third output clock signal from the signal output interface. The first calculation subunit is used to obtain the first time delay difference between the first output clock signal and the input initial clock signal. The second calculation subunit is used to obtain the second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute. The third calculation subunit is used to obtain the third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute. Description of the Drawings

[0029] Figure 1 It is a flowchart of the test method in some embodiments of the present invention;

[0030] Figure 2 It is the timing diagram of the signal in the test method in some embodiments of the present invention;

[0031] Figure 3 It is the structural block diagram of the test system in some embodiments of the present invention. Specific embodiments

[0032] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0033] In view of the problems existing in the prior art, embodiments of the present invention provide a test method, and the test method is applied to an FPGA chip. [[ID=[]] [[ID=[]]

[0034] Refer to Figure 1 , the test method includes the following steps:

[0035] S1: Instantiate a signal input interface and a signal output interface on a test board, and input an initial clock signal to the signal input interface;

[0036] S2: Instantiate a connection line connecting the signal input interface and the signal output interface;

[0037] S3: Configure the input delay attribute of the signal input interface and the output delay attribute of the signal output interface to be both empty, receive a first output clock signal from the signal output interface, and then obtain a first time delay difference between the first output clock signal and the input initial clock signal;

[0038] S4: Configure the input delay attribute of the signal input interface, receive a second output clock signal from the signal output interface, and then obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference and the input delay attribute;

[0039] S5: Configure the output delay attribute of the signal output interface, receive the third output clock signal from the signal output interface, then obtain the third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute. Herein, the order of step S4 and step S5 can be interchanged, and no specific limitation is made here.

[0040] In some embodiments, in the FPGA, each signal input interface and signal output interface includes a delay unit, which is a tap-around circuit with a certain quantity and calibration accuracy, and is used to connect to the input IOB module or the output IOB module to adjust the delay time of the input or output.

[0041] In some embodiments, the IOB module is an Input-Output Buffer, which is the interface part between the FPGA and the external circuit and is used to complete the driving and matching of the input and output signals under different electrical characteristics.

[0042] In some embodiments, the input delay attribute is an Input Delay parameter, which is used to control the number of delay units of the signal input interface; the output delay attribute is an Output Delay parameter, which is used to control the number of delay units of the signal output interface.

[0043] In some embodiments, the signal input interface instantiated on the test board is a global clock signal input interface, the signal output interface instantiated on the test board is a global clock signal output interface, and the connection directly connects the signal input interface and the signal output interface. The connection between the global clock signal input interface and the global clock signal output interface is automatically laid out on the global clock network (clocktree), so that the time delay from the signal input interface to the signal output interface is very small, facilitating the measurement of a more accurate time delay with the smallest time base.

[0044] In some specific embodiments, calculating the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute includes: obtaining the difference between the second time delay difference and the first time delay difference to obtain a first difference, and then dividing the first difference by the input delay attribute to obtain the average delay of the delay unit of the signal input interface. Obtaining the difference between the second time delay difference and the first time delay difference can directly eliminate the test error caused by the channel time delay difference of the test board, connecting wires, etc.

[0045] In some specific embodiments, calculating the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute includes: obtaining the difference between the third time delay difference and the first time delay difference to obtain a second difference, and then dividing the second difference by the output delay attribute to obtain the average delay of the delay unit of the signal output interface. Obtaining the difference between the third time delay difference and the first time delay difference can directly eliminate the test error caused by the channel delay difference of the test board, connection lines, etc.

[0046] Figure 2 is the timing diagram of the signal in the test method in some embodiments of the present invention. Refer to Figure 2 , in the figure, IOin represents the initial clock signal, IOout_NONE represents the first output clock signal, IOout_INDEL represents the second output clock signal, IOout_OUTDEL represents the third output clock signal, a represents the clock of the initial clock signal, b represents the clock of the first output clock signal, c represents the clock of the second output clock signal, d represents the clock of the third output clock signal, t1 represents the first time delay difference, t2 represents the second time delay difference, and t3 represents the third time delay difference.

[0047] Refer to Figure 2 , t1 = b - a, t2 = c - a, t3 = d - a. Then, obtain the difference between the second time delay difference and the first time delay difference to obtain a first difference, and then divide the first difference by the input delay attribute to obtain the average delay of the delay unit of the signal input interface. It is represented by the formula as (t2 - t1) / P, where P represents the input delay attribute; obtain the difference between the third time delay difference and the first time delay difference to obtain a second difference, and then divide the second difference by the output delay attribute to obtain the average delay of the delay unit of the signal output interface. It is represented by the formula as (t3 - t1) / Q, where Q represents the output delay attribute.

[0048] Figure 3 is the structural block diagram of the test system in some embodiments of the present invention. Refer to Figure 3 , the test system 100 includes an instantiation unit 101, a configuration unit 102, and a calculation unit 103.

[0049] Refer to Figure 3 , the instantiation unit 101 is used to instantiate a signal input interface and a signal output interface on the test board 104 and input an initial clock signal to the signal input interface.

[0050] In some embodiments, the instantiation unit 101 instantiates a signal input interface on the test board 104 as a global clock signal input interface, and all the signal output interfaces instantiated by the instantiation unit 101 on the test board 104 are global clock signal output interfaces. The test board is an FPGA chip.

[0051] Referring to Figure 3 , the instantiation unit 101 is further configured to instantiate a connection line connecting the signal input interface and the signal output interface. Specifically, the connection line directly connects the signal input interface and the signal output interface.

[0052] Referring to Figure 3 , the configuration unit 102 is configured to configure the input delay attribute of the signal input interface and the delay output attribute of the signal output interface.

[0053] Referring to Figure 3 , when the input delay attribute of the signal input interface and the output delay attribute of the signal output interface configured by the configuration unit 102 are both empty, the calculation unit 103 is configured to receive a first output clock signal from the signal output interface, and then obtain a first time delay difference between the first output clock signal and the input initial clock signal.

[0054] Referring to Figure 3 , when the configuration unit 102 configures the input delay attribute of the signal input interface, the calculation unit 103 is configured to receive a second output clock signal from the signal output interface, and then obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate an average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute.

[0055] Referring to Figure 3 , when the configuration unit 102 configures the output delay attribute of the signal output interface, the calculation unit 103 is configured to receive a third output clock signal from the signal output interface, and then obtain a third time delay difference between the third output clock signal and the input initial clock signal, and calculate an average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute.

[0056] In some embodiments, the instantiation unit includes a first instantiation subunit and a second instantiation subunit. The first instantiation subunit is configured to instantiate a signal input interface and a signal output interface on the test board, and the second instantiation subunit is configured to instantiate a connection line connecting the signal input interface and the signal output interface.

[0057] In some embodiments, the instantiation unit includes a signal generation unit configured to input an initial clock signal to the signal input interface. Specifically, the signal generation unit is a Signal Generator.

[0058] In some embodiments, the calculation unit includes a signal receiving unit, a first calculation subunit, a second calculation subunit, and a third calculation subunit, configured to receive the first output clock signal, the second output clock signal, and the third output clock signal from the signal output interface. The first calculation subunit is configured to obtain a first time delay difference between the first output clock signal and the input initial clock signal. The second calculation subunit is configured to obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate an average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute. The third calculation subunit is configured to obtain a third time delay difference between the third output clock signal and the input initial clock signal, and calculate an average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute. Specifically, the signal receiving unit is an Oscilloscope.

[0059] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein can have other embodiments, and can be implemented or realized in various ways.

Claims

1. A testing method, characterized in that, Including: Instantiate a signal input interface and a signal output interface on a test board, and input an initial clock signal to the signal input interface; Instantiate a connection line connecting the signal input interface and the signal output interface; Configure the input delay attribute of the signal input interface and the output delay attribute of the signal output interface to be both empty, receive a first output clock signal from the signal output interface, and then obtain a first time delay difference between the first output clock signal and the input initial clock signal; Configure the input delay attribute of the signal input interface, receive a second output clock signal from the signal output interface, and then obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute; Configure the output delay attribute of the signal output interface, receive a third output clock signal from the signal output interface, and then obtain a third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute.

2. The test method according to claim 1, wherein The signal input interface is a global clock signal input interface.

3. The test method according to claim 1, wherein The signal output interface is a global clock signal output interface.

4. The test method according to claim 1, wherein The connection line directly connects the signal input interface and the signal output interface.

5. The test method according to claim 1, wherein The calculating the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute includes: Obtain a difference between the second time delay difference and the first time delay difference to obtain a first difference, and then divide the first difference by the input delay attribute to obtain the average delay of the delay unit of the signal input interface.

6. The test method according to claim 1, wherein The calculating the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute includes: Obtain a difference between the third time delay difference and the first time delay difference to obtain a second difference, and then divide the second difference by the output delay attribute to obtain the average delay of the delay unit of the signal output interface.

7. A test system, characterized in that, Including: An instantiation unit for instantiating a signal input interface and a signal output interface on a test board, and inputting an initial clock signal to the signal input interface; It is also used to instantiate a connection line connecting the signal input interface and the signal output interface; A configuration unit for configuring the input delay attribute of the signal input interface and the delay output attribute of the signal output interface; A calculation unit for, when the configuration unit configures the input delay attribute of the signal input interface and the output delay attribute of the signal output interface to be both empty, receiving a first output clock signal from the signal output interface, and then obtaining a first time delay difference between the first output clock signal and the input initial clock signal; It is also used to receive a second output clock signal from the signal output interface when the input delay attribute of the signal input interface is configured in the configuration unit, then obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute; it is also used to receive a third output clock signal from the signal output interface when the output delay attribute of the signal output interface is configured in the configuration unit, then obtain a third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute.

8. The test system according to claim 7, characterized in that The instantiation unit includes a first instantiation subunit and a second instantiation subunit. The first instantiation subunit is used to instantiate a signal input interface and a signal output interface on a test board, and the second instantiation subunit is used to instantiate a connection connecting the signal input interface and the signal output interface.

9. The test system according to claim 8, wherein The instantiation unit includes a signal generation unit for inputting an initial clock signal to the signal input interface.

10. The test system according to claim 7, wherein The calculation unit includes a signal reception unit, a first calculation subunit, a second calculation subunit, and a third calculation subunit, and is used to receive the first output clock signal, the second output clock signal, and the third output clock signal from the signal output interface. The first calculation subunit is used to obtain a first time delay difference between the first output clock signal and the input initial clock signal. The second calculation subunit is used to obtain a second time delay difference between the second output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal input interface according to the first time delay difference, the second time delay difference, and the input delay attribute. The third calculation subunit is used to obtain a third time delay difference between the third output clock signal and the input initial clock signal, and calculate the average delay of the delay unit of the signal output interface according to the first time delay difference, the third time delay difference, and the output delay attribute.

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