A storage method and system

Abstract

The application discloses a storage method and system, and belongs to the network technical field.The storage system combines 2n storage banks with 1R1W support and a storage bit width of x bits, 2n storage banks with 1R1W support and a storage bit width of 1 bit, and 1 storage bank with 1R1W support and a storage bit width of y bits, so that a storage device with the support of simultaneously processing n RMWs and a storage bit width of y bits is realized.The x is less than the y.

Description

TECHNICAL FIELD

[0001] The present application relates to the network technology field, and in particular to a storage method and system. BACKGROUND

[0002] Network devices need to update queue resource occupation count, port resource occupation count and other statistical data. One statistical data may receive multiple updates at the same time. Multiple updates to the same data at the same time involve multiple updates to the same storage unit at the same time. The corresponding operation of the update is read-modify-write (RMW). That is, the memory bank where the storage unit is located needs to provide the capability of simultaneously processing multiple RMWs. SUMMARY

[0003] The present application provides a storage system and method, which can realize a memory supporting the capability of simultaneously processing multiple RMWs. The technical solution is as follows:

[0004] In a first aspect, a storage system is provided. The storage system comprises a first type of memory bank, n second type of memory banks, n third type of memory banks, n fourth type of memory banks, n first type of update circuit and a second type of update circuit.

[0005] The first type of memory bank is a simultaneous read and write operations (1R1W) memory bank with a storage bit width of y bits. The first type of memory bank is used to store data. The y is an integer greater than or equal to 2.

[0006] The second type of memory bank is a 1R1W memory bank with a storage bit width of x bits. The n second type of memory banks are respectively used to store the first type to the n type of change amount sums. The x is a positive integer less than y. The n is an integer greater than or equal to 2.

[0007] The third type of memory bank is a 1R1W memory bank with a storage bit width of x bits. The n third type of memory banks are respectively used to store the first type to the n type of change amount sums.

[0008] The fourth type of memory bank is a memory bank supporting two simultaneous read operations and two simultaneous write operations (2R2W). The n fourth type of memory banks are respectively used to store the first type to the n type of update flags. The first type to the n type of update flags correspond to the first type to the n type of change amount sums one by one. The first type to the n type of update flags respectively indicate whether the first type to the n type of change amount sums have been updated to the data.

[0009] The n first type of update circuits are respectively used to, based on the first type to the n type of update flags, accumulate the first type to the n type of change amounts received simultaneously to the first type to the n type of change amount sums stored in the n second type of memory banks respectively, to obtain new first type to n type of change amount sums. The n first type of update circuits are further used to write the new first type to n type of change amount sums to the n second type of memory banks respectively, and write the new first type to n type of change amount sums to the n third type of memory banks respectively.

[0010] The second type of update circuit is used to calculate new data based on the first type to the n type of change amount sums stored in the n third type of memory banks, the data stored in the first type of memory bank, and the first type to the n type of update flags stored in the n fourth type of memory banks, and update the data stored in the first type of memory bank with the new data.

[0011] The n type of change amount indicates that the data has n changes simultaneously, and the n changes come from different generators. For example, an interface one of a network device stores a received packet in a queue one, and an interface two of the network device also stores a received packet in a queue two. That is, the packet received by the interface one occupies a queue resource occupation count of the queue one, and the packet received by the interface two also occupies the queue resource occupation count of the queue one. That is, the queue resource occupation count of the queue one has two changes simultaneously, wherein one change comes from the interface one, and one change comes from the interface two.

[0012] The change amount sum indicates a cumulative amount of multiple same type of change amounts in a period of time. For example, if the first type of change amount indicates a change amount of a queue resource occupation count of the queue one caused by a packet received by the interface one, then the first type of change amount sum indicates a cumulative amount of change amounts of the queue resource occupation count of the queue one caused by multiple packets received by the interface one at multiple times.

[0013] The n first-type update circuits can receive n change amounts simultaneously and update the n change amounts to the n 1R1W second-type memory banks simultaneously. The second-type update circuit can read out the n change amount sums from the n 1R1W third-type memory banks simultaneously to update the n change amount sums to the data stored in the 1R1W first-type memory bank at one time. Because the change amount sums are much smaller than the maximum value of the data, the storage bit width x of the second-type memory bank and the third-type memory bank storing the change amount sums is much smaller than the storage bit width y of the first-type memory bank storing the data. Because the update flag is only used to indicate whether the change amount sums have been updated to the data, the storage bit width z of the memory bank storing the update flag is extremely small. For example, the storage bit width z can be 1. When z = 1, the update flag has two values of 0 and 1. For example, the update flag equal to 0 indicates that the change amount sums have not been updated to the data, and the update flag equal to 1 indicates that the change amount sums have been updated to the data. That is, the application realizes the memory supporting simultaneous processing of n RMW with a storage bit width of y bits by combining 2n memory banks supporting 1R1W with a storage bit width of x bits, n memory banks supporting 2R2W with an extremely small storage bit width, and 1 memory bank supporting 1R1W with a storage bit width of y bits.

[0014] According to the first aspect, in a first possible implementation manner of the first aspect, the second-type update circuit and the n first-type update circuits are further configured to update update flags stored in the n fourth-type memory banks. When the data stored in the first-type memory bank is updated based on the first-type to n-type change amount sums stored in the n third-type memory banks, the second-type update circuit is further configured to set the first-type to n-type update flags to a first value. The first value indicates that the first-type to n-type change amount sums stored in the n third-type memory banks have been updated to the data stored in the first-type memory bank. When the first-type to n-type change amount sums stored in the n second-type memory banks and the n third-type memory banks are updated based on the first-type to n-type change amounts, the n first-type update circuits are further configured to set the first-type to n-type update flags to a second value respectively. The second value indicates that the first-type to n-type change amount sums stored in the n third-type memory banks have not been updated to the data stored in the first-type memory bank.

[0015] According to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, when the kth update flag of the first type to the nth type is the first value, the kth first type update circuit of the n first type update circuits is further configured to calculate an arithmetic sum or an arithmetic difference of the kth type change amount sum stored in the kth second type memory bank and the kth type change amount of the first type to the nth type change amount, and write the arithmetic sum or the arithmetic difference into the kth second type memory bank and the kth third type memory bank, so as to update the kth type change amount sum stored in the kth second type memory bank and the kth third type memory bank. When the kth update flag is the second value, the kth first type update circuit is further configured to write the kth type change amount or an opposite number of the kth type change amount into the kth second type memory bank and the kth third type memory bank, so as to update the kth type change amount sum stored in the kth second type memory bank and the kth third type memory bank. k is a positive integer less than or equal to n.

[0016] According to the first aspect or the first or second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, when the kth update flag is the first value, the second type update circuit is further configured to accumulate the kth type change amount sum stored in the kth third type memory entity or an opposite number of the kth type change amount sum to data stored in the first type memory bank. When the kth update flag is the second value, the second type update circuit is further configured to set the kth type change amount sum to 0, and then accumulate the kth type change amount sum to the data stored in the first type memory bank.

[0017] In a second aspect, a storage method is provided. The method comprises:

[0018] n types of change amounts are simultaneously received. The n types of change amounts are used to simultaneously update data and trigger n times of update conflicts. The data is stored in a first type memory bank. The first type memory bank is a 1R1W memory bank with a storage bit width of y bits. n and y are integers greater than or equal to 2;

[0019] The n first-type update circuits respectively accumulate the simultaneously received first-type to nth-type change amounts to first-type to nth-type change amount sums based on first-type to nth-type update flags, to obtain new first-type to nth-type change amount sums. The first-type to nth-type update flags are respectively stored in a first fourth-type memory bank to an n th fourth-type memory bank of n fourth-type memory banks. The fourth-type memory banks are 2R2W memory banks. The first-type to nth-type change amount sums are respectively stored in a first second-type memory bank to an n th second-type memory bank of n second-type memory banks. The second-type memory banks are 1R1W memory banks with a storage bit width of x bits. x is a positive integer less than y.

[0020] The n first-type update circuits write the new first-type to nth-type change amount sums to the n second-type memory banks, to update the first-type to nth-type change amount sums stored in the n second-type memory banks.

[0021] The n first-type update circuits write the new first-type to nth-type change amount sums to n third-type memory banks, to update the first-type to nth-type change amount sums stored in the n third-type memory banks. The third-type memory banks are 1R1W memory banks with a storage bit width of x bits.

[0022] A second-type update circuit calculates new data based on the first-type to nth-type change amount sums stored in the n third-type memory banks, data stored in the first-type memory bank, and the first-type to nth-type update flags stored in the n fourth-type memory banks, and updates the data stored in the first-type memory bank with the new data.

[0023] According to a second aspect, in a first possible implementation manner of the second aspect, the first-type to nth-type update flags respectively indicate whether the first-type to nth-type change amount sums stored in the n third-type memory banks have been updated to the data stored in the first-type memory bank. When the first-type to nth-type change amount sums stored in the n third-type memory banks are updated to the data stored in the first-type memory bank, the second-type update circuit sets the first-type to nth-type update flags to a first value. The first value indicates that the first-type to nth-type change amount sums stored in the n third-type memory banks have been updated to the data stored in the first-type memory bank. When the first-type to nth-type change amounts are updated to the first-type to nth-type change amount sums stored in the n second-type memory banks and the n third-type memory banks, the n first-type update circuits respectively set the first-type to nth-type update flags to a second value. The second value indicates that the first-type to nth-type change amount sums stored in the n third-type memory banks have not been updated to the m data.

[0024] According to the second aspect and the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, when the kth update flag of the first type to the nth update flag of the first type is the first value, a kth first type update circuit of the n first type update circuits calculates an arithmetic sum or an arithmetic difference of a kth change amount total sum stored in a kth second type memory bank of the n second type memory banks and a kth change amount of the first type to the nth type change amount. The kth first type update circuit writes the arithmetic sum or the arithmetic difference into the kth second type memory bank and a kth third type memory bank to update the kth change amount total sum stored in the kth second type memory bank and the kth third type memory bank. When the kth update flag is the second value, the kth first type update circuit writes the kth change amount or an opposite number of the kth change amount into the kth second type memory bank and the kth third type memory bank to update the kth change amount total sum stored in the kth second type memory bank and the kth third type memory bank. k is a positive integer less than or equal to n.

[0025] According to the second aspect, and the first or second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, when the kth update flag is the first value, the second type update circuit accumulates the kth change amount total sum stored in the kth third type memory entity or an opposite number of the kth change amount total sum to data stored in the first type memory bank. When the kth update flag is the second value, the second type update circuit sets the kth change amount total sum to 0 and then accumulates the kth change amount total sum to data stored in the first type memory bank.

[0026] In a third aspect, a chip is provided. The chip includes the memory system provided in the first aspect or any possible implementation manner of the first aspect.

[0027] According to the third aspect, in a first possible implementation manner of the third aspect, the chip includes an application specific integrated circuit and / or a network processor. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic diagram of a data flow direction of a switching chip according to an embodiment of the present application;

[0029] Figure 2 is a schematic diagram of a memory system according to an embodiment of the present application;

[0030] Figure 3 is a flowchart of a change amount total sum update according to an embodiment of the present application;

[0031] Figure 4is another variation of the total sum of the amount of updating flowchart involved in the embodiments of the present application;

[0032] Figure 5 is a statistical data updating flowchart involved in the embodiments of the present application;

[0033] Figure 6 is another storage system schematic diagram provided by the embodiments of the present application;

[0034] Figure 7 is a storage method flowchart involved in the embodiments of the present application;

[0035] Figure 8 is a memory hardware structure schematic diagram involved in the embodiments of the present application; DETAILED DESCRIPTION

[0036] In order to make the principles, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0037] Please refer to Figure 1 which shows a switching chip data flow direction schematic diagram involved in the embodiments of the present application. Referring to Figure 1The schematic diagram includes a switch chip 100. The switch chip 100 can be a component of various network devices, providing packet forwarding function. The various network devices include switches and routers. The switch chip 100 includes eight interfaces (interface 101 to interface 108), packet processors (packet processor 111 to packet processor 118) corresponding to the interfaces, and a switch cache module 120. The interfaces 101 to 108 are associated with ports of the network device to which the switch chip 100 belongs. For example, the interface 101 can be associated with one port of the network device, and the interface 101 can also be associated with multiple ports of the network device. The switch cache module 120 includes a resource management module 121, a cache module 122, and a queue module 123. Any one of the packet processors 111 to 114 can receive a packet received by the interface corresponding to the packet processor, and extract relevant information of the packet, such as a five-tuple of the packet and a length of the packet. The switch cache module 120 stores the packet in the cache module 122 according to the relevant information of the packet, and stores metadata (for example, a header of the packet and a storage location of the packet in the cache module 122) of the packet in the queue module 123. The resource management module 121 updates queue resource occupation statistics of the queue. Any one of the packet processors 115 to 118 takes out the metadata of the packet from the queue module 123, and takes out the packet from the cache module 122 according to the metadata and delivers the packet to the interface corresponding to the packet processor for sending. The resource management module 121 updates the queue resource occupation count of the queue. The packets received by multiple interfaces at the same time can be stored in the same queue, and the packets sent by multiple interfaces at the same time can also come from the same queue. Therefore, the resource management module can need to update the same queue count, such as the queue resource occupation count, at the same time. At this time, the storage body storing the queue resource occupation count needs to provide the storage capability of simultaneously processing multiple RMWs. When the packets received by multiple interfaces at the same time or the packets sent by multiple interfaces at the same time come from multiple queues, if the queue resource occupation counts of the multiple queues are stored in the same storage body, the storage body also needs to provide the storage capability of simultaneously processing multiple RMWs. For example, please refer to Figure 1At the same time, the interfaces 101-104 receive packets and the packets are stored in the queue one; the interfaces 105-108 send packets and the packets come from the queue one. Therefore, at the same time, the resource management module 121 needs to add the number of queue resources occupied by the packets received by the interfaces 101-104 to the queue resource occupation count of the queue one, and write the updated queue resource occupation count into the storage storing the queue resource occupation count; meanwhile, the resource management module 121 also needs to subtract the number of queue resources occupied by the packets sent by the interfaces 105-108 from the queue resource occupation count, and write the updated queue resource occupation count into the storage storing the queue resource occupation count. That is, the storage needs to provide the storage capacity of processing 8 RMWs at the same time to support 8 interfaces to update the queue resource occupation count at the same time.

[0038] The resource management module 121 needs to update the change amount generated by 8 interfaces to the queue resource occupation count at the same time. That is, the queue resource occupation count has 8 change amounts at the same time. The 8 change amounts occurring at the same time come from different generators, such as the interfaces 101-108. Hereinafter, n change amounts coming from n generators at the same time are referred to as n types of change amounts.

[0039] The change amount will be much smaller than the maximum value of the data. For example, assuming that the storage space of the queue is 32 megabytes (MB), and the queue resource is a unit of 256 bytes (B), the maximum value of the queue resource occupation count of the queue is 131072 (32 MB / 256 B=128K, i.e. 131072, which is 2 raised to the power of 17). Therefore, the storage bit width of the storage storing the queue resource occupation count is at least 17 bits. For example, the storage unit of the storage occupies a storage space of 17 bits, and provides a maximum statistical value of 131072.

[0040] If the rate of the interface 101 is 1.6 million terabits per second (Tbps), the interface receives a maximum of 1.6 million terabits in 1 second. If the main frequency of the switch chip is 2 Giga Hertz (GHz), a clock cycle is 0.5 nanoseconds (ns). The interface 101 receives a maximum of 800 bits of data in a clock cycle. Therefore, the maximum change amount brought by the interface 101 to the queue resource occupation count in a clock cycle is 1 (800 bits / (256 bytes*8), rounded up). The change amount is much smaller than the maximum value of the data 131072 (1 / 131072). A storage with a storage bit width of 1 bit is needed to store the change amount.

[0041] If a 1R1W memory bank with a storage bit width of y bits (e.g., y = 17) is copied n times to support simultaneous processing of n RMWs, n memory banks with a storage bit width of y bits are required. However, the amount of change corresponding to each RMW is small (e.g., 1), and if n memory banks are used to store n amounts of change received simultaneously, the increased storage bit width x (e.g., x = 1) of the n memory banks will be much smaller than the storage bit width y (e.g., y = 17) of the memory bank used to store data.

[0042] Therefore, the storage system provided by the embodiments of the present application logically decomposes the module for simultaneously processing n RMW operations into two sub-modules: the first sub-module is used to simultaneously receive n amounts of change and simultaneously write the n amounts of change to n memory banks. The second sub-module is used to simultaneously read the n amounts of change from the n memory banks, accumulate the n amounts of change to data to obtain new data, and write the new data to the memory bank storing the data to simultaneously update the n amounts of change to the data. Considering that there can be a time delay between the writing of the amounts of change and the accumulation of the amounts of change, the n memory banks respectively store one amount of change or the accumulation of multiple amounts of change within the time delay, i.e., the sum of the amounts of change. That is, the n memory banks store n sums of amounts of change, and the n sums of amounts of change correspond one-to-one to the n amounts of change. For example, the first memory bank is used to store the sum of the amounts of change brought by the queue resource occupation count of the queue 1 by the interface 101 in 4 clock cycles, and the maximum value of the sum of the amounts of change is 1*4 = 4. Here, 1 is the maximum amount of change that can be brought by the interface 101 in one clock cycle. The storage bit width x of the memory bank is 2 (2 raised to the power of 2 equals 4). That is, the storage bit width x of the memory bank used to store the sum of the amounts of change is still smaller than the storage bit width y of the memory bank used to store data, and the difference is large (e.g., the difference is 15, 17-2 = 15).

[0043] In order to simultaneously update n amounts of change to n memory banks, the storage system provided by the embodiments of the present application includes n first-type update circuits. The n first-type update circuits are used to simultaneously receive n amounts of change and simultaneously update the n amounts of change to n memory banks. In order to simultaneously read n sums of amounts of change from n memory banks and update the n sums of amounts of change to data, the storage system provided by the embodiments of the present application includes a second-type update circuit. The second-type update circuit is used to simultaneously read n sums of amounts of change from n memory banks and update the n sums of amounts of change to data at one time. Because almost all contemporary digital systems are based on a pipeline architecture, the storage system provided by the present application can receive multiple amounts of change occurring simultaneously and simultaneously update the multiple amounts of change occurring at the previous time to data. For example, at the current time, the n first-type update circuits receive n amounts of change; at the next time, the n first-type update circuits can receive newly received n amounts of change while simultaneously updating the n amounts of change to n memory banks.

[0044] The first type of update circuit needs to read the change amount sum from the memory bank storing the change amount sum and write the new change amount sum to the memory bank. That is, the first type of update circuit needs to consume the 1R1W capability of the memory bank. Meanwhile, the second type of update circuit needs to read the change amount sum from the memory bank and clear the change amount sum after the change amount sum is updated to the data. That is, the second type of update circuit needs to consume the 1R1W capability of the memory bank. The first type of update circuit and the second type of update circuit together need to consume the 2R2W capability of the memory bank. That is, the memory bank with a storage bit width of x bits for storing the change amount sum needs to provide 2R2W storage capability.

[0045] The application combines two storage banks with storage bit width x bits supporting 1R1W and one storage bank with storage bit width z bits supporting 2R2W to realize a storage bank with storage bit width x bits supporting 2R2W. The first type of update circuit reads the change sum from the first storage bank with storage bit width x bits supporting 1R1W and writes the updated change sum into the first storage bank and the second storage bank with storage bit width x bits supporting 1R1W. The second type of update circuit reads the change sum from the second storage bank supporting 1R1W to update the data, but the second type of update circuit no longer directly clears the change sum. The clearing of the change sum is completed by the first type of update circuit with the assistance of the storage bank with storage bit width z bits. The storage bank with storage bit width z bits is used to store an update flag. The update flag indicates whether the change sum has been updated to the data and is used to assist the first type of update circuit to clear the change sum. For example, when the update flag is a first value (e.g., 1), it indicates that the change sum has been updated to the data. When the update flag is a second value (e.g., 0), it indicates that the change sum has not been updated to the data. When the data is updated, the second type of update circuit reads the update flag from the storage bank. If the update flag is the second value (i.e., the change sum has not been updated to the data), the second type of update circuit adds the change sum to the data to update the data. If the update flag is the first value (i.e., the change sum has been updated to the data), the second type of update circuit no longer adds the change sum to the data. After the second type of update circuit updates the change sum to the data, the update flag is set to the first value and the update flag is written into the storage bank. When the change sum is updated, the first type of update circuit reads the update flag from the storage bank. If the update flag is the second value (i.e., the change sum has not been updated to the data), the first type of update circuit adds the change to the change sum to update the change sum. If the update flag is the first value (i.e., the change sum has been updated to the data), the first type of update circuit directly sets the change sum to the change, which is equivalent to clearing the change sum that has been updated to the data. After the first type of update circuit updates the change sum, the update flag is set to the second value (indicating that the change sum has changed and has not been updated to the data) and the update flag is written into the storage bank. As can be seen, the first type of update circuit reads and writes the update flag from and into the storage bank, and the second type of update circuit also reads and writes the update flag from and into the storage bank. That is, the first type of update circuit and the second type of update circuit jointly consume the 2R2W storage capacity of the storage bank. Therefore, the storage bank is a storage bank with storage bit width z bits supporting 2R2W. Because the update flag is only used to indicate whether the change sum has been updated to the data, the storage bit width z can be very small. For example, the storage bit width can be 1, and the update flag can have two selected values of 0 and 1.Wherein, 0 option value represents that the change amount sum is not updated to the data, and 1 option value represents that the change amount sum is updated to the data.

[0046] Therefore, the storage system provided by the present application realizes the storage system supporting simultaneous processing of n RMWs and having a storage bit width of y bits by combining n first-type update circuits, 2n storage banks supporting 1R1W and having a storage bit width of x bits, n storage banks supporting 2R2W and having a storage bit width of z bits, one second-type update circuit, and one storage bank supporting 1R1W and having a storage bit width of y bits. The n first-type update circuits are configured to simultaneously receive n types of change amounts, read out change amount sums from the n storage banks supporting 1R1W and having a storage bit width of x bits (hereinafter referred to as n second-type storage banks) to calculate n types of new change amount sums, and write the n types of new change amount sums into the n storage banks supporting 1R1W and having a storage bit width of x bits (hereinafter referred to as n third-type storage banks) and another n storage banks supporting 1R1W and having a storage bit width of x bits to update the change amount sums. The one second-type update circuit is configured to simultaneously read out n change amount sums from the n third-type storage banks, read out data from the storage bank supporting 1R1W and having a storage bit width of y bits (hereinafter referred to as a first-type storage bank) to calculate new data, and write the new data into the first-type storage bank to update the data. The n storage banks supporting 2R2W and having a storage bit width of z bits (hereinafter referred to as fourth-type storage banks) are configured to store n types of update flags. The n types of update flags correspond to the n types of change amount sums one by one. The n types of update flags respectively represent whether the n types of change amount sums have been updated to the data. After the second-type update circuit updates the n types of change amount sums to the data, the n types of update flags are set to a first value, indicating that the n types of change amount sums have been updated to the data. After the n first-type update circuits update the change amounts to the change amount sums, the n types of update flags are set to a second value, indicating that the n types of change amount sums have not been updated to the data.

[0047] For the sake of brevity, the following uses alternative language to describe the change amount, the change amount sum, and the update flag. Delta represents the change amount, for example, Delta1, Delta2…Deltan represent the first type to the n type of change amount. DeltaSum represents the change amount sum, for example, DeltaSum1, DeltaSum2…DeltaSumn represent the first type to the n type of change amount. CLR represents the update flag, for example, CLR1, CLR2…CLR3 represent the first type to the n type of update flag. The following takes n=2 as an example to specifically describe the technical solution of the storage bank supporting simultaneous processing of n RMWs.

[0048] Please refer to Figure 2Fig. 2 shows a schematic diagram of a storage system 200 according to an embodiment of the present application. The storage system 200 provides a storage capability of processing 2 RMWs simultaneously. The storage system 200 comprises 2 first type update circuits, 1 second type update circuit 250, 1 first type storage bank 260, 2 second type storage banks, 2 third type storage banks and 2 fourth type storage banks. The 2 first type update circuits comprise a first type update circuit 201 and a first type update circuit 202. The 2 second type storage banks comprise a second type storage bank 210 and a second type storage bank 220. The 2 third type storage banks comprise a third type storage bank 230 and a third type storage bank 240. The 2 fourth type storage banks comprise a fourth type storage bank 270 and a fourth type storage bank 280.

[0049] The first type storage bank 260 is a 1R1W supporting storage bank with a storage bit width of y bits, comprising a storage unit 261. The storage unit 261 is configured to store the statistical data.

[0050] The second type storage bank 210 is a 1R1W supporting storage bank with a storage bit width of x bits, comprising a storage unit 211. The storage unit 211 is configured to store a first type change amount sum DeltaSuml. The first type change amount sum DeltaSuml is an arithmetic sum or an arithmetic difference of a plurality of first type change amounts Delta 1 associated with the statistical data in a period of time.

[0051] The second type storage bank 220 is a 1R1W supporting storage bank with a storage bit width of x bits, comprising a storage unit 221. The storage unit 221 is configured to store a second type change amount sum DeltaSum2. The second type change amount sum DeltaSum2 is an arithmetic sum or an arithmetic difference of a plurality of second type change amounts Delta 2 associated with the statistical data in a period of time.

[0052] The third type storage bank 230 is a 1R1W supporting storage bank with a storage bit width of x bits, comprising a storage unit 231. The storage unit 231 is configured to store the first type change amount sum DeltaSuml.

[0053] The third type storage bank 240 is a 1R1W supporting storage bank with a storage bit width of x bits, comprising a storage unit 241. The storage unit 241 is configured to store the second type change amount sum DeltaSum2.

[0054] The fourth type storage bank 270 is a 2R2W supporting storage bank with a storage bit width of 1, comprising a storage unit 271. The storage unit 271 is configured to store a first type update flag (CLRl). The CLRl corresponds to the DeltaSuml and is configured to indicate whether the DeltaSuml stored in the third type storage bank 230 has been updated to the statistical data.

[0055] The fourth type of memory bank 280 is a 2R2W supporting memory bank with a very small memory bit width, including a memory cell 281. For example, the memory bit width can be 1. The memory cell 281 is used to store a second type of update flag (CLR2). The CLR2 corresponds to the DeltaSum2, and is used to indicate whether the DeltaSum2 stored in the third type of memory bank 240 has been updated to the statistics.

[0056] The first type of update circuit 201 is used to update the DeltaSum1 based on the received Delta1, and the CLR1 stored in the memory cell 271. Please refer to Figure 3 which shows the update process of the DeltaSum1. The update process is as follows:

[0057] Step 301, receiving a first type of change amount Delta1.

[0058] The first type of change amount Delta1 is one of multiple change amounts of the statistics occurring in the same clock cycle. For example, in Figure 1 In the embodiment environment diagram shown, the interface 101 receives a packet with a length of 1024 bytes (byte, B), and the packet processor 111 stores the packet into the queue one. Then the packet will occupy 1024 bytes of the storage space of the queue one. If the queue resource occupation count is in units of 256 bytes, then the packet occupies 4 units of queue resources. That is, the reception of a packet with a length of 1024 bytes by the interface 101 causes the queue resource occupation count of the queue one to increase by 4. Here, 4 is a first type of change amount Delta1. Correspondingly, if the interface 102 also receives a packet with a length of 1024 bytes in the same clock cycle, and the packet processor 112 also stores the packet into the queue one. Then the packet also occupies 4 units of queue resources of the queue one. That is, the reception of a packet with a length of 1024 bytes by the interface 102 in the same clock cycle also causes the queue resource occupation count of the queue one to increase by 4. Here, 4 is a second type of change amount Delta2. Delta1 and Delta2 are two change amounts of the statistics occurring at the same time, which are generated by different generators.

[0059] Step 302, reading the first type of change amount sum DeltaSum1 from the second type of memory bank 210, and reading the first type of update flag CLR1 from the fourth type of memory bank 270.

[0060] The DeltaSum1 represents the arithmetic sum or arithmetic difference of multiple first type of change amounts Delta1 received by the first type of update circuit 201 in a period of time. For example, in Figure 1In the shown embodiment environment diagram, if interface 101 receives 10 packets with length of 1024 bytes in a period of time, and the 10 packets are stored in the same queue, then first type updating circuit 201 will receive 10 first type change values Delta1 with value of 4 in the period of time, and the value of DeltaSum1 is the arithmetic sum of the 10 first type change values Delta1, which is 40. If interface 101 sends 10 packets with length of 1024 bytes in a period of time, and the 10 packets are all taken from the same queue, then first type updating circuit 201 will receive 10 first type change values Delta1 with value of -4 in the period of time, and the value of DeltaSum1 is the arithmetic sum of the 10 first type change values Delta1, which is -40; or, first type updating circuit 201 will receive 10 first type change values Delta1 with value of 4 in the period of time, and the value of DeltaSum1 is the arithmetic difference of the 10 first type change values Delta1, which is -40.

[0061] CLR1 corresponds to DeltaSum1, and indicates whether DeltaSum1 has been updated to the statistics. For example, when CLR1 is true, it indicates that DeltaSum1 has been updated to the statistics. If CLR1 remains true, then second type updating circuit does not update DeltaSum1 to the statistics when updating the statistics. When CLR1 is false, it indicates that DeltaSum1 has not been updated to the statistics, and second type updating circuit adds or subtracts DeltaSum1 from the statistics when updating the statistics.

[0062] CLR1 is stored in fourth type memory with very small memory bit width. For example, the memory bit width is 1, and CLR1 has two possible values of 0 and 1. CLR1=1 can be used to indicate that CLR1 is true. CLR1=0 can also be used to indicate that CLR1 is true. For example, CLR1=1 is used to indicate that CLR1 is true in the embodiment of the present application.

[0063] Step 303, according to the value of CLR1, determine how to update DeltaSum1.

[0064] Step 3031, if CLR1=1, then set DeltaSum1=Delta1 or DeltaSum1=-Delta1, and set CLR1=0.

[0065] If CLR1 = 1, it means that DeltaSuml has been updated to the statistics, and the following should not update the statistics using DeltaSuml. Therefore, directly set DeltaSuml = Delta 1 or DeltaSuml = - Delta 1. It is equivalent to clearing the DeltaSuml that has been updated to the statistics, and accumulating the new change amount Delta 1 to DeltaSuml for the next time of updating the statistics.

[0066] Set CLR1 = 0. Because DeltaSuml has been updated using Delta 1, and the updated DeltaSuml has not been updated to the statistics, set CLR1 = 0 to enable the second type of updating circuit to update the updated DeltaSuml to the statistics.

[0067] After the step 3031 is executed, directly execute step 304, and do not execute step 3032.

[0068] If CLR1 = 0, set DeltaSuml = DeltaSuml + Delta 1 or DeltaSuml = DeltaSuml - Delta 1.

[0069] If CLR1 = 0, it means that DeltaSuml has not been updated to the statistics. Therefore, directly accumulate DeltaSuml to DeltaSuml, or subtract Delta 1 from DeltaSuml.

[0070] For the calculation of DeltaSuml, the first type of updating circuit can have two implementation forms: arithmetic difference and arithmetic sum. Arithmetic difference is generally used when Delta 1 needs to be subtracted from DeltaSuml. At this time, the pin connected with Delta 1 on the first type of updating circuit can be set as an arithmetic difference pin. When the first type of updating circuit receives Delta 1, Delta 1 is subtracted from DeltaSuml, or DeltaSuml = - Delta 1 is set. Arithmetic sum is generally used when Delta 1 needs to be accumulated to DeltaSuml. At this time, the pin connected with Delta 1 on the first type of updating circuit can be set as an arithmetic sum pin. When the first type of updating circuit receives Delta 1, Delta 1 is accumulated to DeltaSuml, or DeltaSuml = Delta 1 is set. When Delta 1 needs to be subtracted from DeltaSuml, the arithmetic sum pin can also be used, and at this time, Delta 1 is negative. For example, if an interface sends a 1024 byte message, then its corresponding Delta 1 = -4.

[0071] After the step 3032 is performed, the step 304 is performed.

[0072] The step 304, the updated DeltaSuml is written into the memory cell 211 in the second type of memory body 210 to update the original DeltaSuml stored in the memory cell 211, and the DeltaSuml is written into the memory cell 231 in the third type of memory body 230 to update the original DeltaSuml stored in the memory cell 231. Meanwhile, the CLRl is written into the memory cell 271 in the fourth type of memory body 270 to update the original CLRl stored in the memory cell 271.

[0073] After the updated DeltaSuml is written into the memory cell 211 and the memory cell 231, the updating of the DeltaSuml stored in the second type of memory body and the third type of memory body is completed.

[0074] If the original CLRl = 1, then the CLRl = 0 at this time. After the CLRl is written into the memory cell 271, the second type of updating circuit will update the change of the DeltaSuml to the statistical data when updating the statistical data.

[0075] The first type of updating circuit 202 is used to update the DeltaSum2 based on the Delta2 received at the same time with the Delta 1, and the CLR2 stored in the memory cell 281. The Delta2 and the Delta 1 are received by the storage system 200 at the same clock cycle, triggering 2 times of updating for the same statistical data. Please refer to Figure 4 The steps 401-404 show the updating process of the DeltaSum2. The specific updating process and Figure 3 The updating process is similar to that shown in the steps 301-303. Here, no further description is given.

[0076] The second type of updating circuit 250 is used to update the statistical data stored in the first type of memory body based on the first type of change sum DeltaSuml stored in the third type of memory body 230, the second type of change sum DeltaSum2 stored in the third type of memory body 240, and the first type of updating flag CLRl corresponding to the DeltaSuml and the second type of updating flag CLR2 corresponding to the DeltaSum2. The updating process is a periodic process, for example, it can be updated once every fixed clock cycle. Please refer to Figure 5 which shows an updating process of the statistical data. A specific updating process is as follows:

[0077] Step 501, read the statistic data from the first type of memory bank 260, read the change sum associated with the statistic data from the third type of memory bank, read the first type of change sum DeltaSuml from the third type of memory bank 230, read the second type of change sum DeltaSum2 from the third type of memory bank 240, read the update flag corresponding to the change sum from the fourth type of memory bank, read the first type of update flag CLRl corresponding to the DeltaSuml from the fourth type of memory bank 270, read the second type of update flag CLR2 corresponding to the DeltaSum2 from the fourth type of memory bank 280.

[0078] Step 502, according to the values of CLRl and CLR2, determine how to update the statistic data.

[0079] Step 5021, if CLRl = 0, CLR2 = 0, then set statistic data = statistic data + DeltaSuml + DeltaSum2, set CLRl = 1, CLR2 = 1.

[0080] CLRl = 0, CLR2 = 0, indicates that the DeltaSuml corresponding to the CLRl and the DeltaSum2 corresponding to the CLR2 have not been updated to the statistic data, therefore, add the DeltaSuml and the DeltaSum2 to the statistic data, set statistic data = statistic data + DeltaSuml + DeltaSum2.

[0081] After adding the DeltaSuml and the DeltaSum2 to the statistic data, then set CLRl = 1, CLR2 = 1, indicating that the DeltaSuml and the DeltaSum2 have been updated to the statistic data.

[0082] After executing step 5021, skip steps 5022-5024, and directly execute step 503.

[0083] Step 5022, if CLRl = 1, CLR2 = 0, then set statistic data = statistic data + DeltaSum2, set CLR2 = 1.

[0084] CLRl = 1, CLR2 = 0, indicates that the DeltaSuml corresponding to the CLRl has been updated to the statistic data, but the DeltaSum2 corresponding to the CLR2 has not been updated to the statistic data, therefore, only add the DeltaSum2 to the statistic data, set statistic data = statistic data + DeltaSum2.

[0085] After adding the DeltaSum2 to the statistic data, then set CLR2 = 1, indicating that the DeltaSum2 has been updated to the statistic data.

[0086] After step 5022 is executed, step 5023-5024 is skipped, and step 503 is executed directly.

[0087] Step 5023, if CLR1=0, CLR2=1, then set statistic data = statistic data + DeltaSum1, and set CLR1=1.

[0088] CLR1=0, CLR2=1 means that DeltaSum2 corresponding to the CLR2 has been updated to the statistic data, but DeltaSum1 corresponding to the CLR1 has not been updated to the statistic data, so only DeltaSum1 is accumulated to the statistic data, and statistic data = statistic data + DeltaSum1 is set.

[0089] After DeltaSum1 is accumulated to the statistic data, CLR1=1 is set, indicating that DeltaSum1 has been updated to the statistic data.

[0090] After step 5023 is executed, step 5024 is skipped, and step 503 is executed directly.

[0091] Step 5024, if CLR1=1, CLR2=1, then set statistic data = statistic data

[0092] CLR1=1, CLR2=1 means that DeltaSum1 corresponding to the CLR1 and DeltaSum2 corresponding to the CLR2 have both been updated to the statistic data, so DeltaSum1 and DeltaSum2 do not need to be accumulated to the statistic data, otherwise repeated statistics will occur. Set statistic data = statistic data.

[0093] Step 503, write the statistic data into the storage unit 261 of the first type of storage body 260 to update the statistic data originally stored therein; store CLR1 in the storage unit 271 of the fourth type of storage body 270 to update the CLR1 originally stored therein; and store CLR2 in the storage unit 281 of the fourth type of storage body 280 to update the CLR2 originally stored therein.

[0094] According to steps 5021-5023, the second type of update circuit simultaneously reads multiple change amount sums and updates the multiple change amount sums to the statistic data at one time.

[0095] Similar to steps 3031 and 3032, steps 5021-5023, when modifying the statistics, have the possibility of subtracting DeltaSuml or DeltaSum2 from the statistics, depending on the implementation of the second type of update circuit. For example, if the pin of the third type of memory bank 240 to which the second type of update circuit 250 is connected is the algebraic difference pin, then in step 5021, the statistics = statistics + DeltaSuml - DeltaSum2 will be set.

[0096] In summary, the first type of update circuit reads the change sum from the second type of memory bank and writes the updated change sum to the second type of memory bank. That is, the second type of memory bank only needs to provide the ability of 1 read and 1 write. The second type of memory bank is a memory bank supporting 1R1W. The first type of update circuit writes the updated change sum to the third type of memory bank, and the second type of update circuit reads the change sum from the third type of memory bank. That is, the third type of memory bank only needs to provide the ability of 1 read and 1 write. The third type of memory bank is a memory bank supporting 1R1W. The first type of update circuit reads the update flag from the fourth type of memory bank and writes the modified update flag back to the fourth type of memory bank. The second type of update circuit reads the update flag from the fourth type of memory bank and writes the modified update flag back to the fourth type of memory bank. Therefore, the fourth type of memory bank needs to provide the ability of 2 read and 2 write. The update flag only has two states: the change sum has been updated to the statistics, and the change sum has not been updated to the statistics. Therefore, 1 bit of storage space can store the update flag. The fourth type of memory bank is a memory bank supporting 2R2W with very low storage bit width. For example, the storage bit width is 1 bit. The second type of update circuit reads the statistics from the first type of memory bank and writes the updated statistics to the second type of memory bank. Therefore, the second type of memory bank only needs to provide the ability of 1 read and 1 write. The second type of memory bank is a memory bank supporting 1R1W.

[0097] The sum of the change amounts in a period of time is much smaller than the maximum value of the statistical data. Therefore, the storage bit width x of the second type of storage and the third type of storage that stores the sum of the change amounts is much smaller than the storage bit width y of the first type of storage that stores the statistical data. For example, if the storage space of a queue is 32 megabytes (MB), and the queue resource is in a unit of 256 bytes (B), the maximum value of the queue resource occupancy count of the queue is 2 raised to the power of 17 (32 MB / 256 B = 128 K, i.e., 2 raised to the power of 17). That is, the storage bit width y of the first type of storage that stores the statistical data is 17. If the rate of an interface receiving packets is 1.6 million terabits per second (Tbps), the interface can receive 1.6 million terabits in 1 second. If the network device in which the switching chip is located has a main frequency of 2 GHz, then a clock cycle is 0.5 nanoseconds (ns). Therefore, the interface receives at most 800 bits of data in a clock cycle. The maximum change amount of the queue resource occupancy count caused by the interface in a clock cycle is 1 (800 b / (256 B*8), rounded up). If the second type of update circuit has an update period of 64 clock cycles, then the sum of the change amounts needs to be accumulated for at most 64 clock cycles. Therefore, the storage bit width x of the second type of storage and the third type of storage that stores the sum of the change amounts is 6 (the change amount of each clock cycle is 1, and the accumulated change amount of 64 clock cycles is 64*1 = 64, and 2 raised to the power of 6 is equal to 64). If the second type of update circuit updates more frequently, then the storage bit width x will be smaller. For example, if the second type of update circuit has an update period of 32 clock cycles, then x = 5; if the second type of update circuit has an update period of 16 clock cycles, then x = 4; and if the second type of update circuit has an update period of 8 clock cycles, then x = 3.

[0098] In summary, Figure 2The storage system shown in the figure, two first type update circuits can simultaneously receive two change amounts associated with the same statistical data, and simultaneously update the two change amounts received simultaneously to the two change amount sums, and write the two change amount sums into two 1R1W second type storage banks and two 1R1W third type storage banks, the second type update circuit simultaneously reads the two change amount sums stored in the two 1R1W third type storage banks, and updates the two change amount sums to the statistical data stored in the 1R1W first type storage bank at one time. The update process is based on the two update flags stored in the two 2R2W fourth type storage banks. The storage bit width x of the two 1R1W second type storage banks and the two 1R1W third type storage banks is much smaller than the storage bit width y of the 1R1W first type storage bank. That is, the storage system provided in the embodiment of the present application, by combining 2x2 low storage bit width 1R1W storage banks, two low storage bit width 2R2W storage banks, one high storage bit width 1R1W storage bank and three update circuits, realizes a high storage bit width storage system supporting simultaneous processing of two RMWs. The above two are expanded to n: two second type storage banks are expanded to n second type storage banks, two third type storage banks are expanded to n third type storage banks, two fourth type storage banks are expanded to n fourth type storage banks, and two first type update circuits are expanded to n first type update circuits. The storage system can simultaneously receive n change amounts associated with the same statistical data, and realize a high storage bit width storage system supporting n RMWs at the same time. N is an integer greater than 2. That is, the storage system provided in the embodiment of the present application realizes a high storage bit width high performance storage system by combining low storage bit width low performance storage banks.

[0099] Figure 2 The storage system provides two update capabilities for the same statistical data. However, the storage system is not limited to updating the same statistical data, and can also provide multiple update capabilities for different statistical data simultaneously. Please refer to Figure 6 which shows the storage system 600 provided in the embodiment of the present application. The storage system 600 can provide a storage capability of simultaneously processing two RMWs, for simultaneously updating two statistical data. The storage system 600 includes two first type update circuits, one second type update circuit 650, one first type storage bank 660, two second type storage banks, two third type storage banks and two fourth type storage banks. The two first type update circuits include a first type update circuit 601 and a first type update circuit 602. The two second type storage banks include a second type storage bank 610 and a second type storage bank 620. The two third type storage banks include a third type storage bank 630 and a third type storage bank 640. The two fourth type storage banks include a fourth type storage bank 670 and a fourth type storage bank 680.

[0100] The first type of memory bank 660 is a 1R1W memory bank with a bit width of y bits, and includes two memory cells: memory cell 661 and memory cell 662. The two memory cells are used to store different statistics. For example, memory cell 661 is used to store the statistics of queue 1 (Ql) Ql statistics, and memory cell 662 is used to store the statistics of queue 2 (Q2) Q2 statistics. Because the two statistics are stored in the same 1R1W memory bank, only one of the statistics can be updated in one clock cycle. That is, if the first type of memory bank 660 receives an update for both the Ql statistics and the Q2 statistics at the same time, two update conflicts will be triggered.

[0101] The second type of memory bank 610 is a 1R1W memory bank with a bit width of x bits, and includes memory cell 611 and memory cell 612. Memory cell 611 is used to store the first type of change amount sum of Ql Ql DeltaSuml. The Ql DeltaSuml is the arithmetic sum or difference of a plurality of first type of change amounts Delta1 (Ql Delta1) associated with the Ql statistics in a period of time. Memory cell 612 is used to store the first type of change amount sum of Q2 Q2 DeltaSuml. For example, Figure 1 The packet received by interface 101 can be stored in queue 1 or queue 2. When the packet received by interface 101 is stored in queue 1, interface 101 brings a first type of change amount to the Ql statistics, which is accumulated to Ql DeltaSuml. When the packet received by interface 101 is stored in queue 2, interface 101 brings a first type of change amount to the Q2 statistics, which is accumulated to Q2 DeltaSuml.

[0102] The second type of memory bank 620 is a 1R1W memory bank with a bit width of x bits, and includes memory cell 621 and memory cell 622. Memory cell 621 is used to store the second type of change amount sum of Ql Ql DeltaSum2. The Ql DeltaSum2 is the arithmetic sum or difference of a plurality of second type of change amounts Delta2 (Ql Delta2) associated with the Q2 statistics in a period of time. Memory cell 622 is used to store the second type of change amount sum of Q2 Q2 DeltaSum2. For example, Figure 1The packets received by interface 102 may be stored in queue one or queue two. When a packet received by interface 102 is stored in queue one, interface 102 introduces a second type of change to the Q1 statistics, which is accumulated in Q1DeltaSum2. When a packet received by interface 101 is stored in queue two, interface 101 introduces a second type of change to the Q2 statistics, which is accumulated in Q2DeltaSum2.

[0103] The third type of memory bank 630 is a 1R1W memory bank with a storage width of x bits, including memory cell 631 and memory cell 632. Memory cell 631 is used to store Q1 DeltaSum1. Memory cell 632 is used to store Q2 DeltaSum1.

[0104] The third type of memory bank 640 is a 1R1W memory bank with a storage width of x bits, including memory cell 641 and memory cell 642. Memory cell 641 is used to store Q2 DeltaSum2. Memory cell 642 is used to store Q2DeltaSum2.

[0105] The fourth type of memory bank 670 is a 2R2W-supporting memory bank with an extremely low memory width, including memory cells 671 and 672. For example, the memory width is 1 bit. Memory cell 671 stores the first type update flag (Q1CLR1) for Q1. Q1 CLR1 corresponds to Q1 DeltaSum1 and indicates whether Q1 DeltaSum1 has been updated to the Q1 statistics. When Q1 CLR1 is true, it means that Q1 DeltaSum1 has been updated to the Q1 statistics. If the value of Q1 CLR1 remains true, Q1 DeltaSum1 will not be updated to the statistics. When Q1 CLR1 is false, it means that Q1 DeltaSum1 has not been updated to the statistics. Memory cell 672 stores the first type update flag (Q2CLR1) for Q2. Q2CLR1 corresponds to Q2 DeltaSum1 and indicates whether Q2 DeltaSum1 has been updated to the Q2 statistics. When Q2 CLR1 is true, it means that Q2 DeltaSum1 has been updated to the Q2 statistics. If the value of Q2 CLR1 remains true, Q2 DeltaSum1 will not be updated to the statistics. When Q2 CLR1 is false, it means that Q2 DeltaSum1 has not been updated to the statistics.

[0106] The first type of update circuit 601 is used to update Q1 DeltaSum1 based on the received Q1 Delta1 and Q1CLR1 stored in the storage unit 671. This update process is similar to...Figure 3 The updating process is similar and will not be repeated here.

[0107] The first type of updating circuit 602 is configured to update Q2 DeltaSum2 based on the received Q2 Delta2 and Q2 CLR2 stored in the storage unit 682. The Q2 Delta2 and Q1 Delta1 are received by the storage system 600 in the same clock cycle, triggering simultaneous updating of two statistics stored in the same 1R1W supported memory bank. The updating process of Q2 DeltaSum2 and Figure 3 The updating process is similar and will not be repeated here.

[0108] The second type of updating circuit 650 is configured to update Q1 statistics stored in the storage unit 661 based on Q1 DeltaSum1 stored in the third type of memory bank 630 and Q1 CLR1 corresponding to Q1 DeltaSum1, or update Q2 statistics stored in the storage unit 662 based on Q2 DeltaSum2 stored in the third type of memory bank 640 and Q2 CLR2 corresponding to Q2 DeltaSum2. The updating process of Q1 statistics and the updating process of Q2 statistics are similar to Figure 5 The updating process is similar and will not be repeated here. The second type of updating circuit 650 can poll to update Q1 statistics and Q2 statistics alternately, or update Q1 statistics and Q2 statistics according to a specified clock cycle interval.

[0109] For details not disclosed in the embodiments of the present application, please refer to Figures 2-5 the embodiments shown.

[0110] In summary, Figure 6The storage system shown is combined with 2x2 low storage bit width 1R1W supporting memory banks, 2 very low storage bit width 2R2W supporting memory banks, 1 high storage bit width 1R1W supporting memory bank and 3 update circuits to realize a high storage bit width storage system capable of simultaneously processing 2 RMWs. The high storage bit width storage system capable of simultaneously processing 2 RMWs can be used to simultaneously update 2 statistical data. The 2 statistical data are stored in the same 1R1W memory bank. The above 2 are expanded to n: 2 second type memory banks are expanded to n second type memory banks, 2 third type memory banks are expanded to n third type memory banks, 2 fourth type memory banks are expanded to n fourth type memory banks, and 2 first type update circuits are expanded to n first type update circuits. The storage system can simultaneously receive n change amounts (n >= m) associated with m statistical data to realize a high storage bit width storage system capable of simultaneously processing n RMWs. The high storage bit width storage system capable of simultaneously processing n RMWs can be used to simultaneously update m statistical data. The m statistical data are stored in the same 1R1W supporting memory bank. The n change amounts received simultaneously are associated with the m statistical data. Any statistical data in the m statistical data receives at least 1 change amount. That is, the storage system provided in the embodiments of the present application realizes a high storage bit width high performance storage system by combining low storage bit width low performance memory banks.

[0111] Please refer to Figure 7 which shows a flowchart of a storage method provided in the embodiments of the present application, including the following steps:

[0112] Step 701: simultaneously receive n change amounts of a first type change amount to an n th type change amount, the n change amounts are used to update m data and trigger n times of update conflicts. The m data are stored in a first type memory bank supporting 1R1W.

[0113] When m = 1, the n change amounts are n change amounts of the 1 data occurring in the same clock cycle. For example, 5 interfaces of a network device each receive a 1024B packet in the same clock cycle and store the packet in the same queue. The 1024B packet received by each interface occupies 4 units of queue resources of the queue. That is, in the same clock cycle, the queue resource occupation count of the queue has 5 change amounts, and each change amount has a value of 4. The 5 change amounts occurring simultaneously correspond to the first type change amount to the fifth type change amount received simultaneously in step 701. The first type memory bank storing the data is a 1R1W supporting memory bank. That is, only one change amount can be updated to the data in the same clock cycle. Because the data has 5 change amounts occurring in the same clock cycle, if the 5 change amounts are directly updated to the first type memory bank storing the data, 5 times of update conflicts will be triggered.

[0114] When m>1, the n changes are changes occurred in the same clock cycle, but the n changes are associated with m data. For example, 5 interfaces of a network device each receive a 1024B packet in the same clock cycle. 3 of the interfaces store the packets into queue one, and the other 2 interfaces store the packets into queue two. That is, in the same clock cycle, the queue resource occupancy count of queue one has 3 changes, and the queue resource occupancy count of queue two has 2 changes. That is, 5 simultaneous changes are used to update 2 data. Because the 2 data are stored in the same memory bank supporting 1R1W, if the 5 changes are directly updated to a first type memory bank storing the 2 data at the same time, 5 update conflicts will be triggered.

[0115] In step 702, n first type update circuits respectively calculate new change sums based on one of the n changes, the change sum corresponding to the one change, and the update flag corresponding to the change sum. The n change sums corresponding to the n changes are respectively stored in n second type memory banks supporting 1R1W. The n first type update circuits calculate n new change sums.

[0116] For example, the first first type update circuit reads the first type change sum corresponding to the first type change from the first second type memory bank, and calculates the arithmetic sum or difference of the first type change sum and the first type change to obtain a new first type change sum; the n-th first type update circuit reads the n-th type change sum corresponding to the n-th type change from the n-th second type memory bank, and calculates the arithmetic sum or difference of the n-th type change sum and the n-th type change to obtain a new n-th type change sum. The specific calculation process is similar to that of steps 3031-3032 shown in FIG. 3B, and will not be described here. Figure 3 The steps 4031-4032 shown in FIG. 4B are similar. Details are not described here. Figure 4 The steps 4031-4032 shown in FIG. 4B are similar. Details are not described here.

[0117] In step 703, the n first type update circuits respectively write the n new change sums into the n second type memory banks to update the change sums already stored in the second type memory banks. The n first type update circuits respectively write the n new change sums into the n third type memory banks to update the change sums already stored in the third type memory banks.

[0118] For example, the first first-type update circuit writes the new first-type change amount sum into the first second-type memory bank to update the first-type change amount sum originally stored in the second-type memory bank; the first first-type update circuit writes the new first-type change amount sum into the first third-type memory bank to update the first-type change amount sum originally stored in the third-type memory bank; the nth first-type update circuit writes the new nth-type change amount sum into the nth second-type memory bank to update the nth-type change amount sum originally stored in the nth-type memory bank; and the nth first-type update circuit writes the new nth-type change amount sum into the nth third-type memory bank to update the nth-type change amount sum originally stored in the third-type memory bank. The specific process is similar to that shown in steps 304, or, Figure 3 steps 404. Details are not described herein. Figure 4

[0119] In step 704, the second-type update circuit calculates m new data based on the n change amount sums of the first to nth types stored in the n third-type memory banks, the update flags corresponding to the n change amount sums, and the m data stored in the first-type memory bank, and writes the m new data into the first-type memory bank to update the m data.

[0120] When m = 1, the update process is similar to that shown in steps 304, or, Figure 5 When m > 1, the update process is similar to that performed by the second-type update circuit 650. Details are not described herein.

[0121] Please refer to Figure 8 which shows a hardware structure diagram of a storage device 800 provided by an embodiment of the present application. The storage device 800 is used to implement a memory bank capable of processing two RMWs and having a storage bit width of y bits. Please refer to Figure 8 The storage device 800 includes update circuits 801-802, 1R1W supporting memory banks 810-820 having a storage bit width of x bits, 2R2W supporting memory banks 870-880 having a storage bit width of z (for example, z = 1) bits, 1R1W supporting memories 830-840 having a storage bit width of x bits, an update circuit 850, and a 1R1W memory bank 860 having a storage bit width of y bits. Wherein x and y are positive integers, and y > x. The memory banks 810-820, the memories 830-840, the memory banks 870-880, and the memory bank 860 include one or more memory cells. W shown in the figure represents writing data in the direction of the arrow, and R represents reading data in the direction of the arrow.

[0122] ​The memory banks 810-820, 830-840, 870-880, and 860 can be implemented based on a plurality of types of storage media, including random access memory (RAM), non-volatile RAM (NVRAM), electrically erasable PROM (EEPROM), and the like.

[0123] The update circuits 801-802 and 850 can be implemented based on a plurality of technologies, such as an ASIC or an FPGA.

[0124] The connection lines connecting the memory banks or the update circuits can be in a plurality of forms, such as an on-chip interconnection, a Si Interposer, a printed circuit board (PCB), and the like.

[0125] As can be appreciated by those skilled in the art, referring to the above hardware structure diagram, the number of 1R1W memory banks and 2R2W memory banks with an extended storage bit width of x bits, and the number of update circuits, can realize a memory with a storage bit width of y bits supporting simultaneous processing of n RWMs (n>2): the update circuits are expanded from 2 (801 and 802) to n; the 1R1W memory banks with a storage bit width of x bits are expanded from 2 (810 and 820) to n; the 2R2W memory banks are expanded from 2 (870 and 880) to n; the 1R1W memory banks with a storage bit width of x bits are expanded from 2 (830 and 840) to n.

[0126] The above devices can be respectively arranged on independent chips, or at least partially or entirely arranged on the same chip. Whether to arrange the devices independently on different chips or to integrate them on one or more chips often depends on the needs of product design. The embodiments of the present application do not limit the specific implementation form of the above devices.

[0127] The embodiments of the present application provide a chip, which includes one or more of the following: a network processor (NP) and an application-specific integrated circuit (ASIC). The chip implements the storage system shown in the above embodiments. Figure 8

[0128] It should be understood that, in the embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.​

[0129] The above detailed description of the specific embodiments of the present application is provided for the purpose of further explaining the objects, technical solutions and advantages of the present application, and it should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application, and any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the present application shall be included in the protection scope of the present application.

Claims

1. A storage system, characterized by, The storage system comprises: a first type of memory bank, wherein the first type of memory bank is a memory bank supporting simultaneous read and write operation 1R1W with a storage bit width of y bits, y being an integer greater than or equal to 2, and is used to store data; n second type of memory banks, wherein the second type of memory bank is a memory bank supporting 1R1W with a storage bit width of x bits, the n second type of memory banks are respectively used to store first type to nth type of change amount sums, x being a positive integer less than y, and n being an integer greater than or equal to 2; n third type of memory banks, wherein the third type of memory bank is a memory bank supporting 1R1W with a storage bit width of x bits, the n third type of memory banks are respectively used to store the first type to nth type of change amount sums; n fourth type of memory banks, wherein the fourth type of memory bank is a memory bank supporting 2R2W with 2 simultaneous read and 2 simultaneous write operations, the n fourth type of memory banks are respectively used to store first type to nth type of update flags, the first type to nth type of update flags correspond one-to-one to the first type to nth type of change amount sums, and the first type to nth type of update flags respectively indicate whether the first type to nth type of change amount sums have been updated to the data; n first type of update circuits, which are respectively used to, based on the first type to nth type of update flags, accumulate the first type to nth type of change amounts received simultaneously to the first type to nth type of change amount sums stored in the n second type of memory banks respectively to obtain new first type to nth type of change amount sums, write the new first type to nth type of change amount sums into the n second type of memory banks respectively, and write the new first type to nth type of change amount sums into the n third type of memory banks respectively; a second type of update circuit, which is used to calculate new data based on the first type to nth type of change amount sums stored in the n third type of memory banks, the data stored in the first type of memory bank, and the first type to nth type of update flags stored in the n fourth type of memory banks, and update the data stored in the first type of memory bank with the new data.

2. The storage system according to claim 1, wherein the second type of update circuit is further used to, after updating the data stored in the first type of memory bank based on the first type to nth type of change amount sums stored in the n third type of memory banks, set the first type to nth type of update flags to a first value, the first value indicating that the first type to nth type of change amount sums stored in the n third type of memory banks have been updated to the data stored in the first type of memory bank; the n first type of update circuits are further used to, after updating the first type to nth type of change amount sums stored in the n second type of memory banks and the n third type of memory banks based on the first type to nth type of change amounts, respectively set the first type to nth type of update flags to a second value, the second value indicating that the first type to nth type of change amount sums stored in the n third type of memory banks have not been updated to the data stored in the first type of memory bank.

3. The storage system according to claim 2, wherein the kth first-type update circuit is further configured to, when the kth update flag in the first-type to n-type update flags is the first value, calculate an arithmetic sum or an arithmetic difference of a kth change amount sum stored in a kth second-type memory bank and a kth change amount in the first-type to n-type change amounts, and write the arithmetic sum or the arithmetic difference into the kth second-type memory bank and a kth third-type memory bank to update the kth change amount sum stored in the kth second-type memory bank and the kth third-type memory bank, k being a positive integer less than or equal to n; the kth first-type update circuit is further configured to, when the kth update flag is the second value, write the kth change amount or an opposite number of the kth change amount into the kth second-type memory bank and the kth third-type memory bank to update the kth change amount sum stored in the kth second-type memory bank and the kth third-type memory bank.

4. The memory system of claim 3, wherein the second-type update circuit is further configured to, when the kth update flag is the first value, accumulate the kth change amount sum or an opposite number of the kth change amount sum stored in the kth third-type memory entity to data stored in the first-type memory bank; the second-type update circuit is further configured to, when the kth update flag is the second value, set the kth change amount sum to 0 and then accumulate the kth change amount sum to the data stored in the first-type memory bank.

5. A storage method characterized by comprising: The method comprises: n types of change amounts are simultaneously received, the n types of change amounts being used to simultaneously update data and trigger n times of update conflicts, the data being stored in a first-type memory bank, the first-type memory bank being a 1R1W memory bank with a storage bit width of y bits, n and y being integers greater than or equal to 2; n first-type update circuits accumulate the first-type to n-type change amounts received simultaneously in first-type to n-type change amount sums respectively based on first-type to n-type update flags stored in a first fourth-type memory bank to an n th fourth-type memory bank of n fourth-type memory banks respectively, the fourth-type memory banks being 2R2W memory banks, the first-type to n-type change amount sums being stored in a first second-type memory bank to an n th second-type memory bank of n second-type memory banks respectively, the second-type memory banks being 1R1W memory banks with a storage bit width of x bits, x being a positive integer less than y; the n first-type update circuits write the new first-type to n-type change amount sums into the n second-type memory banks to update the first-type to n-type change amount sums stored in the n second-type memory banks; and the second-type update circuit is further configured to, when the kth update flag is the first value, accumulate the kth change amount sum or an opposite number of the kth change amount sum stored in the kth third-type memory entity to data stored in the first-type memory bank; the second-type update circuit is further configured to, when the kth update flag is the second value, set the kth change amount sum to 0 and then accumulate the kth change amount sum to the data stored in the first-type memory bank. The n first-type update circuits write the new first-type to n-type change amount sums into n third-type memories respectively to update the first-type to n-type change amount sums stored in the n third-type memories, and the third-type memories are 1R1W supporting memories with a bit width of x bits; The second-type update circuit calculates new data based on the first-type to n-type change amount sums stored in the n third-type memories, the data stored in the first-type memory, and the first-type to n-type update flags stored in the n fourth-type memories, and updates the data stored in the first-type memory with the new data.

6. The method of claim 5, wherein, The method further comprises: The first-type to n-type update flags respectively indicate whether the first-type to n-type change amount sums stored in the n third-type memories have been updated to the data stored in the first-type memory: When the first-type to n-type change amount sums stored in the n third-type memories are updated to the data stored in the first-type memory, the second-type update circuit sets the first-type to n-type update flags to a first value respectively, indicating that the first-type to n-type change amount sums stored in the n third-type memories have been updated to the data stored in the first-type memory; When the first-type to n-type change amounts are updated to the first-type to n-type change amount sums stored in the n second-type memories and the n third-type memories, the n first-type update circuits set the first-type to n-type update flags to a second value respectively, indicating that the first-type to n-type change amount sums stored in the n third-type memories have not been updated to the data.

7. The method of claim 6, wherein, The method further comprises: When the kth update flag in the first-type to n-type update flags is the first value, a kth first-type update circuit in the n first-type update circuits calculates an arithmetic sum or an arithmetic difference of a kth change amount sum stored in a kth second-type memory in the n second-type memories and the kth change amount in the first-type to n-type change amounts, and writes the arithmetic sum or the arithmetic difference into the kth second-type memory and a kth third-type memory to update the kth change amount sum stored in the kth second-type memory and the kth third-type memory, k is a positive integer less than or equal to n; When the kth update flag is the second value, the kth first-type update circuit writes the kth change amount or an opposite number of the kth change amount into the kth second-type memory and the kth third-type memory to update the kth change amount sum stored in the kth second-type memory and the kth third-type memory.

8. The method according to claim 7, wherein, When the kth update flag is the first value, the second-type update circuit accumulates the kth change amount sum stored in the kth third-type memory or an opposite number of the kth change amount sum to the data stored in the first-type memory; When the kth update flag is the second value, the second update circuit sets the kth change amount sum to 0 and then accumulates the kth change amount sum to data stored in the first memory bank.

9. A chip, characterized by The chip comprises the memory system of any one of claims 1 to 4.

10. The chip of claim 9, wherein, The chip comprises an application specific integrated circuit and / or a network processor.

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