Machine code instruction conversion method and apparatus, electronic device, and readable storage medium

Abstract

Embodiments of the present application provide a machine code instruction conversion method and device, electronic equipment and readable storage medium, and relate to the technical field of computers. The method comprises: obtaining a machine code instruction to be converted, wherein the machine code instruction can comprise an operation code, a first operand, a second operand, a third operand and an original immediate number; analyzing the machine code instruction to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained after conversion based on the original immediate number; and obtaining an assembly code corresponding to the machine code instruction based on preset rule information combination of the obtained target assembly instruction, register names and target immediate number, which realizes convenient conversion of the machine code instruction into the assembly code, is conducive to further analysis of the assembly code by technical personnel, and effectively fills the technical gap of conversion of the machine code into the assembly code.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular, the present application relates to a machine code instruction conversion method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] With the vigorous development of computer technology, the processing performance of chip hardware is getting stronger and stronger, and the speed of processing data is also getting faster. Among them, the CPU (central processing unit) executes instructions in the pipeline. The execution process of an instruction can be divided into several steps, each step is completed by an independent circuit, and the operations of different steps of different instructions are overlapped, so as to realize parallel processing of multiple instructions, so as to speed up the program running process.

[0003] The instructions executed in the pipeline of CPU are generally in the form of machine code, and for technical personnel, the readability of machine code is low, and the information presented is not intuitive. In the case of lacking the technical scheme of quickly converting machine code into assembly code at present, technical personnel can hardly directly obtain the execution information of CPU from machine code for analysis. SUMMARY

[0004] The purpose of the embodiment of the present application is to solve the technical problem that it is difficult to conveniently convert machine code instructions into assembly code.

[0005] In a first aspect, the present application provides a machine code instruction conversion method, which comprises:

[0006] obtaining machine code instructions to be converted; the machine code instructions include operation code, first operand, second operand, third operand and original immediate number;

[0007] parsing the machine code instructions to determine the target assembly instructions corresponding to the operation code and the second operand, the register names corresponding to the first operand and the third operand respectively, and the target immediate number obtained based on the original immediate number conversion;

[0008] combining the target assembly instructions, the register names and the target immediate number based on the preset rule information to obtain the assembly code corresponding to the machine code instructions; wherein, the rule information includes the assembly format for the target assembly instructions.

[0009] In an optional embodiment of the first aspect, the preset rule information further includes the corresponding relationship between the operation code, the second operand and the target assembly instructions; determining the target assembly instructions corresponding to the operation code and the second operand comprises:

[0010] determining at least one candidate assembly instruction corresponding to the operation code based on the preset rule information and the operation code;

[0011] determine, based on the preset rule information and the second operand, an assembly instruction corresponding to the second operand in the at least one candidate assembly instruction as the target assembly instruction.

[0012] In an optional embodiment of the first aspect, determining the register names corresponding to the first operand and the third operand respectively comprises:

[0013] determining the instruction type of the target assembly instruction, and determining the register names corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand and the third operand.

[0014] In an optional embodiment of the first aspect, the register names comprise register names of target registers and source registers corresponding to the machine code instruction.

[0015] determining the register names corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand and the third operand comprises:

[0016] determining the register name of the target register corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the first operand;

[0017] determining the register name of the source register corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the third operand.

[0018] In an optional embodiment of the first aspect, determining the register name of the target register corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the first operand comprises:

[0019] determining at least two first register names based on the first operand and the preset rule information; the preset rule further comprises a corresponding relationship between each first register name and the instruction type; determining, as the register name of the target register, a register name corresponding to the instruction type of the target assembly instruction in the at least two first register names;

[0020] determining the register name of the source register corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the third operand comprises:

[0021] determining at least two second register names based on the third operand and the preset rule information; the preset rule further comprises a corresponding relationship between each second register name and the instruction type; determining, as the register name of the source register, a register name corresponding to the instruction type of the target assembly instruction in the at least two second register names.

[0022] In an optional embodiment of the first aspect, the method further comprises:

[0023] determining an execution time corresponding to the machine code instruction;

[0024] The preset user interface displays the assembly code corresponding to the machine code instruction and the execution time.

[0025] In a second aspect, a machine code instruction conversion apparatus is provided, and the apparatus comprises:

[0026] A machine code obtaining module is configured to obtain a machine code instruction to be converted, wherein the machine code instruction comprises an operation code, a first operand, a second operand, a third operand, and an original immediate number.

[0027] A machine code analyzing module is configured to analyze the machine code instruction, to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained based on the original immediate number.

[0028] A combining module is configured to combine the target assembly instruction, the register names, and the target immediate number based on preset rule information, to obtain an assembly code corresponding to the machine code instruction, wherein the rule information comprises an assembly format for the target assembly instruction.

[0029] In a third aspect, an electronic device is provided, and the electronic device comprises:

[0030] A memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor implements the machine code instruction conversion method of any of the above embodiments when executing the program.

[0031] In a fourth aspect, a readable storage medium is provided, and the readable storage medium stores a program, wherein the program is executable by a processor to implement the machine code instruction conversion method of any of the above embodiments.

[0032] In a fifth aspect, a program product or program is provided, and the program product or program comprises at least one instruction stored in a readable storage medium. A processor of a device reads the instruction from the readable storage medium, and the processor executes the instruction, so that the device implements the method provided in the first aspect embodiment when executed.

[0033] The machine code instruction conversion method described above obtains a machine code instruction to be converted, wherein the machine code instruction can comprise an operation code, a first operand, a second operand, a third operand, and an original immediate number. The machine code instruction is then analyzed to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained based on the original immediate number. The obtained target assembly instruction, register names, and target immediate number can be combined based on preset rule information to obtain an assembly code corresponding to the machine code instruction, which facilitates the conversion of the machine code instruction to the assembly code, and is beneficial for technical personnel to further analyze the assembly code, and effectively fills the technical gap of converting machine code to assembly code. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0035] Figure 1 A flowchart illustrating a machine code instruction conversion method provided in an embodiment of this application;

[0036] Figure 2 This application provides a schematic representation of the relationship between the opcode, the second operand, and the target assembly instruction in a machine code instruction conversion method.

[0037] Figure 3 This application provides a schematic representation of the relationship between the first operand, the third operand, and the register name in a machine code instruction conversion method according to an embodiment of the present application.

[0038] Figure 4 A flowchart illustrating a machine code instruction conversion method provided in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of the structure of a machine code instruction conversion device provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the structure of an electronic device for machine code instruction conversion provided in an embodiment of this application. Detailed Implementation

[0041] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0042] Those skilled in the art can understand that the singular forms "a", "an" and "the" used herein include plural forms unless expressly stated otherwise. It should be further understood that the terms "include" and "contain" used in the embodiments of the present application mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude other features, information, data, steps, operations, elements, components and / or their combinations supported by the art. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or it can mean that the element and the other element establish a connection relationship through an intermediate element. In addition, "connection" or "coupling" used herein can include wireless connection or wireless coupling. The term "and / or" used herein indicates that at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0043] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0044] First, several terms related to the present application are introduced and explained:

[0045] Machine code: also known as machine instruction code. The program language directly used by the computer, whose statements are machine instruction codes. Machine instruction codes are a set of binary numbers used to instruct the computer to perform operations and operation number addresses. When the computer executes a program written in a high-level language, the program still needs to be interpreted and compiled into machine instructions. This process is still completed by the computer. The program that completes this process is called an interpreter or a compiler.

[0046] Central processing unit: (central processing unit, CPU for short) as the operation and control core of the computer system, it is the final execution unit of information processing and program running.

[0047] RISC-V: an open-source instruction set architecture (ISA) based on the principle of reduced instruction set (RISC). Compared with most instruction sets, the RISC-V instruction set can be freely used for any purpose, allowing anyone to design, manufacture and sell RISC-V chips and software. Although it is not the first open-source instruction set, it is significant because of its design, which makes it suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones and tiny embedded systems.

[0048] With the vigorous development of computer technology, the processing performance of chip hardware is getting stronger and stronger, and the speed of processing data is getting faster and faster. Among them, the CPU (central processing unit) executes instructions in the internal pipeline. The execution process of an instruction can be divided into several steps, each step is completed by an independent circuit, and the operations of different steps of different instructions are overlapped, so as to realize parallel processing of multiple instructions, so as to speed up the program running process.

[0049] Generally, the CPU will directly execute the machine code converted from the assembly code, and the technical personnel do not need to know the specific content of the machine code executed by the CPU, but in some application scenarios, the technical personnel need to view the internal instruction execution pipeline change of the CPU, and the technical personnel have the demand to know the assembly code corresponding to the machine code currently executed by the CPU.

[0050] At present, in the absence of a technical solution for quickly converting machine code into assembly code, technical personnel have difficulty in directly obtaining CPU execution information from machine code for analysis.

[0051] The machine code instruction conversion method, device, electronic equipment and readable storage medium provided by the present application aim to solve the above technical problems of the prior art.

[0052] Specifically, the present application embodiment provides a machine code instruction conversion method, which can be implemented by a machine code conversion device / system. The device / system related to the present application embodiment can conveniently convert machine code, solving the technical problem of converting the machine code executed by the CPU into the corresponding assembly code.

[0053] The technical solutions of the present application embodiments and the technical effects of the present application will be described below through the description of several exemplary embodiments. It should be pointed out that the following embodiments can be mutually referenced, borrowed or combined. For the same terms, similar features and similar implementation steps in different embodiments, they will not be described repeatedly.

[0054] A machine code instruction conversion method is provided in the present application embodiment, as shown in Figure 1 The method comprises the following steps:

[0055] Step S101, obtaining a machine code instruction to be converted; the machine code instruction comprises an operation code, a first operand, a second operand, a third operand and an original immediate number.

[0056] In the present application embodiment, the machine code instruction to be converted can be a machine code instruction that needs to be converted in any application scenario with machine code conversion demand, and the present application does not limit the source of the machine code instruction.

[0057] Specifically, as an example, the machine code instruction can be a machine code of a 32-bit RISC-V processor, the machine code instruction can be obtained from a preset module recording the execution of CPU instructions, and the preset module is not limited in the application. The preset module can store a plurality of machine code instructions and the execution time corresponding to each machine code instruction.

[0058] In the embodiments of the application, the machine code instruction can have different formats, and the specific format and division method are not limited in the application.

[0059] In some embodiments, the machine code can be divided according to the number of bits into an operation code, a first operand, a second operand, a third operand and an original immediate number. The operation code can be used to represent the operation type of the machine code instruction; the first operand can be used to represent the register name of the target register; the second operand can be used to determine the target assembly instruction corresponding to the machine code instruction; and the third operand can be used to represent the register name of the source register.

[0060] In the embodiments of the application, the operation code, the first operand, the second operand, the third operand and the original immediate number can be sequentially divided according to the number of bits of the machine code instruction, wherein the naming of the first operand, the second operand and the third operand only serves to distinguish, and in fact does not limit the naming method of the several parts obtained by dividing the machine code instruction according to the number of bits.

[0061] In other embodiments, the machine code instruction does not necessarily have each of the operation code, the first operand, the second operand, the third operand and the original immediate number, and the machine code instruction can have only one or more of the above items, which is not limited in the application. Each item of data divided in the machine code instruction is converted respectively.

[0062] In one example, when the machine code instruction is a RISC-V instruction, the machine code instruction can have different instruction formats according to different instruction types, the instruction format can be agreed by the framework author in advance, and the instruction can be divided into different parts according to the instruction format, which is not limited in the application.

[0063] In step S102, the machine code instruction is parsed to determine the target assembly instruction corresponding to the operation code and the second operand, the register name corresponding to the first operand and the third operand respectively, and the target immediate number obtained by converting the original immediate number. Specifically, the original immediate number can be converted into a target immediate number of a preset base.

[0064] In the embodiments of the present application, the correspondence between the operation code and the second operand and the target assembly instruction can be pre-set, and the target assembly instruction corresponding to the operation code and the second operand can be determined based on the correspondence. Similarly, the correspondence between the first operand and the third operand and the register name can be pre-set, and the register name corresponding to the first operand and the third operand respectively can be determined based on the correspondence. The above correspondence can be integrated into the preset rule information, and the preset rule information can be arranged into a manual or an instruction set in an actual application scenario, which is not limited in the present application.

[0065] As an example, the preset rule information can be arranged into the instruction set of the 32-bit RISC-V processor and the RISC-V standard manual. The machine code instruction to be converted can be the machine code of the 32-bit RISC-V processor, wherein the operation code can be 0-6 bits of the machine code instruction, the first operand can be 7-11 bits of the machine code instruction, the second operand can be 12-14 bits of the machine code instruction, the third operand can be 15-19 bits of the machine code instruction, and the original immediate number can be 20-31 bits of the machine code instruction. The target assembly instruction corresponding to the operation code and the second operand, and the register name corresponding to the first operand and the third operand respectively can be determined according to the preset rule information.

[0066] The above steps describe a conversion step of converting the machine code instruction of a type of assembly instruction into assembly code, and the machine code instruction conversion step of the remaining types of assembly instructions in the RISC-V instruction set can be derived in the same way, which is not limited in the present application.

[0067] In the embodiments of the present application, when the preset rule information includes the correspondence between the operation code, the second operand and the target assembly instruction, the target assembly instruction corresponding to the operation code and the second operand can be determined, which can specifically include the following steps:

[0068] (1) determining at least one candidate assembly instruction corresponding to the operation code based on the preset rule information and the operation code. Specifically, at least one candidate assembly instruction corresponding to the operation code can be determined based on the preset rule information. The operation code can correspond to multiple candidate assembly instructions, and the target assembly instruction can be further determined based on the second operand.

[0069] (2) taking the assembly instruction corresponding to the second operand in the at least one candidate assembly instruction as the target assembly instruction based on the preset rule information and the second operand.

[0070] As an example, the preset rule information can include, for example, Figure 2The corresponding relationship table is shown, where the table has 5 columns, and the meanings from left to right are original immediate number, third operand, second operand, first operand and operation code respectively. Assuming that the operation code of the machine code instruction to be converted is "000011", according to the preset rule information, the instructions corresponding to "000011" are "LB", "LH", "LW", "LD", "LBU", "LHU" and "LWU". The instructions corresponding to the operation code "000011" can be taken as candidate assembly instructions.

[0071] Further, the target assembly instruction can be determined from the candidate assembly instructions according to the second operand. As shown, if the second operand is "000", the target assembly instruction is "LB"; if the second operand is "001", the target assembly instruction is "LH"; if the second operand is "010", the target assembly instruction is "LW"; if the second operand is "100", the target assembly instruction is "LBU"; if the second operand is "101", the target assembly instruction is "LHU". Figure 2

[0072] In the embodiment of the present application, determining the register names corresponding to the first operand and the third operand can include the following steps: determining the instruction type of the target assembly instruction, and determining the register names corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand and the third operand.

[0073] In the embodiment of the present application, the instruction type of the target assembly instruction can be a floating point instruction or a non-floating point instruction. In the assembly instruction, the register names will be different according to whether the instruction type is a floating point instruction.

[0074] After the register name corresponding to the first operand and the register name corresponding to the third operand are determined, the register name corresponding to the machine code instruction can be further determined according to the instruction type of the target assembly instruction.

[0075] Step S103: combining the target assembly instruction, the register name and the target immediate number based on the preset rule information to obtain the assembly code corresponding to the machine code instruction; where the rule information includes the assembly format for the target assembly instruction.

[0076] In actual application scenarios, the preset rule information can be a RISC-V standard manual. The assembly format of the target assembly instruction can be queried in the standard manual, the register name and the target immediate number are filled into the assembly format of the target assembly instruction, and the assembly code corresponding to the machine code instruction is obtained.

[0077] ​The machine code instruction conversion method described above obtains a machine code instruction to be converted, wherein the machine code instruction can include an operation code, a first operand, a second operand, a third operand, and an original immediate number. Then the machine code instruction is parsed to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained based on the original immediate number after conversion. The target assembly instruction, the register names, and the target immediate number obtained can be combined based on preset rule information to obtain an assembly code corresponding to the machine code instruction, which realizes convenient conversion of the machine code instruction into the assembly code, and is beneficial to further analysis of the assembly code by technical personnel, effectively filling the technical gap of converting machine code into assembly code.

[0078] In the embodiments of the present application, the register name includes a register name of a target register and a source register corresponding to the machine code instruction.

[0079] In the embodiments of the present application, the register name corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction, the first operand, and the third operand, which can include the following steps:

[0080] The register name of the target register corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction and the first operand;

[0081] The register name of the source register corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction and the third operand.

[0082] Specifically, the register name of the target register corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction and the first operand, which can include the following steps:

[0083] At least two first register names are determined based on the first operand and the preset rule information; wherein the preset rule further includes a corresponding relationship between each first register name and the instruction type; and the register name corresponding to the instruction type of the target assembly instruction in the at least two first register names is taken as the register name of the target register.

[0084] The register name of the source register corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction and the third operand, which can include the following steps:

[0085] At least two second register names are determined based on the third operand and the preset rule information; wherein the preset rule further includes a corresponding relationship between each second register name and the instruction type; and the register name corresponding to the instruction type of the target assembly instruction in the at least two second register names is taken as the register name of the source register.

[0086] In one example, when the machine code instruction to be converted is an instruction of a 32-bit RISCV processor, the correspondence between the third operand, the first operand, the instruction type, and the register name in the preset rule information can be as shown in the following table. Figure 3

[0087] The operation code can be bits 0-6 of the machine code instruction, the first operand can be bits 7-11 of the machine code instruction, the second operand can be bits 12-14 of the machine code instruction, the third operand can be bits 15-19 of the machine code instruction, and the original immediate number can be bits 20-31 of the machine code instruction.

[0088] In this example, the first operand and the third operand can be 5-bit binary numbers, and it is assumed that the first operand is "01111" and the third operand is "10011". The determined target assembly instruction is LW.

[0089] According to Figure 3 , the first operand "01111" corresponds to the first register name "s3" and "fs3", and the third operand corresponds to the second register name "a5" and "fa5". According to the instruction type of the instruction LW, which is a non-floating-point instruction, it can be further determined that "s3" is the register name of the target register corresponding to the first operand, and "a5" is the register name of the source register corresponding to the third operand.

[0090] The present application provides a possible implementation in the embodiments, and the machine code instruction conversion method provided by the present application can further include: determining the execution time corresponding to the machine code instruction; and displaying the assembly code corresponding to the machine code instruction and the execution time on a preset user interface.

[0091] Specifically, as an example, the machine code instruction can be a machine code of a 32-bit RISC-V processor, and the machine code instruction can be obtained from a preset module that records the execution of CPU instructions. The present application does not limit the preset module. The preset module can store a plurality of machine code instructions and the execution time corresponding to each machine code instruction.

[0092] After converting the machine code instruction to be converted into assembly code, the execution time corresponding to the machine code instruction can be used as the execution time corresponding to the target assembly code after conversion. The target assembly code and the corresponding execution time can be displayed on a preset user interface, so that technical personnel can clearly and directly view the execution of the CPU instructions.

[0093] ​In some embodiments, after obtaining the target assembly code and the corresponding execution time, the computer can perform preliminary analysis, for example, in the case of multiple target assembly codes and corresponding execution times, the computer can classify the multiple target assembly codes, the classification basis can be instruction function, instruction category, etc., the computer can count the execution time used by each category, and the statistical result is displayed to the user.

[0094] The machine code instruction conversion method in the present application can be as shown in the figure Figure 4 The machine code instruction conversion method in the present application can be as shown in the figure

[0095] Step S401, obtaining machine code instructions to be converted; the machine code instructions include operation code, first operand, second operand, third operand and original immediate number;

[0096] Step S402, parsing the machine code instructions, determining at least one candidate assembly instruction corresponding to the operation code based on the preset rule information and the operation code; wherein, the preset rule information includes the corresponding relationship between the operation code, the second operand and the target assembly instruction;

[0097] Step S403, based on the preset rule information and the second operand, taking the assembly instruction corresponding to the second operand in the at least one candidate assembly instruction as the target assembly instruction;

[0098] Step S404, determining the instruction type of the target assembly instruction, determining the register name corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand and the third operand; specifically, at least two first register names can be determined based on the first operand and the preset rule information, and the register name corresponding to the instruction type of the target assembly instruction in the at least two first register names is taken as the register name of the target register; similarly, at least two second register names can be determined based on the third operand and the preset rule information, and the register name corresponding to the instruction type of the target assembly instruction in the at least two second register names is taken as the register name of the source register;

[0099] Step S405, converting the original immediate number into a target immediate number of a preset base;

[0100] Step S406, combining the target assembly instruction, the register name and the target immediate number based on the preset rule information to obtain the assembly code corresponding to the machine code instruction; wherein, the rule information includes the assembly format for the target assembly instruction;

[0101] Step S407, determining the execution time corresponding to the machine code instruction, and displaying the assembly code corresponding to the machine code instruction and the execution time on the preset user interface.

[0102] The machine code instruction conversion method described above obtains a machine code instruction to be converted, wherein the machine code instruction can include an operation code, a first operand, a second operand, a third operand, and an original immediate number. Then the machine code instruction is parsed to determine a target assembly instruction corresponding to the operation code and the second operand, a register name corresponding to the first operand and the third operand respectively, and a target immediate number obtained based on the original immediate number conversion. The target assembly instruction, the register name, and the target immediate number obtained based on the preset rule information can be combined to obtain the assembly code corresponding to the machine code instruction, which realizes the conversion of the machine code instruction to the assembly code, and is beneficial to the further analysis of the assembly code by the technical personnel, effectively filling the technical gap of converting the machine code to the assembly code.

[0103] As an example, the preset rule information can be sorted as the instruction set of the 32-bit RISC-V processor and the RISC-V standard manual. The machine code to be converted can be the machine code of the 32-bit RISC-V processor, wherein the operation code can be 0-6 bits of the machine code instruction, the first operand can be 7-11 bits of the machine code instruction, the second operand can be 12-14 bits of the machine code instruction, the third operand can be 15-19 bits of the machine code instruction, and the original immediate number can be 20-31 bits of the machine code instruction.

[0104] Suppose the machine code instruction to be converted is "0000 0000 0000 1001 1010 0111 10000011", the parsing process is as follows:

[0105] (1) The operation code of 0-6 bits is "000011", referring to the corresponding relationship table in Figure 2 , the instructions corresponding to "000011" are "LB", "LH", "LW", "LD", "LBU", "LHU" and "LWU". The instruction corresponding to the operation code "000011" can be taken as a candidate assembly instruction.

[0106] (2) The second operand of 12-14 bits is "010", referring to the corresponding relationship table in Figure 2 , from the candidate assembly instruction, it is determined that LW is the target assembly instruction.

[0107] (3) The first operand of 7-11 bits is "01111", referring to the corresponding relationship diagram in Figure 3 , the corresponding first register name is "s3" and "fs3"; the second register name corresponding to the third operand of 15-19 bits is "a5" and "fa5". According to the instruction type of the instruction LW is a non-floating point instruction, it can be further determined that "s3" is the register name of the target register corresponding to the first operand, and "a5" is the register name of the source register corresponding to the third operand.

[0108] (4) 31-20 bits 000000000000 is an immediate number, converted to hexadecimal is 0x0.

[0109] Thus, the assembly instruction corresponding to the machine code instruction and the corresponding operation register and the immediate number are obtained, and the complete assembly code corresponding to the machine code can be obtained by combination in the next step.

[0110] (5) Referring to the RISC-V standard manual, for example, the target assembly instruction is LW, and according to the standard manual, the assembly format of the LW instruction is like "lw rd, offset(rs1)", wherein rd is the register name of the source register, and rs1 is the register name of the target register.

[0111] (6) The target assembly instruction, the register name and the immediate number are combined to obtain the complete assembly code "lwa5, 0(s3)".

[0112] The machine code conversion method described above describes a step of converting a machine code instruction in an instruction format into assembly code. The format of the machine code instruction is not limited in the present application, and the conversion method of machine code instructions in other formats can be derived according to the above method.

[0113] The embodiment of the present application provides a machine code instruction conversion device, as shown in the figure, the machine code instruction conversion device 50 can include: machine code acquisition module 501, machine code analysis module 502 and combination module 503, wherein, Figure 5

[0114] The machine code acquisition module 501 is configured to acquire a machine code instruction to be converted; the machine code instruction includes an operation code, a first operand, a second operand, a third operand and an original immediate number;

[0115] The machine code analysis module 502 is configured to analyze the machine code instruction, determine a target assembly instruction corresponding to the operation code and the second operand, a register name corresponding to the first operand and the third operand respectively, and a target immediate number obtained based on the original immediate number after conversion;

[0116] The combination module 503 is configured to combine the target assembly instruction, the register name and the target immediate number based on preset rule information to obtain assembly code corresponding to the machine code instruction; wherein the rule information includes an assembly format for the target assembly instruction.

[0117] ​The machine code instruction conversion device described above obtains a machine code instruction to be converted, wherein the machine code instruction can include an operation code, a first operand, a second operand, a third operand, and an original immediate number. Then the machine code instruction is parsed to determine a target assembly instruction corresponding to the operation code and the second operand, register names corresponding to the first operand and the third operand respectively, and a target immediate number obtained based on the original immediate number. The target assembly instruction, the register names, and the target immediate number obtained can be combined based on preset rule information to obtain an assembly code corresponding to the machine code instruction, which realizes convenient conversion of the machine code instruction into the assembly code, and is beneficial to further analysis of the assembly code by technical personnel, and effectively fills the technical gap of conversion of machine code into assembly code.

[0118] In the embodiment of the present application, the preset rule information further includes a corresponding relationship between the operation code, the second operand, and the target assembly instruction; and the machine code parsing module 502, when determining the target assembly instruction corresponding to the operation code and the second operand, is specifically configured to:

[0119] determine at least one candidate assembly instruction corresponding to the operation code based on the preset rule information and the operation code;

[0120] take, as the target assembly instruction, an assembly instruction corresponding to the second operand in the at least one candidate assembly instruction based on the preset rule information and the second operand.

[0121] In the embodiment of the present application, the machine code parsing module 502, when determining the register names corresponding to the first operand and the third operand respectively, is specifically configured to:

[0122] determine an instruction type of the target assembly instruction, and determine the register names corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand, and the third operand.

[0123] In the embodiment of the present application, the register names include register names of target registers and source registers corresponding to the machine code instruction;

[0124] The machine code parsing module 502, when determining the register names corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand, and the third operand, is specifically configured to:

[0125] determine the register names of the target registers corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the first operand;

[0126] determine the register names of the source registers corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the third operand.

[0127] In the embodiment of the present application, the machine code analysis module 502 is specifically configured to:

[0128] determine at least two first register names based on the first operand and the preset rule information; the preset rule further comprises a corresponding relationship between each first register name and the instruction type; and the register name corresponding to the instruction type of the target assembly instruction in the at least two first register names is taken as the register name of the target register;

[0129] In the embodiment of the present application, the machine code analysis module 502 is specifically configured to:

[0130] determine at least two second register names based on the third operand and the preset rule information; the preset rule further comprises a corresponding relationship between each second register name and the instruction type; and the register name corresponding to the instruction type of the target assembly instruction in the at least two second register names is taken as the register name of the source register.

[0131] In the embodiment of the present application, the display module is specifically configured to:

[0132] determine the execution time corresponding to the machine code instruction;

[0133] display the assembly code corresponding to the machine code instruction and the execution time on the preset user interface.

[0134] The apparatus of the embodiment of the present application can execute the method provided by the embodiment of the present application, and the implementation principles are similar. The actions performed by each module in the apparatus of each embodiment of the present application are corresponding to the steps in the method of each embodiment of the present application. For the detailed function description of each module of the apparatus, refer to the description of the corresponding method in the foregoing description, which will not be repeated here.

[0135] In the embodiment of the present application, an electronic device (computer device / equipment / system) is provided, which comprises a memory, a processor and a computer program stored in the memory. The processor executes the above computer program to implement the steps of a machine code instruction conversion method. Compared with related technologies, the machine code instruction conversion method can conveniently convert machine code instructions into assembly codes, which is beneficial for technical personnel to further analyze the assembly codes and effectively fills the technical gap of converting machine code into assembly code.

[0136] In an optional embodiment, an electronic device is provided, as shown in Figure 6 Figure 6 ​The electronic device 4000 shown includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 can also include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception, etc. It should be noted that the transceiver 4004 is not limited to one in actual application, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0137] The processor 4001 can be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic device, a transistor logic device, a hardware component or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in combination with the disclosure. The processor 4001 can also be a combination of computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0138] The bus 4002 can include a path for transmitting information between the above-mentioned components. The bus 4002 can be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience, Figure 6 In the figure, only one thick line is used to represent the bus, but it does not mean that there is only one bus or only one type of bus.

[0139] The memory 4003 can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions that are not to be changed by the computer; a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions for execution by the processor 4001; an EEPROM (Electrically Erasable Programmable Read-Only Memory), a CD-ROM (Compact Disc Read-Only Memory) or other optical disk storage, a magnetic disk storage or other magnetic storage devices, or any other medium capable of storing computer instructions and capable of being read by a computer, without limitation.

[0140] The memory 4003 is configured to store a computer program for implementing the embodiments of the present application, and the processor 4001 is configured to control the execution of the computer program stored in the memory 4003. The processor 4001 is configured to execute the computer program stored in the memory 4003 to implement the steps of the method embodiments described above.

[0141] The electronic device includes, but is not limited to, a mobile phone, a notebook computer, a PAD, and other mobile terminals such as a digital TV, a desktop computer, and other fixed terminals.

[0142] The embodiments of the present application provide a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the steps and corresponding contents of the method embodiments described above can be implemented.

[0143] The embodiments of the present application also provide a computer program product, and the computer program product includes a computer program. When the computer program is executed by a processor, the steps and corresponding contents of the method embodiments described above can be implemented.

[0144] The terms "first", "second", "third", "fourth", "1", "2", and the like (if any) in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described.

[0145] It should be understood that although each operation step in the flowchart of the embodiments of the present application is indicated by an arrow, the implementation order of the steps is not limited to the order indicated by the arrow. Unless explicitly stated herein, in some implementation scenarios of the embodiments of the present application, the implementation steps in each flowchart can be executed in other orders as required. In addition, part or all of the steps in each flowchart can include multiple sub-steps or multiple stages based on the actual implementation scenario. Part or all of these sub-steps or stages can be executed at the same time, and each of these sub-steps or stages can also be executed at different times. In the scenario where the execution times are different, the execution order of these sub-steps or stages can be flexibly configured as required, and the embodiments of the present application do not limit this.

[0146] The above is only an optional implementation of some implementation scenarios of the present application. It should be pointed out that, for ordinary skilled persons in the technical field, other similar implementation means based on the technical idea of the present application without departing from the technical concept of the present application also belong to the protection scope of the embodiments of the present application.

Claims

1. A machine code instruction conversion method, characterized in that, include: Obtain the machine code instruction to be converted; the machine code instruction includes an opcode, a first operand, a second operand, a third operand, and a raw immediate value; The machine code instruction is parsed to determine the target assembly instruction corresponding to the opcode and the second operand, the register names corresponding to the first operand and the third operand respectively, and the target immediate value obtained after conversion based on the original immediate value; Based on preset rule information, the target assembly instruction, the register name, and the target immediate value are combined to obtain the assembly code corresponding to the machine code instruction; wherein, the rule information includes the assembly format for the target assembly instruction; The preset rule information also includes the correspondence between the opcode, the second operand, and the target assembly instruction; determining the target assembly instruction corresponding to the opcode and the second operand includes: Based on the preset rule information and the opcode, at least one candidate assembly instruction corresponding to the opcode is determined; Based on the preset rule information and the second operand, the assembly instruction corresponding to the second operand among the at least one candidate assembly instructions is taken as the target assembly instruction.

2. The machine code instruction conversion method according to claim 1, characterized in that, Determining the register names corresponding to the first operand and the third operand respectively includes: The instruction type of the target assembly instruction is determined, and the register name corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction, the first operand, and the third operand.

3. The machine code instruction conversion method according to claim 2, characterized in that, The register name includes the register name of the target register and the source register corresponding to the machine code instruction; Determining the register name corresponding to the machine code instruction based on the instruction type of the target assembly instruction, the first operand, and the third operand includes: The register name of the target register corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction and the first operand; The register name of the source register corresponding to the machine code instruction is determined based on the instruction type of the target assembly instruction and the third operand.

4. The machine code instruction conversion method according to claim 3, characterized in that, The step of determining the register name of the target register corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the first operand includes: At least two first register names are determined based on the first operand and the preset rule information; the preset rule also includes the correspondence between each first register name and the instruction type; the register name that corresponds to the instruction type of the target assembly instruction among the at least two first register names is used as the register name of the target register; The step of determining the register name of the source register corresponding to the machine code instruction based on the instruction type of the target assembly instruction and the third operand includes: At least two second register names are determined based on the third operand and the preset rule information; the preset rule also includes the correspondence between each second register name and the instruction type, and the register name that corresponds to the instruction type of the target assembly instruction among the at least two second register names is used as the register name of the source register.

5. The machine code instruction conversion method according to any one of claims 1-4, characterized in that, The method further includes: Determine the execution time corresponding to the machine code instruction; The assembly code corresponding to the machine code instruction and the execution time are displayed on a preset user interface.

6. A machine code instruction conversion device, characterized in that, include: The machine code acquisition module is used to acquire the machine code instruction to be converted; the machine code instruction includes an opcode, a first operand, a second operand, a third operand, and a raw immediate value; The machine code parsing module is used to parse the machine code instructions, determine the target assembly instruction corresponding to the opcode and the second operand, the register names corresponding to the first operand and the third operand respectively, and the target immediate value obtained after conversion based on the original immediate value; The combination module is used to combine the target assembly instruction, the register name, and the target immediate value based on preset rule information to obtain the assembly code corresponding to the machine code instruction; wherein, the rule information includes the assembly format for the target assembly instruction; The preset rule information also includes the correspondence between the opcode, the second operand, and the target assembly instruction; the machine code parsing module is further configured to determine at least one candidate assembly instruction corresponding to the opcode based on the preset rule information and the opcode. Based on the preset rule information and the second operand, the assembly instruction corresponding to the second operand among the at least one candidate assembly instructions is taken as the target assembly instruction.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the machine code instruction conversion method according to any one of claims 1-5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-5.

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