Method and system for accelerating NVMe SSD trim

Abstract

The application discloses a method and system for accelerating NVMe SSD Trim. After receiving a Dataset Management command, the application writes a Trim Range into RAM, and then reads the Trim Range in the RAM according to an address configured by firmware. A rearrangement acceleration module sorts the Range according to the starting LBA of each Range. After sorting the Range, the starting LBA and the logical length of each Range are checked from Range 0 to Range n, and it is checked whether the value contains the starting LBA of the next Range. If the value contains the starting LBA of the next Range and the attributes are the same, the Range and the next Range are combined into the same Range. In the case that the LBA Range overlaps, the LBA Range is sorted and combined, and then is displayed to the firmware, so that the processing complexity of the Dataset Management command of the firmware is reduced, and the CPU occupation is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a method and system for accelerating NVMe SSD Trim. BACKGROUND

[0002] NVMe SSD is a solid state drive (Solid State Disk) that complies with the Non-Volatile Memory express (NVMe) host controller interface specification. The SSD is composed of a controller and a memory. An excellent NVMe SSD controller can fully utilize the low latency and parallelism of the PCIE channel, greatly improve the read / write performance of the solid state disk under controllable storage costs, reduce the high latency caused by the AHCI interface, and completely liberate the ultimate performance of the solid state disk in the STAT era.

[0003] In the interaction between the NVMe SSD and the host, the Dataset Management command is an IO command for data trim issued by the host, which is accompanied by an LBA Range, and can perform trim operation on a certain LBA or several LBAs. The trimmed LBA will be marked as invalid, so that garbage collection can be performed. However, in the LBA Range issued by the host, there may be many overlapping LBA Ranges, and when the FW processes these LBA Ranges, it causes additional CPU burden. SUMMARY

[0004] In view of the defects of the prior art, the present application discloses a method and system for accelerating NVMe SSD Trim, which can sort and merge the LBA Range in the case of overlapping, and then present it to the firmware, thereby reducing the processing complexity of the firmware for the Dataset Management command and reducing the CPU occupation.

[0005] To solve the technical problem, the technical scheme adopted by the present application is: a method for accelerating NVMe SSD Trim, comprising the following steps:

[0006] S01), the firmware receives the Dataset Management command and writes the Trim Range into the RAM;

[0007] S02), the firmware writes the address where the Trim Range is located into the register of the Trim Range rearrangement acceleration module;

[0008] S03), the firmware writes an enable signal to the enable register of the Trim Range rearrangement acceleration module;

[0009] S04), the Trim Range rearrangement acceleration module reads the Trim Range in the RAM according to the address configured by the firmware;

[0010] S05), the Trim Range rearrangement acceleration module sorts the Range according to the starting LBA of each Range;

[0011] S06), starting from Range 0, the starting LBA and the logical length of each Range are checked to see if the starting LBA and the logical length of each Range contain the starting LBA of the next Range, if they do and the attributes are the same, step S07) is entered, otherwise the step is repeated;

[0012] S07), the Range and the next Range are merged into one Range, the starting LBA of the merged Range is the starting LBA of the previous Range, the logical length is D, D = A + B - C, A represents the starting LBA of the latter Range, B represents the logical length of the latter Range, and C represents the starting LBA of the former Range, the address stored in the register of the Trim Range rearrangement acceleration module is updated to the configuration address + the processed range address, and step S08) is executed;

[0013] S08), the next group of Range is checked, and step S09) is entered;

[0014] S09), after all Range checks are completed, the state register of the Trim Range rearrangement acceleration module is updated to inform the firmware that the rearrangement is complete.

[0015] Further, in step S05), the Range is sorted from small to large.

[0016] The application also discloses a system for accelerating NVMe SSD Trim, comprising firmware, a Trim Range rearrangement acceleration module and RAM;

[0017] The firmware is used for receiving a Dataset Management command, writing the Trim Range into the RAM, enabling the Trim Range rearrangement acceleration module, and writing the address where the Trim Range is located into the register of the Trim Range rearrangement acceleration module;

[0018] The Trim Range rearrangement acceleration module comprises a control register, a quick sorting module and a merge range module, the control register receives an address of the Trim Range written by the firmware and receives an enable signal of the firmware to enable the Trim Range rearrangement acceleration module to work;

[0019] The quick sorting module reads the Trim Range in the RAM and sorts the Range according to the starting LBA of each Range;

[0020] The merge range module checks the sum of the starting LBA and the logical length of each Range from Range 0 to Range n, and checks whether the sum of the starting LBA and the logical length of each Range contains the starting LBA of the next Range, if yes and the attributes are the same, the Range and the next Range are merged into one Range, the starting LBA of the merged Range is the starting LBA of the former Range, and the logical length is D, D = A + B - C, A represents the starting LBA of the latter Range, B represents the logical length of the latter Range, and C represents the starting LBA of the former Range;

[0021] The RAM is used for storing the Trim Range and interacting with the firmware and the Trim Range rearrangement acceleration module.

[0022] Further, the quick sorting module sorts the Range from small to large.

[0023] The present application has the following beneficial effects: the present application sorts and merges the LBA Range in the case of overlapping, and presents the LBA Range to the firmware, reduces the processing complexity of the firmware to the Dataset Management command, and the hardware acceleration module is also realized, which reduces the CPU loss caused by the firmware processing the Trim Range and reduces the CPU occupation. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 FIG. 1 is a structural diagram of the LBA Range;

[0025] Figure 2 FIG. 2 is a flow chart of the method described in Embodiment 1;

[0026] Figure 3 FIG. 3 is a principle block diagram of the system described in Embodiment 2. DETAILED DESCRIPTION

[0027] The present application will be further described below in combination with the drawings and specific embodiments.

[0028] Embodiment 1

[0029] The embodiment discloses a method for accelerating NVMe SSD Trim, as shown in Figure 1 The structure of LBA Range is composed of Context Attributes, Length in Logical Blocks and Starting LBA. Each Dataset Data command can contain multiple Range. When Range overlaps, the Starting LBA of Range1 is in the range of Range0, and the Starting LBA of Range2 is in the range of Range1. Therefore, the overlapping LBA is only contained by 1 Range.

[0030] The method is to realize a hardware merging Range to accelerate, as shown in Figure 2 The method comprises the following steps:

[0031] S01, the firmware receives a Dataset Management command, and writes a Trim Range into a RAM;

[0032] S02, the firmware writes an address of the Trim Range into a register of a Trim Range rearrangement acceleration module;

[0033] S03, the firmware writes an enable signal into an enable register of the Trim Range rearrangement acceleration module;

[0034] S04, the Trim Range rearrangement acceleration module reads the Trim Range in the RAM according to the address configured by the firmware;

[0035] S05, the Trim Range rearrangement acceleration module sorts the Range from small to large according to the Starting LBA of each Range;

[0036] S06, for the sorted Range, starting from Range0 to Rangen, the Starting LBA and the logical length of each Range are checked to see whether the Starting LBA and the logical length of each Range contain the Starting LBA of the next Range, if yes and the attributes are the same, step S07 is entered, otherwise, the step is repeated;

[0037] S07), merge the Range and the next Range into one Range, the start LBA of the merged Range is the start LBA of the former Range, the logical length is D, D=A+B-C, A represents the start LBA of the latter Range, B represents the logical length of the latter Range, and C represents the start LBA of the former Range, update the address stored in the register of the Trim Range rearrangement acceleration module to the configuration address+the processed range address, and perform step S08);

[0038] S08), check the next group of Range, and enter step S09);

[0039] S09), all Range are checked, the state register of the Trim Range rearrangement acceleration module is updated, and it is informed to the firmware that the rearrangement is completed.

[0040] Embodiment 2

[0041] This embodiment discloses a system for accelerating NVMe SSD Trim, as shown in FIG. 1, which comprises a firmware, a Trim Range rearrangement acceleration module and a RAM. Figure 3

[0042] The firmware is used to receive a Dataset Management command, write a Trim Range into the RAM, enable the Trim Range rearrangement acceleration module, and write the address where the Trim Range is located into the register of the Trim Range rearrangement acceleration module.

[0043] The Trim Range rearrangement acceleration module comprises a control register, a quick sorting module and a merge range module, the control register receives the address where the Trim Range is located written by the firmware and receives an enabling signal of the firmware, so that the Trim Range rearrangement acceleration module starts to work.

[0044] The quick sorting module reads the Trim Range in the RAM and sorts the Range from small to large according to the start LBA of each Range.

[0045] ​The merged Range module checks the sum of the start LBA and the logical length of each Range, starting from Range 0 to Range n, to see if the value contains the start LBA of the next Range, if it contains and the attributes are the same, then the Range and the next Range are merged into one Range, the start LBA of the merged Range is the start LBA of the former Range, the logical length is D, D=A+B-C, A represents the start LBA of the latter Range, B represents the logical length of the latter Range, and C represents the start LBA of the former Range;

[0046] The RAM is used to store the Trim Range and interact with the firmware and the Trim Range rearrangement acceleration module.

[0047] After all the Range is checked, the state register of the Trim Range rearrangement acceleration module is updated to inform the firmware that the rearrangement is completed.

[0048] The above description is only the basic principle and the preferred embodiment of the present application, and the improvements and substitutions made by the person skilled in the art according to the present application belong to the protection scope of the present application.

Claims

1. A method for accelerating NVMe SSD Trim, characterized in that: Includes the following steps: S01) The firmware receives the Dataset Management command and writes the Trim Range into RAM; S02) The firmware writes the address of the Trim Range to the register of the Trim Range rearrangement acceleration module; S03) Write the firmware enable signal to the enable register of the Trim Range rearrangement acceleration module; S04) The Trim Range rearrangement acceleration module reads the Trim Range in RAM according to the address configured in the firmware; S05), the Trim Range rearrangement acceleration module sorts the Ranges according to the starting LBA of each Range; S06) For the sorted Range, starting from Range0, check the sum of the starting LBA and logical length of each Range. Check if the sum of the starting LBA and logical length of each Range contains the starting LBA of the next Range. If it contains and the attributes are the same, proceed to step S07; otherwise, repeat this step. (S07) Merge the current Range and the next Range into a single Range. The starting LBA of the merged Range is taken from the starting LBA of the previous Range, and the logical length is D, where D = A + BC, A represents the starting LBA of the next Range, B represents the logical length of the next Range, and C represents the starting LBA of the previous Range. Update the address stored in the register of the Trim Range rearrangement acceleration module to the configuration address + the processed range address, and execute step S08). S08), Check the next group of Ranges and proceed to step S09). S09) After all Range checks are completed, update the status register of the Trim Range rearrangement acceleration module to inform the firmware that the rearrangement is complete.

2. The method for accelerating NVMe SSD Trim according to claim 1, characterized in that: In step S05), the Ranges are sorted from smallest to largest.

3. A system for accelerating NVMe SSD Trim, characterized in that: This includes firmware, the Trim Range rearrangement acceleration module, and RAM; The firmware is used to receive Dataset Management commands, write the Trim Range into RAM, enable the Trim Range rearrangement acceleration module, and write the address of the Trim Range into the register of the Trim Range rearrangement acceleration module. The Trim Range rearrangement acceleration module includes a control register, a fast sorting module, and a merge range module. The control register receives the address of the Trim Range written by the firmware and receives the enable signal from the firmware to enable the Trim Range rearrangement acceleration module to start working. The quicksort module reads the Trim Range from RAM and sorts the Ranges according to their starting LBA. The merge Range module checks the sum of the starting LBA and logical length of each sorted Range, starting from Range0. It then checks if the sum of the starting LBA and logical length of each Range includes the starting LBA of the next Range. If they do and have the same attributes, the Range and the next Range are merged into the same Range. The starting LBA of the merged Range is taken from the starting LBA of the previous Range, and the logical length is taken as D, where D = A + BC, where A represents the starting LBA of the next Range, B represents the logical length of the next Range, and C represents the starting LBA of the previous Range. RAM is used to store Trim Ranges and interact with the firmware and Trim Range rearrangement acceleration module.

4. The system for accelerating NVMe SSD Trim according to claim 3, characterized in that: The quicksort module sorts Ranges from smallest to largest.

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