Method for establishing spice macro model of balanced super-junction mosfet drain-source capacitance

Abstract

The application discloses a SPICE macro model establishment method of balancing drain-source capacitance of a super-junction MOSFET, which is applied to the field of electronic component modeling and solves the problems of high fitting difficulty and poor precision in the modeling scheme of the existing super-junction MOSFET parasitic capacitance. The application firstly tests and obtains data of the super-junction MOSFET parasitic capacitance changing with the drain-source voltage; then establishes an equivalent circuit topology of the drain-source capacitance based on the device depletion mechanism; further extracts cell process parameters reversely from the capacitance test data, builds a mathematical description of the drain-source capacitance, and completes coefficient fitting based on mathematical software to determine macro model circuit parameters; finally, the SPICE model is written and packaged, and finally the drain-source capacitance macro model module which can be called in the super-junction MOSFET SPICE model is obtained. The establishment method is based on the physical mechanism of the super-junction MOSFET, can realize high-precision fitting of the drain-source capacitance in the full-voltage range in the semi-logarithmic coordinate, and can be widely applied to the conventional super-junction MOSFET products of charge balance.

Description

Technical Field

[0001] This invention belongs to the field of electronic component modeling and relates to a technique for establishing a superjunction MOSFET capacitor model. Background Technology

[0002] Superjunction MOSFETs (SMTs) replace the single-conductivity drift region of traditional VDMOS with alternating P / N pillars. Compared to traditional VDMOS, this introduces a lateral electric field into the drift region, transforming the triangular electric field into a rectangular one. This allows the drift region to be completely depleted at a relatively low blocking voltage, improving the trade-off between on-resistance and breakdown voltage and overcoming the limitations of silicon. This results in SMTs exhibiting low power loss and high switching speed, making them a promising new type of power device aligned with the "carbon neutrality" trend. They have broad application prospects and can be widely used in systems such as servo / telecommunications, charging piles, adapters, lighting, smart meters, and LCD TVs, replacing traditional MOSFET switches in SMPS topologies to achieve higher system efficiency and lower power consumption.

[0003] The unique drift region structure of superjunction MOSFETs results in a more complex drift region depletion process during switching, leading to a unique nonlinearity in parasitic capacitance as it changes with drain-source voltage. This parasitic capacitance determines the characteristics of superjunction MOSFETs as power switches. Since the switching process involves the charging and discharging of a capacitive network, the device's parasitic capacitance determines its operating state in a dynamic system. Furthermore, the high voltage and current present during switching transients introduce dynamic losses, meaning capacitance affects system efficiency. During switching, current flowing through related components generates significant spike interference and resonant noise, which may enter the power grid or affect the system's electromagnetic environment, reducing system reliability. Therefore, in SPICE simulation design of switching power supplies, the accuracy of the power transistor's capacitance model significantly impacts signal fluctuations, thus affecting the consideration of design margins for electrical parameters.

[0004] Currently, the SPICE models provided for conventional superjunction MOSFET products are all macro-models built from standard device models, characterized by relatively complete functionality, fast simulation speed, and relatively easy development. The macro-modeling of superjunction MOSFET parasitic capacitance typically employs methods similar to those for traditional MOSFET devices: directly fitting the capacitance function across the entire voltage range, which presents challenges in selecting the nonlinear function; using existing diode capacitance models does not conform to the unique capacitance characteristics of superjunction MOSFETs. Both of these modeling methods suffer from poor accuracy in semi-logarithmic coordinates and, as purely mathematical means, lack physical meaning and have poor scalability. To achieve more accurate prediction of the switching behavior of superjunction MOSFETs as power switches in a system, their capacitance SPICE models should incorporate more physical meaning, resulting in lower fitting difficulty and higher accuracy. Summary of the Invention

[0005] To address the aforementioned technical issues, this invention proposes a SPICE macro-modeling method for balancing the drain-source capacitance of a superjunction MOSFET. This method reduces the difficulty of fitting the model and achieves high-precision fitting of the drain-source capacitance model across the entire voltage range in semi-logarithmic coordinates, thereby improving the accuracy of SPICE simulations for superjunction MOSFET application circuits. The depletion process-based modeling gives the mathematical model of the capacitance physical meaning and scalability. The method can be widely applied to various charge-balanced conventional superjunction MOSFET products.

[0006] The technical solution adopted in this invention is: a method for establishing a SPICE macromodel of balanced superjunction MOSFET drain-source capacitance, comprising:

[0007] A method for establishing a SPICE macromodel of balanced superjunction MOSFET drain-source capacitance includes the following steps:

[0008] S1. Obtain data on the changes in input capacitance, output capacitance, and Miller capacitance of the balanced superjunction MOSFET with drain-source voltage using a capacitance tester;

[0009] S2. Based on the basic structure of the balanced superjunction MOSFET device and the depletion law of the drift region with the drain-source voltage, establish the equivalent circuit topology of the drain-source capacitance of the balanced superjunction MOSFET.

[0010] S3. Based on the test capacitance data, the structure and process parameters of the balanced superjunction MOSFET are extracted in reverse, the zero bias capacitance value is determined, and the optimal coefficient is fitted based on mathematical software. Thus, the equivalent circuit parameters of the SPICE macro model of the drain-source capacitance of the balanced superjunction MOSFET are determined.

[0011] S4. Based on the equivalent circuit parameters and equivalent circuit model, write the corresponding SPICE model to obtain the drain-source capacitance SPICE macro model module that can be directly called in the balanced superjunction MOSFET SPICE model.

[0012] As a preferred method, step S1 specifically involves: measuring the input capacitance C of the balanced superjunction MOSFET using a capacitance meter. iss Output capacitor C oss With Miller capacitance C rss The capacitance curve as a function of drain-source voltage; the gate-source capacitance C is obtained by subtracting the Miller capacitance from the input capacitance. GS Data showing the variation of drain-source voltage; the drain-source capacitance C is obtained by subtracting the Miller capacitance from the drain-source capacitance. DS Data that varies with drain-source voltage.

[0013] As a preferred embodiment, the equivalent circuit topology of the drain-source capacitor in step S2 includes: a basic superjunction MOSFET, a controlled current source, a fixed capacitor, first, second, third, and fourth voltage control sources, first and second diodes, first, second, third, and fourth resistors, and first, second, and third voltage sources, wherein: the two ends of the controlled current source are respectively connected to the drain and source of the superjunction MOSFET; the drain of the superjunction MOSFET is connected to the first end of the first resistor; the second end of the first resistor is connected to the positive terminal of the first voltage control source and the positive terminals of the first and second diodes. The first terminal of the capacitor; the negative terminals of the first and second diodes and the second terminal of the capacitor are respectively connected to the positive terminals of the first, second, and third voltage sources; the negative terminal of the first voltage control voltage source is connected to the negative terminals of the first, second, and third voltage sources and led out to ground; the source of the superjunction MOSFET is connected to the first terminal of the second resistor; the second terminal of the second resistor is connected to the negative terminals of the second, third, and fourth voltage control voltage sources and the second terminals of the third, fourth, and fifth resistors and led out to ground; the positive terminals of the second, third, and fourth voltage control voltage sources are respectively connected to the first terminals of the third, fourth, and fifth resistors.

[0014] As a preferred method, the process of determining the equivalent circuit parameters of the SPICE macromodel for the drain-source capacitance of the superjunction MOSFET in step S3 is as follows:

[0015] The process of determining the equivalent circuit parameters of the SPICE macromodel for the drain-source capacitance of the balanced superjunction MOSFET in step S3 is as follows:

[0016] S31, Miller capacitor C rss With drain-source voltage V DS The drain-source voltage corresponding to the inflection point where the curve abruptly changes from decreasing to increasing is extracted as the pinch-off voltage V. pin V pin The relationship between the pillar width W, pillar doping N, elementary charge q, and semiconductor dielectric constant ε is as follows:

[0017]

[0018] Take a low voltage V with an applied bias voltage close to 0 l The test data is as follows: the capacitance formed by electric field coupling can be ignored at this time. The length of the PN pillar is L, and the junction potential is V. j Given a voltage of 0.6V, a total parallel cell length of Z, and a drain-source capacitance Cds formed by the contact potential difference, the capacitance is:

[0019]

[0020] Take the high voltage V near 70% breakdown voltage h When the drift region is nearly completely depleted, the drain-source capacitance is:

[0021] Formula (3)

[0022] The total length Z of the parallel cells can be extracted based on formulas (1), (2), and (3):

[0023] Formula (4)

[0024] Based on the above formulas (1)(2)(3)(4), the aspect ratio L / W of the balanced superjunction pitch can be extracted as follows: Formula (5)

[0025] It can be deduced that the critical voltage V corresponding to the exchange change of the short and major axes of the depletion line is... pp for:

[0026] Formula (6)

[0027] S32. Based on the basic structural parameters of the balanced superjunction MOSFET extracted in S21, establish a zero-bias drain-source capacitance model of the balanced superjunction MOSFET based on the device structure, and extract the zero-bias PN junction capacitance parameters CJO1 and CJO2 as follows:

[0028] Formula (7)

[0029] Formula (8)

[0030] S33. Based on the basic structural parameters of the balanced superjunction MOSFET extracted in S31 and the zero-bias drain-source capacitance model of the balanced superjunction MOSFET extracted in S32, a drain-source capacitance model is established.

[0031] Based on the approximate relationship between the electric field distribution location and voltage at depletion, it can be deduced that when the drain-source voltage is less than the pinch-off voltage V... pin Let k1 be the undetermined function characterizing the relationship between coupling capacitance and drain-source voltage, and let C be the drain-source capacitance. ds1 for:

[0032] Formula (9)

[0033] When the drain-source voltage is greater than the pinch-off voltage V pin And less than the critical voltage V pp Let k2 be the undetermined function characterizing the relationship between coupling capacitance and drain-source voltage, and let C be the drain-source capacitance. ds2 for:

[0034] Formula (10)

[0035] When the drain-source voltage is greater than the critical voltage V pp Let k3 be the undetermined function characterizing the relationship between coupling capacitance and drain-source voltage, and let C be the drain-source capacitance. ds3 for:

[0036] Formula (11)

[0037] S34. Based on mathematical software, fit the capacitance expression obtained in S33 with the test results obtained in S1 to determine the undetermined functions k1, k2 and k3 that vary with drain-source voltage.

[0038] S35. Based on the zero-biased PN junction capacitance parameters obtained in S32, the formula for the change of drain-source capacitance with drain-source voltage obtained in S33, and the undetermined function obtained in S34, the equivalent circuit model parameters of the drain-source capacitance are determined.

[0039] The first controlled current source current G1 is controlled by the currents I1, I2, and I3 passing through the first, second, and third voltage sources, and the first terminal voltages V1, V2, and V3 of the second, third, and fourth voltage-controlled voltage sources, satisfying the following relationship:

[0040]

[0041] The first, second, third, fourth, and fifth resistors are resistors that increase the convergence of the SPICE simulation. The first and second resistors are in the megaohm range, and the third, fourth, and fifth resistors are in the kiloohm range.

[0042] The first, second, and third voltage sources are all zero volts, used to read the branch current in the SPICE model programming;

[0043] The first and second diodes characterize the barrier capacitances of a P-pillar-N substrate diode and a P-pillar-N pillar diode under zero bias, respectively; the first and second diodes use the LEVEL1 diode model; the zero-bias capacitance parameter of the first diode is obtained from S32. The zero-bias capacitance parameter of the second diode is obtained from S32. The remaining parameters of the first and second diodes are set to default values.

[0044] The first capacitor is a fixed capacitor with a capacitance of C1 = 1pF;

[0045] First voltage control voltage source Second voltage control voltage source Third voltage control voltage source Fourth voltage control voltage source:

[0046]

[0047]

[0048] .

[0049] The currents of the first and second diodes and the first capacitor, along with the voltages of the corresponding second, third, and fourth voltage control sources, serve as control factors, influencing the first controlled current source to equivalently constitute the components of the drain-source capacitor; the currents I1, I2, and I3 flowing through the first, second, and third voltage sources are respectively:

[0050]

[0051]

[0052]

[0053] Therefore, the CV characteristics of the parasitic drain-source capacitance of the superjunction MOSFET can be effectively simulated by using the IV characteristics of a single-port network connected in parallel with the drain-source terminal of the superjunction MOSFET.

[0054] S4. Based on the equivalent circuit parameters and equivalent circuit model, write the corresponding SPICE model to obtain the parasitic capacitance SPICE macro model module that can be directly called in the superjunction MOSFET SPICE model.

[0055] The parasitic capacitance model based on the depletion principle considers the bulk diode capacitance formed by the P-pillar-N substrate, the bulk diode capacitance formed by the P-pillar-N pillar, and the coupling capacitance introduced by the two-dimensional electric field at the top of the P-pillar and the bottom of the N-pillar as the main components of the drain-source capacitance. The diode capacitance is approximated by the variation of a standard diode with reverse bias voltage, and the coupling capacitance is considered as the product of an undetermined function and the parallel plate capacitance. The plate length of the parallel plate capacitance is taken as the approximate length of the depletion line, and the plate distance is taken as the distance between the depletion lines of the PN pillars. The undetermined function is determined by the fitting results of the test data and the mathematical model.

[0056] The proposed topology construction approach for the capacitor macro model can be applied to SPICE macro modeling of various parasitic capacitances of various devices.

[0057] The undetermined function used can be an exponential function, which conforms to the general law of semiconductor capacitance change with voltage, avoiding the difficulty of directly fitting the capacitance test results;

[0058] The physics-based capacitance equation naturally divides the capacitance variation with voltage into three segments. As a preferred approach, linear interpolation can be performed in the transition region of each segment to improve simulation convergence.

[0059] The method of extracting superjunction MOSFET structure and process parameters from capacitance data can be extended to other parasitic capacitance or DC model modeling.

[0060] The beneficial effects of this invention are as follows: The method of this invention achieves accurate modeling of the drain-source capacitance of a balanced superjunction MOSFET across the entire voltage range in a semi-logarithmic coordinate system. Compared to direct fitting, the method of this invention provides a physically based segmentation approach, reducing the difficulty of fitting while improving fitting accuracy, thereby improving the accuracy of SPICE simulation of superjunction MOSFET application circuits; the depletion process-based modeling method gives the mathematical model of the capacitance certain physical meaning and is scalable, and the method can be widely applied to conventional superjunction MOSFET products that are close to charge balance; the SPICE code of different products has a high degree of repetition and can be encapsulated into a directly callable parasitic capacitance module; a new macro-model topology for capacitance is proposed, in which the equivalent circuit parameters are easily obtained from test and fitting results, and can be applied to the modeling of parasitic capacitance SPICE macro-models for various devices. Attached Figure Description

[0061] Figure 1 This is shown as the main flowchart of the present invention;

[0062] Figures 2(a) and 2(b) show the main components of a conventional superjunction MOSFET structure and its drain-source capacitance. Figure 2(a) shows the drain-source capacitance before the depletion region is pinched off when the drain-source voltage is small, and Figure 2(b) shows the drain-source capacitance after the depletion region is pinched off when the drain-source voltage is large.

[0063] Figure 3 This diagram illustrates the geometric relationship between the depletion line and drain-source voltage in a conventional superjunction MOSFET; in the horizontal plane of the figure, W represents the half-cell width, and L represents the drift region length. d The width of the depletion region is given, and the curve in the vertical plane represents the longitudinal electric field distribution, 0.78W. d This is the distance at which a longitudinal electric field distribution exists;

[0064] Figure 4 The diagram shows a general topology model of the parasitic capacitance equivalent circuit provided by the present invention; where 1 and 2 represent the first and second terminals of the components, respectively.

[0065] Figure 5 The graph shown is a curve of the parasitic capacitance of a superjunction MOSFET device obtained by testing in an embodiment of the present invention.

[0066] Figures 6(a)-6(c) show the undetermined function k1(V) in a superjunction MOSFET model calculated from test results according to an embodiment of the present invention. DS k2(V) DS ), k3(V DS A comparison of the variation of drain-source voltage with the data (points) and the results of its fitting formula (solid line); where Figure 6(a) shows the undetermined function k1(V DSFigure 6(b) shows a comparison between the calculation results and the fitting formula for the undetermined function k2(V). DS Figure 6(c) shows a comparison between the calculation results and the fitting formula for the undetermined function k3(V). DS The calculation results are compared with the fitting formula.

[0067] Figure 7 This is a comparison chart showing the capacitance value (dashed line) of the SPICE model of the drain-source capacitance of the superjunction MOSFET established in this embodiment of the invention with the measured value (asterisk).

[0068] Figure 8 The content displayed is the SPICE model of the drain-source capacitance of a superjunction MOSFET as described in this embodiment of the invention. Detailed Implementation

[0069] To facilitate understanding of the technical content of this invention by those skilled in the art, the following description, in conjunction with the accompanying drawings, further illustrates the invention.

[0070] like Figure 1 As shown, a method for establishing a SPICE macromodel of balanced superjunction MOSFET drain-source capacitance includes the following steps:

[0071] Step 1: Obtain data on the input capacitance, output capacitance, and Miller capacitance of the balanced superjunction MOSFET as a function of drain-source voltage using a capacitance meter; the measured results are as follows: Figure 5 As shown.

[0072] Step 2, as follows Figures 2(a)-2(b) As shown, the drain-source capacitance of a superjunction MOSFET comprises three parts: the body diode capacitance formed by the P-pillar-N substrate, the body diode capacitance formed by the P-pillar-N substrate, and the coupling capacitance introduced by the two-dimensional electric field at the top of the P-pillar and the bottom of the N-pillar. Therefore, the general mathematical description of the drain-source capacitance is the sum of these three capacitances in parallel. The diode capacitance is approximated by the variation of a standard diode with reverse bias voltage, and the coupling capacitance is considered as the product of an undetermined function and the parallel plate capacitance. Thus, the following approach is adopted... Figure 4 A general-purpose drain-source capacitance equivalent circuit topology;

[0073] Step 3: Based on the test capacitance data, extract the structure and process parameters of the balanced superjunction MOSFET in reverse, determine the zero bias capacitance value, and fit the optimal coefficients based on mathematical software to determine the equivalent circuit parameters of the SPICE macromodel of the drain-source capacitance of the balanced superjunction MOSFET.

[0074] S31, Miller capacitor C rss With drain-source voltage V DS The drain-source voltage corresponding to the inflection point where the curve abruptly changes from decreasing to increasing is extracted as the pinch-off voltage V. pin V pinThe relationship between the pillar width W, pillar doping N, elementary charge q, and semiconductor dielectric constant ε is as follows:

[0075] Formula (1)

[0076] The applied bias voltage is V l When V = 0.1V, Vj = 0.6V, and ε = 1e-12F / cm, the drain-source capacitance formed by the contact potential difference is:

[0077]

[0078] Formula (2)

[0079] Take the high voltage V near the rated breakdown voltage h =600V, the drift region is almost completely depleted, and the drain-source capacitance is:

[0080] Formula (3)

[0081] The total length Z of the parallel arrangement of device cells can be extracted based on formulas (1), (2), and (3):

[0082] Formula (4)

[0083] Based on the above formulas (1)(2)(3)(4), the aspect ratio of the balanced superjunction pitch can be extracted as follows:

[0084] Formula (5)

[0085] It can be deduced that the critical voltage V corresponding to the exchange change of the short and major axes of the depletion line is... pp for:

[0086] Formula (6)

[0087]

[0088] S32. Based on the basic structural parameters of the balanced superjunction MOSFET extracted in S21, establish a zero-bias drain-source capacitance model of the balanced superjunction MOSFET based on the device structure, and extract the zero-bias PN junction capacitance parameters CJO1 and CJO2 as follows:

[0089]

[0090]

[0091] S33. Based on the basic structural parameters of the balanced superjunction MOSFET extracted in S31 and the zero-bias drain-source capacitance model of the balanced superjunction MOSFET extracted in S32, a drain-source capacitance model is established.

[0092] Based on the approximate relationship between the electric field distribution location and voltage at depletion, it can be deduced that when the drain-source voltage is less than the pinch-off voltage V... pin Let k1 be the undetermined function characterizing the relationship between coupling capacitance and drain-source voltage, and let C be the drain-source capacitance. ds1 It can be written as:

[0093] Formula (9)

[0094] When the drain-source voltage is greater than the pinch-off voltage V pin Less than the critical voltage V pp Let k2 be the undetermined function characterizing the relationship between coupling capacitance and drain-source voltage, and let C be the drain-source capacitance. ds2 for:

[0095] Formula (10)

[0096] When the drain-source voltage is greater than the critical voltage V pp Let k3 be the undetermined function characterizing the relationship between coupling capacitance and drain-source voltage, and let C be the drain-source capacitance. ds3 for:

[0097] Formula (11)

[0098] S34. Using mathematical software, fit the capacitance expression obtained in S33 with the test results obtained in S1 to determine the undetermined functions k1, k2, and k3 that vary with the drain-source voltage. Usually, fitting with the undetermined coefficient function is more consistent with the capacitance variation and has higher fitting accuracy.

[0099] Based on the test results and the mathematical expressions of formulas (9), (10), and (11), the variation patterns of the undetermined functions k1, k2, and k3 with the drain-source voltage are deduced in reverse, as shown in Figures 6(a), 6(b), and 6(c). Then, the functions k1, k2, and k3 are generated using the curve fitting function of Matlab, respectively:

[0100]

[0101] Formula (18)

[0102] Formula (19)

[0103] The calculation and fitting results of the undetermined functions k1, k2, and k3 are compared as follows: Figures 6(a)-6(c) As shown.

[0104] Based on the zero-bias PN junction capacitance parameters obtained in S32, the formula for the change of drain-source capacitance with drain-source voltage obtained in S33, and the undetermined function obtained in S34, the model parameters of the drain-source capacitance equivalent circuit are determined respectively.

[0105] The currents of the first and second diodes and the first capacitor, along with the voltages of the corresponding second, third, and fourth voltage control sources, serve as control factors, influencing the first controlled current source:

[0106]

[0107] The first and second resistors are set to 1MΩ, and the third, fourth, and fifth resistors are set to 1kΩ to improve the convergence of the SPICE simulation.

[0108] The first, second, and third voltage sources are all zero volts, used to read the branch current in the SPICE model programming;

[0109] The first and second diodes use the LEVEL1 diode model; the zero-bias capacitance parameter of the first diode is obtained from S32. The zero-bias capacitance parameter of the second diode is obtained from S32. Use the default values ​​for the remaining parameters;

[0110] The first capacitor is a fixed capacitor with a capacitance of C1 = 1pF;

[0111] First voltage control voltage source Second voltage control voltage source Third voltage control voltage source Fourth voltage control voltage source

[0112]

[0113]

[0114]

[0115] Therefore, the CV characteristics of the parasitic drain-source capacitance of a superjunction MOSFET can be effectively simulated by using the IV characteristics of a single-port network connected in parallel with the drain-source terminal of the superjunction MOSFET. The capacitance value of the conventional superjunction MOSFET drain-source capacitance SPICE model established in this embodiment of the invention is compared with the measured values, for example... Figure 7 As shown. By Figure 7 It is evident that this physics-based segmentation method can achieve accurate fitting within the semi-logarithmic coordinate range.

[0116] Step 4: Based on the equivalent circuit parameters and equivalent circuit model, write the corresponding SPICE model to obtain the parasitic capacitance SPICE macromodel module that can be directly called in the balanced superjunction MOSFET SPICE model. For example... Figure 8 As shown, when the modeled superjunction MOSFET product object changes, only the parameters that need to be called need to be adjusted.

[0117] In summary, this invention provides a method for establishing a SPICE macromodel of the drain-source capacitance of a superjunction MOSFET. Based on the depletion process that varies with drain-source voltage, it establishes a parasitic capacitance model and provides a physically based segmentation method. Compared to direct fitting, this physically based segmentation method reduces fitting difficulty while improving fitting accuracy, thereby enhancing the accuracy of SPICE simulations for superjunction MOSFET application circuits. The modeling method based on the depletion process gives the mathematical model of the capacitance a certain physical meaning and is scalable. The method can be widely applied to conventional superjunction MOSFET products that are close to charge balance. The SPICE codes of different products have a high degree of repetition, forming a mature parasitic capacitance module that can be directly called. A new capacitance macromodel topology is proposed, in which the equivalent circuit parameters are easily obtained from test and fitting results, and can be applied to the modeling of parasitic capacitance SPICE macromodels for various devices. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0118] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for establishing a SPICE macro model of balanced super-junction MOSFET drain-source capacitance, characterized in that Comprise the following steps: S1, obtain the data of the input capacitance, output capacitance and Miller capacitance of the balanced super-junction MOSFET with respect to the drain-source voltage by a capacitance tester respectively; S2, establish the equivalent circuit topology of the balanced super-junction MOSFET drain-source capacitance according to the basic structure of the balanced super-junction MOSFET and the depletion law of the drift region with respect to the drain-source voltage; S3, according to the test capacitance data, extract the balanced super-junction MOSFET structure and process parameters in reverse, determine the zero-bias capacitance value, and based on the mathematical software, divide the capacitance data into three sections according to the voltage size and fit the best coefficient respectively, thereby determining the SPICE macro model equivalent circuit parameters of the balanced super-junction MOSFET drain-source capacitance; S4, based on the equivalent circuit parameters and the equivalent circuit topology, write the corresponding SPICE model, and obtain the final drain-source capacitance SPICE macro model module which can be directly called in the balanced super-junction MOSFET SPICE model.

2. The method of claim 1, wherein the SPICE macro model of the balanced super junction MOSFET drain-source capacitance is established by: Step S1 is specifically: through the capacitance tester, the balance super-junction MOSFET input capacitance C iss , output capacitance C oss And Miller capacitance C rss The capacitance curve of the change of the voltage is measured; the gate-source capacitance C GS The data of the change of the voltage is obtained by subtracting the Miller capacitance from the input capacitance; the drain-source capacitance C ds The data of the change of the voltage is obtained by subtracting the Miller capacitance from the output capacitance.

3. The method of claim 1, wherein the SPICE macro model of the balanced super junction MOSFET drain-source capacitance is established by: The equivalent circuit topology of the drain-source capacitance in step S2 comprises: a basic super-junction MOSFET, a controlled current source, a fixed capacitance, first, second, third and fourth voltage control voltage sources, first and second diodes, first, second, third and fourth resistors, and first, second and third voltage sources, wherein: the two ends of the controlled current source are connected to the drain and source of the super-junction MOSFET respectively; the drain of the super-junction MOSFET is connected to the first end of the first resistor; the second end of the first resistor is connected to the positive electrode of the first voltage control voltage source, the positive electrodes of the first and second diodes, and the first end of the capacitance; the negative electrodes of the first and second diodes and the second end of the capacitance are respectively connected to the positive electrodes of the first, second and third voltage sources; the negative electrodes of the first, second and third voltage sources are connected to the negative electrode of the first voltage control voltage source and are led out to the ground; the source of the super-junction MOSFET is connected to the first end of the second resistor; the second end of the second resistor is connected to the negative electrodes of the second, third and fourth voltage control voltage sources and the second ends of the third, fourth and fifth resistors, and is led out to the ground; the positive electrodes of the second, third and fourth voltage control voltage sources are respectively connected to the first ends of the third, fourth and fifth resistors.

4. The method of claim 1, wherein the SPICE macro model of the balanced super junction MOSFET drain-source capacitance is established by: The process of determining the SPICE macro model equivalent circuit parameters of the balanced super-junction MOSFET drain-source capacitance in step S3 is specifically: S31, the Miller capacitance C rss The drain-source voltage V DS The inflection point of the curve from decreasing to increasing corresponds to the pinch-off voltage V pin , V pin The relationship with the column width W, column doping N, elementary charge q, and semiconductor dielectric constant ε is: ； Low voltage V l Test data is taken near 0 bias voltage, when the electric field coupling formed capacitance can be ignored, PN column length is L, junction potential V j 0.6V, the total length of the cell is Z, and the drain-source capacitance Cds formed by the contact potential difference is: ； ； Take the high voltage V near 70% breakdown voltage h , the drift region is approximately fully depleted, at which time the drain-source capacitance is: Equation (3) The total length Z of the cell can be extracted based on formulas (1), (2) and (3): Equation (4) The length-width ratio L / W of the balanced super-junction Pitch can be extracted based on the above formulas (1), (2), (3) and (4): Equation (5) It can be inferred that the depletion line short axis variation exchange changes the corresponding critical voltage V pp is: Equation (6) S32, based on the basic structure parameters of the balanced super-junction MOSFET extracted in S21, establish the balanced super-junction MOSFET zero-bias drain-source capacitance model based on the device structure, and extract the zero-bias PN junction capacitance parameters CJO1 and CJO2 respectively as: Equation (7) Equation (8) S33, based on the basic structure parameters of the balanced super-junction MOSFET extracted in S31 and the balanced super-junction MOSFET zero-bias drain-source capacitance model extracted in S32, establish the drain-source capacitance model; From the approximate relationship between the position of the electric field distribution and the voltage when the device is depleted, we can get that when the drain-source voltage is less than the pinch-off voltage V pin , let the undetermined function representing the relationship between the coupling capacitance and the drain-source voltage be k1, and the drain-source capacitance C ds1 is: Formula (9) When the drain-source voltage is greater than the pinch-off voltage V pin and less than the critical voltage V pp , let the undetermined function k2 representing the relationship between the coupling capacitance and the drain-source voltage be k2, and the drain-source capacitance C ds2 be: Equation (10) When the drain-source voltage is greater than the threshold voltage V pp , let the undetermined function representing the relationship between the coupling capacitance and the drain-source voltage be k3, and the drain-source capacitance C ds3 be: Equation (11) S34, fitting the capacitance expression obtained in S33 with the test results obtained in S1 based on mathematical software to determine the undetermined functions k1, k2 and k3 varying with drain-source voltage; S35, determining the drain-source capacitance equivalent circuit model parameters based on the zero-bias PN junction capacitance parameters obtained in S32, the formula of drain-source capacitance varying with drain-source voltage obtained in S33 and the undetermined functions obtained in S34; The first controlled current source current G1 is controlled by the currents I1, I2 and I3 passing through the first, second and third voltage sources and the first end voltages V1, V2 and V3 of the second, third and fourth voltage-controlled voltage sources, and satisfies the relationship: ； The first, second, third, fourth and fifth resistances are resistances for increasing the convergence of SPICE simulation, the first and second resistances are megohm level, and the third, fourth and fifth resistances are kilohm level; The first, second and third voltage sources are zero volts, which are used to realize the reading of branch current in the programming of SPICE model; The first and second diodes represent the barrier capacitance of the P-column-N-substrate diode and the P-column-N-column diode under zero bias voltage respectively; the first and second diodes use the LEVEL1 diode model; the zero-bias capacitance parameter of the first diode is obtained by S32 , the zero-bias capacitance parameter of the second diode is obtained by S32 ; the rest of the parameters of the first and second diodes are selected by default values; The first capacitance is a fixed capacitance with a capacitance value of C1=1pF; First voltage-controlled voltage source Second voltage-controlled voltage source Third voltage-controlled voltage source Fourth voltage-controlled voltage source 。

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