Low leakage cell circuit design method based on input vector analysis and stacking effect

Abstract

The present invention discloses a low-leakage cell circuit design method based on input vector analysis and stacking effect, belonging to the field of digital integrated circuit design. Analyze the leakage ratio of each port of the transistor; establish the relationship between the transistor size and leakage; select the maximum number of stacked transistors; establish the leakage model of the stacked cut-off transistors; establish the leakage model of the stacked transistors under different input vectors; according to various input vector situations of the target cell circuit during operation, conduct classification discussions; find and label the leakage paths in the cell circuit; find and label the leakage power consumption components in the cell circuit; find and label the common leakage paths in the cell circuit; find and label the key leakage paths in the cell circuit. Adjust the transistor size in the key leakage path; adjust the transistor position starting from input vector control; selectively increase the stacked transistors. Conduct simulation verification on the improved circuit, and after confirmation, the cell library can be built.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a low-leakage cell circuit design method based on input vector analysis and stacking effect. Background Art

[0002] The power consumption of a CMOS circuit consists of two parts: dynamic power consumption and static power consumption (leakage power consumption). Dynamic power consumption is generated when the transistor switches; when there is no switching activity, the leakage current flowing between the two power rails generates static power consumption, and these leakage currents are mainly composed of subthreshold current, gate leakage current, and reverse-biased PN junction current.

[0003] With the gradual increase of low-speed and always-on application scenarios represented by the Internet of Things, the static power consumption in these circuit systems accounts for a relatively high proportion of the total power consumption.

[0004] The effect that the leakage current decreases due to transistor stacking is called the stacking effect. Compared with a single cutoff transistor, the series superposition of two or more cutoff transistors significantly reduces the subthreshold leakage current. It is very important to select the stacking method in advanced processes, otherwise the effect of leakage suppression will be reduced or the performance of the circuit will be affected. The selection of the input vector of stacked transistors will also affect the magnitude of the leakage current.

[0005] Ultra-high threshold voltage (EHVT) devices significantly reduce the subthreshold current, thereby reducing the static power consumption. However, it becomes more difficult to further reduce the leakage current of the cell circuit composed of EHVT transistors through circuit design. In addition, various secondary leakages including gate leakage and reverse-biased PN junction leakage also need to be concerned in advanced processes. In high-threshold voltage transistors, due to the high doping concentration, band-to-band tunneling (BTBT) and gate-induced drain leakage (GIDL) can make the reverse-biased PN junction leakage current close to the level of subthreshold leakage.

[0006] Existing low-leakage cell circuit design methods usually only focus on subthreshold leakage and have poor universality for advanced processes. Some methods require multiple threshold library transistors, with high costs and complex design methods. There are also some methods that use special connections of the substrate, require special processes to avoid junction leakage, have high costs, and complex layout designs. Summary of the Invention

[0007] The purpose of the present invention is to provide a low-leakage cell circuit design method based on input vector analysis and stacking effect, so as to solve the technical problems that existing low-leakage cell circuit design methods usually only focus on subthreshold leakage and have poor universality for advanced processes. Some methods require multiple threshold library transistors, with high costs and complex design methods. There are also some methods that use special connections of the substrate, require special processes to avoid junction leakage, have high costs, and complex layout designs.

[0008] To solve the above technical problems, the specific technical solution of the present invention is as follows:

[0009] A low-leakage cell circuit design method based on input vector analysis and stacking effect, comprising the following steps:

[0010] Step 1: For the target circuit that needs leakage optimization, establish a leakage model for the transistors therein;

[0011] Step 1.1: Analysis of the leakage ratio of each port of the transistor; separately simulate the NMOS and PMOS transistors in the circuit to be optimized. When the NMOS input is at a low level and the PMOS input is at a high level in the cut-off state, simulate respectively to measure the leakage current of each port, that is, the leakage currents of the four ports of the transistor gate, source, drain, and substrate; at the same time, in order to consider the influence of port voltage changes on subthreshold leakage, gate leakage, and substrate leakage, fix the gate and substrate biases, and separately scan the source and drain voltages sequentially to detect the current changes of the four ports of the transistor gate, source, drain, and substrate, and draw curves for observation;

[0012] Using Kirchhoff's current law, calculate the subthreshold leakage. Denote the leakage of the NMOS source as subthreshold current I subn and denote the leakage of the PMOS source as subthreshold current I subp Let I bn represent the substrate leakage current of the NMOS, I bp represent the substrate leakage current of the PMOS, I gn represent the gate leakage of the NMOS, I gp represent the gate leakage of the PMOS; calculate the magnitudes and ratios of the gate and substrate leakage currents of the NMOS and PMOS at the operating voltage of this circuit, and use I subn and I subp as the unit current to represent, and measure their ratio I subn / I subp ;

[0013] Step 1.2: Establish the relationship between size and leakage; measure the corresponding leakage current values of each port by separately scanning the transistor width W and transistor length L in the target circuit;

[0014] Step 1.3: Select the maximum number of stacked transistors; use the transistors of the target circuit to construct an inverter, increase the stacked NMOS and PMOS transistors. When the number of stacked transistors increases to n and the leakage current suppression effect does not meet the expected requirements, then adopt the scheme of stacking n - 1 transistors;

[0015] Step 1.4: Establish a leakage model for the stacked cutoff transistors; test the leakage of each port when stacking from n - 1 to 2 transistors; use the transistors in Step 1.1 to calculate the total NMOS leakage current I of stacking n - 1 transistors N(n-1) and I subn 、I bn 、I gn ; calculate the numerical relationship of I P(n-1) and I subp 、I bp 、I gp when stacking n - 1 transistors; calculate until n = 2 ends; the result of n = 1 has been obtained in Step 1.1;

[0016] Step 1.5: Establish a leakage model for the stacked transistors under different input vectors; use the circuit simulation tool to control the gate input vectors of the series-connected NMOS and PMOS stacked structures according to the maximum stacking number determined in Step 1.3 for different permutations and combinations, measure the leakage of each port under these input vectors respectively, and express the total leakage current in terms of the leakage current of each port according to the calculation method in Step 1.4;

[0017] Step 2: Establish a leakage model for the target cell circuit;

[0018] Step 2.1: Discuss different input vector cases according to various input vector situations of the target cell circuit during operation; the occurrence probability of the i-th group of input vectors is denoted as P i , and Steps 2.2 to 2.9 need to be carried out for different input vector combinations;

[0019] Step 2.2: Find and label the leakage path LP in the cell circuit;

[0020] Step 2.3: Find and label the leakage power consumption component LPC in the cell circuit;

[0021] Step 2.4: Find and label the common leakage path PLP in the cell circuit;

[0022] Step 2.5: Find and label the critical leakage path CLP in the cell circuit;

[0023] Step 2.6: Adjust the transistor size in CLP according to the result of Step 1.2;

[0024] Step 2.7: Adjust the transistor position starting from the input vector control according to the result of Step 1.5;

[0025] Step 2.8: Selectively add stacked transistors on CLP according to the requirements of the stacking number according to the results of Steps 1.3 and 1.4;

[0026] Step 2.9: Perform simulation verification on the improved circuit. Let the percentage reduction in static power consumption under the i-th group of input vectors be X i ; Check whether the optimization method affects the results under other input vectors. If it does, it is necessary to start improving from Step 2.6 again until ∑P i ×X i reaches the maximum value, and the optimization is completed, where i represents the combination of the i-th group of input vectors;

[0027] Step 3.1: Use tools for layout design, extract parasitic parameters using tools, perform post-simulation using software to verify the optimization effect, and after confirmation, unit library building can be carried out.

[0028] Further, Step 2.2 specifically includes the following steps:

[0029] Define the leakage path LP: Without considering gate leakage and substrate leakage, all leakage current paths in the circuit from the power supply rail to the ground rail are marked with solid arrows.

[0030] Further, Step 2.3 specifically includes the following steps:

[0031] Define the leakage power consumption component LPC: The leakage path consists of transistors in various states. Among them, the transistors in the off state are regarded as high resistors. If there is a voltage difference at both ends, it is the component that generates leakage power consumption, denoted as LPC; the transistors in the on state are regarded as low resistors or wires, and the voltage difference at both ends is ignored, considering that the generated static power consumption is extremely small. LPC is framed by a solid rectangle; Considering the case where the proportion of secondary leakage is similar to subthreshold leakage, for substrate leakage, when the magnitude of the transistor substrate leakage is comparable to the drain current of the source, it is also LPC; for gate leakage, when the magnitude of the transistor gate leakage is comparable to the drain current of the source, it is also LPC.

[0032] Further, in Step 2.3, the voltages of each node are marked through the model results in Step 1 or by re-simulating the entire target circuit for analysis.

[0033] Further, Step 2.4 specifically includes the following steps:

[0034] Define the common leakage path PLP: For complex circuits with transistor drain cascades, there will be the same transistors passing through between multiple leakage paths, which is the common part of these leakage paths, marked with a dotted box, denoted as PLP; The LPC existing on the PLP is the key to the leakage source because these transistors will affect multiple leakage paths, thus dominating the static power consumption under this input vector.

[0035] Further, Step 2.5 specifically includes the following steps:

[0036] Define the critical leakage path CLP: those leakage paths in the circuit with the largest proportion of leakage current; this definition aims to find the leakage paths and transistors that dominate the leakage in the circuit, and ignore the LPs whose leakage current is more than 40% less than the maximum LP leakage current, so as to efficiently suppress the leakage current of the unit circuit specifically. It is necessary to calculate the leakage current of each leakage path in combination with the leakage model in step 1.5 and make comparisons.

[0037] Further, step 2.6 specifically includes the following steps:

[0038] Minimize the transistor width W or increase the transistor length L as much as possible within the process tolerance, taking into account the performance requirements, and mainly adjust the transistor sizes on the CLP.

[0039] Further, in step 2.8, if the substrate leakage is comparable to the subthreshold leakage and the complexity of the layout design is acceptable, directly connect the transistor substrate to the source to reduce the substrate leakage.

[0040] The low-leakage unit circuit design method based on input vector analysis and stacking effect of the present invention has the following advantages:

[0041] 1. The present invention proposes a low-leakage unit circuit design method based on input vector analysis and stacking effect, which combines the advantages of stacking effect and input vector control, and can further suppress the leakage power consumption of the unit circuit operating near the subthreshold of EHVT. Based on this, low-power digital circuit design can be realized.

[0042] 2. Using the analysis method in step 2, the design method proposed by the present invention can be used to analyze the sources and distributions of leakage current under various input vectors of the unit circuit, and more accurately determine the transistors that mainly generate leakage current.

[0043] 3. Based on the work in step 1, the present invention comprehensively considers various leakage mechanisms, and the leakage current modeling results are closer to the actual situation, with a wider applicable range, and can be applied to advanced processes.

[0044] 4. Starting from the perspective of circuit design, the present invention can perform leakage analysis and optimization on customized unit circuits, and does not require special process technologies to reduce leakage current, with relatively low costs. Description of the Drawings

[0045] Figure 1 is a schematic flow chart of the low-leakage unit circuit design method based on input vector analysis and stacking effect proposed by the present invention;

[0046] Figure 2 is the circuit diagram of the original low-leakage latch-type low storage unit;

[0047] Figure 3It is the analysis of the original low-leakage latch-type low-memory cell circuit under four different input vectors. Figure 3 (a) is the leakage path analysis when D = 0 and N1 = 1. Figure 3 (b) is the leakage path analysis when D = 0 and N1 = 0. Figure 3 (c) is the leakage path analysis when D = 1 and N1 = 0. Figure 3 (d) is the leakage path analysis when D = 1 and N1 = 1.

[0048] Figure 4 It is the circuit diagram of the low-leakage latch-type memory cell improved by the method of the present invention.

[0049] Figure 5 It is the comparison diagram of the pre-simulation results of the low-leakage memory cell before and after improvement by the method of the present invention.

[0050] Figure 6 It is the layout of the low-leakage memory cell improved by the method of the present invention. Detailed implementation mode

[0051] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail a low-leakage cell circuit design method based on input vector analysis and stacking effect of the present invention with reference to the accompanying drawings.

[0052] Example 1: Taking a latch-type memory cell using a CMOS 28-nanometer extreme-high voltage threshold (EHVT) process with a power supply voltage of 0.5V as an example, the circuit is an existing patented structure, and the steps of the method are described in detail as follows:

[0053] As Figure 2 shown, the memory array is composed of a tri-state Latch, which is composed of a write driver circuit, a latch circuit and a read driver circuit, and altogether includes 14 transistors, 7 PMOS transistors and 7 NMOS transistors, and altogether has 8 ports, namely data input port D, high-level write enable port W, low-level write enable port WB, high-level read enable port R, low-level read enable port RB and data output port Q. The entire tri-state Latch is composed of three tri-state gates and an inverter, and all transistors use EHVT transistors to reduce leakage. The dimensions of each transistor of the tri-state Latch are as follows: the width-to-length ratio of M0, M1, M2, M3, M6, M7, M8, M9, M10, M11 is 110nm / 40nm; the width-to-length ratio of M4, M5 is 200nm / 40nm.

[0054] According to the method of the present invention in the attached Figure 1 drawings, start to optimize its low leakage:

[0055] 1.1: Analyze the leakage current ratio of each port of the circuit transistors. Individually simulate the NMOS and PMOS transistors in the circuit that needs to be optimized. The NMOS has a width-to-length ratio of 200nm / 40nm, and the PMOS has a width-to-length ratio of 200nm / 40nm. Simulate at a working voltage of 0.5V and measure the leakage current of each port separately. Through simulation, it can be found that when the EHVT transistor is cutoff under this process, the gate leakage can be ignored, and the substrate leakage increases as the difference between the substrate voltage and the source-drain voltage increases, which is particularly significant in PMOS, and the substrate leakage accounts for a relatively large proportion. The following basic relationship can be obtained: I bn = 0.22I subn 、I bp = 2.44I subp 、I subn = 5.9I subp . It can be seen that in this case, the leakage current of PMOS is mainly substrate leakage, and the subthreshold equivalent resistance is large. The total leakage current is lower than that of NMOS, while the leakage current of NMOS is mainly subthreshold leakage.

[0056] 1.2: Establish the relationship between size and leakage. As the transistor length L increases, the leakage current will decrease. At L = 40nm under the process adopted by the original circuit, the leakage is already very low, and the benefit of further increasing the transistor length is very small. By scanning the size parameter W of the transistors in the target circuit and measuring the corresponding leakage current values of each port, the width of the smallest unit in this standard library is 110nm for PMOS and 100nm for NMOS. As W increases, the substrate leakage increases slightly, and the subthreshold leakage increases significantly. The change in gate leakage can be ignored and is still very small. By looking up the scanning results of the width and corresponding leakage current of NMOS and PMOS transistors, it can be obtained that the leakage of a transistor with a width-to-length ratio of 100nm / 40nm is 0.85 times that of 200nm / 40nm. The cases of widths of 110nm and 100nm are similar, and the leakage model can be approximately used.

[0057] 1.3: Select the maximum number of stacked transistors. Use the transistors of the target circuit to construct an inverter, and increase the stacked NMOS and PMOS transistors. When the number of stacked transistors increases to 3, when the input is high level, the total leakage current even increases by about 13%, which is mainly due to the increase in gate leakage in the conducting pull-down network as the number of stacks increases; when the input is low level, the total leakage current only decreases by 2%. At this time, the proportion of the subthreshold current itself is not large, so the suppression effect is very unsatisfactory. Use a maximum of 2 transistors stacked.

[0058] 1.4: Establish a leakage model for stacked cut-off transistors. Test the leakage of each port when two transistors in 1.1 are stacked at the same operating voltage of 0.5V. Calculate the total leakage current I of stacking two NMOS with a width-to-length ratio of 200nm / 40nm. N(2) and I subn ,I bn ,I gn The numerical relationship of 2 stacked PMOS with a width-to-length ratio of 200nm / 40nm is used to calculate the total leakage current I P(2) and I subp ,I bp ,I gp The numerical relationship of . After approximate calculation of the simulation results, it can be concluded that: I N(2) =0.2I subn +I bn , I P(2) =0.2I subp +I bp .

[0059] 1.5: Establish a leakage model for stacked transistors under different input vectors. Using circuit simulation tools, according to the maximum stacking number 2 determined in 1.3, measure the leakage of each port of stacked NMOS and PMOS of the same size and operating voltage when the input vector is "10" and "01", and use the calculation method in 1.4 to represent the total leakage current with the leakage current of each port. The smaller gate leakage is attributed to the subthreshold leakage of the previous stage or the current stage circuit, and is expressed as I subn ,I subp Combining the results in 1.1 and 1.4, the leakage model is summarized as shown in Table 1. The magnitude of the leakage current is represented by I subn ,I subp It can be seen that the leakage of "01" is less than "10" at this time, that is, the leakage current is smaller when the transistor close to the power supply or ground is turned on, which is especially reflected in PMOS.

[0060] Table 1 Summary of stacked transistor leakage models under different input vectors

[0061]

[0062] 2.1: Classify and discuss the various input vectors of the target unit circuit during operation. For the static situation (W=0, R=0), the unit circuit has four different input vectors (0 represents a low level and 1 represents a high level), namely D=0, N1=0 (that is, the input data is 0, and the data stored in the N1 node is 0); D=0, N1=1; D=1, N1=0; D=1, N1=1. In the actual operation of this circuit, the probability P of these four different input vectors appearing is approximately the same. The following steps must be performed for these four different input vector combinations.

[0063] 2.2: Locate the leakage path LP in this unit circuit and mark it.

[0064] 2.3: Locate the leakage power consumption component LPC in this unit circuit and mark it.

[0065] 2.4: Locate the common leakage path PLP in this unit circuit and mark it.

[0066] 2.5: Locate the critical leakage path CLP in this unit circuit and mark it.

[0067] 2.6: According to the results of 1.2, adjust the transistor size in CLP.

[0068] 2.7: According to the results of 1.5, adjust the transistor position starting from the input vector control.

[0069] 2.8: According to the results of 1.3 and 1.4, selectively increase the stacked transistors in CLP.

[0070] The detailed processes of 2.2 to 2.8 are described as follows:

[0071] For input vector combination one, when D = 0 and N1 = 1, the leakage path and leakage power consumption component of the target circuit are as Figure 3 (a) shown. By marking the voltages of each node, it can be analyzed that LP = 4, LPC = 6, and LPC in PLP = 0. It should be emphasized that the voltages at both ends of M2 are equal and in a high-impedance state, and there will be no obvious current flowing through M2 at this time, so there is no leakage path passing through M2. It is particularly pointed out that the transistor M9 is in the upper transistor state of the "10" stack. Although it is cut off, the voltage difference between its two ends is not very large. Therefore, it can be not recorded in LPC, and only the lower M7 needs to be recorded. Mark each leakage path with a circled digital serial number, and analyze the leakage current magnitude of each path respectively. Path ①: Composed of M6, M8, M3, and M1, there is a "00" stack of NMOS (W = 110nm). Combining Table 1, the leakage current of this path can be estimated as: I1 = 0.85(0.2I subn +I bn ), approximately equal to 0.36I subn . Path ②: Composed of M4 and M5, LPC is a cut-off PMOS (W = 200nm), and it can be estimated that I2 = I subp +I bp , approximately equal to 3.4I subp . Using the relationship between I subp and I subn , it can be obtained that it is approximately equal to 0.58I subn。Path ③: Composed of M6, M8, M9, and M7, there is a "10" stack of NMOS (W = 110nm), I3 = 0.85(0.9I subn +2.7I bn ), approximately equal to 1.3I subn 。Path ④: Composed of M10, M12, M13, and M11, where two PMOS are cutoff and one NMOS is cutoff, it can be predicted that I4 < 0.85(I subp +I bp ), because the property of PMOS in this target circuit is that the resistance is much larger than that of NMOS when cutoff. Thus, it can be concluded that: under this input vector, ③ is the critical leakage path. It can be considered to swap the positions of M7 and M9 to form a 01 stack, and add a stacked transistor to M7. In addition, the width of M4 in ② can also be halved and then stacked. However, the static power consumption benefit of stacking other transistors such as M13 is almost negligible, and it will only increase unnecessary area and performance overhead.

[0072] Input vector combination two, when D = 0 and N1 = 0, the leakage paths and leakage power consumption components of the target circuit are as shown in Figure 3 (b). By labeling the node voltages, it can be analyzed that LP = 4, LPC = 6, and LPC = 0 in PLP. Analyze the leakage current magnitudes of each path respectively. Path ①: Composed of M0, M2, M9, and M7, there is a "01" stack of PMOS (W = 110nm), I1 = 0.85(1.4I subn +I bn ), approximately equal to 3.3I subp 。Path ②: Composed of M4 and M5, LPC is a cutoff NMOS (W = 200nm), so I2 = I subn +I bn , approximately equal to 1.2I subn 。Path ③: Composed of M6, M8, M9, and M7, there is a "10" stack of PMOS (W = 110nm), I3 = 0.85(0.8I subp +2.3I bp ), approximately equal to 5.5I subp 。Path ④: Composed of M10, M12, M13, and M11, where two NMOS are cutoff and one PMOS is cutoff, it can be predicted that I4 < I subp +I bpTherefore, it can be concluded that under this input vector, ② and ③ are the critical leakage paths. It can be considered to swap the positions of M8 and M6 to form a "01" stack, and halve the transistor width of M5 while increasing its stack. Combining with the changes when D = 0 and N1 = 1, it is actually to stack the inverter composed of M4 and M5 and halve the transistor width. Note that the changes in input vector combination one will not have much impact on the circuit leakage of input vector combination two.

[0073] For input vector combination three, when D = 1 and N1 = 0, the leakage paths and leakage power consumption components of the target circuit are as Figure 3 (c) shown. By labeling the node voltages, it can be analyzed that LP = 4, LPC = 7, and LPC = 0 in PLP. Analyze the leakage current magnitudes of each path respectively. Path ①: Composed of M0, M2, M9, and M7, there is a "11" stack of PMOS (W = 110nm), I1 = 0.85(0.2I subn +I bn ), approximately equal to 2.2I subp . The situations of paths ②, ③, and ④ are the same as the leakage currents of the corresponding paths in input vector combination two. Therefore, it can be concluded that under this input vector, ② and ③ are the critical leakage paths, and the changes for input vector combination two are also applicable. Note that the changes in input vector combination one will not have much impact on the circuit leakage of input vector combination three.

[0074] For input vector combination four, when D = 1 and N1 = 1, the leakage paths and leakage power consumption components of the target circuit are as Figure 3 (d) shown. By labeling the node voltages, it can be analyzed that LP = 4, LPC = 6, and LPC = 0 in PLP. Path ①: Composed of M6, M8, M3, and M1, there is a "01" stack of NMOS (W = 110nm). Combining with Table 4-1, it is not difficult to estimate that the leakage current of this path is: I1 = 0.85(1.1I subn +I bn ), approximately equal to 1.1I subn . The situations of paths ②, ③, and ④ are the same as the leakage currents of the corresponding paths in input vector combination one. Therefore, it can be concluded that ① and ③ are the critical leakage paths, and the changes in input vector combination one are also applicable. M3 can be further stacked, and this change will not affect the previous situations. Note that the changes in input vector combinations two and three will not have much impact on input vector combination four.

[0075] The improved low-leakage latch-type memory cell circuit structure is as Figure 4As shown. Among them, the sizes of the newly added stacked transistors M31 and M91 are W = 110 nm and L = 40 nm. The sizes of transistors M4, M41, M5, and M51 are W = 110 nm and L = 40 nm. The write signal "W" is adjusted from the gate of M8 to the gate of M6, and the write-not signal "WB" is adjusted from the gate of M9 to the gate of M7.

[0076] 2.9: Perform simulation verification on the improved circuit, and the results are as Figure 5 shown. First, test the static power consumption of the circuit. When D = 0 and N1 = 0, the static power consumption is reduced by 40.01%; when D = 0 and N1 = 1, the static power consumption is reduced by 38.68%; when D = 1 and N1 = 0, the static power consumption is reduced by 40.78%; when D = 1 and N1 = 1, the static power consumption is reduced by 49.01%. Since P1 = P2 = P3 = P4 = 25% during the operation of this circuit, the probability of each input vector appearing is the same. The average static power consumption has obtained a 42.39% benefit. Then, test the total power consumption of the unit circuit when it works at 8 kHz with three different data activities of 0%, 10%, and 100%. The total power consumption of the circuit has also been reduced to a certain extent.

[0077] 3: Use tools such as Virtuoso for layout design. The layout of the new unit circuit is as Figure 6 shown. Since only two transistors are added, the layout area only increases by 33%; use tools such as Synopsys StarRC to extract parasitic parameters, and use EDA software such as HSPICE for post-simulation to verify the optimization effect. The results are shown in Tables 2, 3, and 4. The improved unit circuit can still obtain a 26.87% benefit in static power consumption, and it has a certain reduction in the total power consumption at the circuit operating frequency, while having a small impact on the delay. After the function of the circuit is confirmed to be correct, the unit library can be built.

[0078] Table 2 Comparison of static power consumption of the latch-type storage cell before and after improvement (post-simulation, average value of 1000 Monte Carlo simulations)

[0079] Input vector Original circuit static power consumption (pW) Improved circuit static power consumption (pW) D = 0, N1 = 0 3.7336 2.7515 D = 0, N1 = 1 3.4593 2.5208 D = 1, N1 = 0 3.7904 2.7708 D = 1, N1 = 1 3.7934 2.7634 Average 3.6942 2.7016

[0080] Table 3 Comparison of total power consumption of the latch-type storage cell before and after improvement (post-simulation, average value of 1000 Monte Carlo simulations)

[0081] Data activity @ 8kHz Original circuit total power consumption (pW) Improved circuit total power consumption (pW) 0％ 5.0869 4.6310 10％ 6.0175 5.5122 100％ 9.5266 9.5202

[0082] Table 4 Comparison of delay of the latch-type storage cell before and after improvement (post-simulation, 1000 Monte Carlo simulations)

[0083]

[0084] It is understood that the present invention is described by means of some embodiments. Those skilled in the art will know that, without departing from the spirit and scope of the present invention, various changes or equivalent substitutions can be made to these features and embodiments. Additionally, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application belong to the scope protected by the present invention.

Claims

1. A low-leakage cell circuit design method based on input vector analysis and stacking effect, characterized in that Including the following steps: Step 1: For the target circuit that needs leakage optimization, establish a leakage model for the transistors therein; Step 1.1: Analysis of the leakage ratio of each port of the transistor; separately simulate the NMOS and PMOS transistors in the circuit that needs to be optimized. Simulate in the cut-off state where the NMOS input is low level and the PMOS input is high level, and measure the leakage current of each port respectively, that is, the leakage current of the four ports of the transistor gate, source, drain, and substrate; at the same time, in order to consider the influence of port voltage changes on subthreshold leakage, gate leakage, and substrate leakage, fix the gate and substrate biases, and separately scan the source and drain voltages sequentially to detect the current changes of the four ports of the transistor gate, source, drain, and substrate, and draw curves for observation; The leakage current of the NMOS source is denoted as the subthreshold current I subn , and the leakage current of the PMOS source is denoted as the subthreshold current I subp . Let I bn represent the substrate leakage current of the NMOS, and I bp represent the substrate leakage current of the PMOS. Let I gn represent the gate leakage current of the NMOS, and I gp represent the gate leakage current of the PMOS; calculate the magnitudes and ratios of the gate and substrate leakage currents of the NMOS and PMOS at the operating voltage of this circuit, and use I subn and I subp as the unit currents to represent them, and measure their ratio I subn / I subp . Step 1.2: Establish the relationship between size and leakage; measure the corresponding leakage current values of each port by separately scanning the transistor width W and transistor length L in the target circuit; Step 1.3: Select the maximum number of stacked transistors; construct an inverter using the transistors of the target circuit, and increase the stacked NMOS and PMOS transistors. When the number of stacked transistors increases to n and the leakage current suppression effect fails to meet the expected requirements, then adopt the scheme of stacking n - 1 transistors; Step 1.4: Establish a leakage model for the stacked cutoff transistors; test the leakage of each port when stacking from n-1 to 2 transistors; use the transistors in Step 1.1 to calculate the total NMOS leakage current I when stacking n-1 transistors N(n-1) and I subn 、I bn 、I gn 's numerical relationship, calculate the total PMOS leakage current I when stacking n-1 transistors P(n-1) and I subp 、I bp 、I gp 's numerical relationship; The calculation ends when n = 2; the result of n = 1 has been obtained in Step 1.1; Step 1.5: Establish a leakage model for the stacked transistors under different input vectors; use a circuit simulation tool to control the gate input vectors of the series-connected NMOS and PMOS stacked structures to perform different permutations and combinations according to the maximum stacking number determined in Step 1.3, measure the leakage of each port under these input vectors respectively, and express the total leakage current in terms of the leakage current of each port according to the calculation method in Step 1.4; Step 2: Establish a leakage model for the target cell circuit; Step 2.1: Discuss the cases of different input vectors respectively according to various input vector situations of the target unit circuit during operation; the occurrence probability of the i-th group of input vectors is denoted as P i , Steps 2.2 to 2.9 need to be carried out for different combinations of input vectors; Step 2.2: Find and label the leakage path LP in the cell circuit; Step 2.3: Find and label the leakage power consumption component LPC in the cell circuit; Step 2.4: Find and label the common leakage path PLP in the cell circuit; Step 2.5: Find and label the critical leakage path CLP in the cell circuit; Step 2.6: Adjust the transistor size in the CLP according to the result of Step 1.2; Step 2.7: Adjust the transistor position starting from the input vector control according to the result of Step 1.5; Step 2.8: Selectively add stacked transistors on the CLP according to the requirements of the stacking number according to the results of Steps 1.3 and 1.4; Step 2.9: Perform simulation verification on the improved circuit. Let the percentage reduction in static power consumption under the i-th group of input vectors be X i ; Check whether the optimization method affects the results under other input vectors. If it does, it is necessary to start improving from Step 2.6 again until the sum of P i ×X i is maximized, where i represents the combination of the i-th group of input vectors; Step 3.1: Use a tool for layout design, use a tool to extract parasitic parameters, perform post-simulation using software to verify the optimization effect, and after confirmation, the cell library can be built.

2. The low leakage unit circuit design method based on input vector analysis and stacking effect according to claim 1, characterized in that Step 2.2 specifically includes the following steps: Define the leakage path LP: Without considering gate leakage and substrate leakage, all leakage current paths from the power supply rail to the ground rail in the circuit are marked with solid arrows.

3. The low leakage unit circuit design method based on input vector analysis and stacking effect according to claim 2, characterized in that Step 2.3 specifically includes the following steps: Define the leakage power consumption element LPC: The leakage path consists of transistors in various states. Those in the off state are regarded as high resistance. If there is a voltage difference across both ends, it is the element that generates leakage power consumption, denoted as LPC. Those in the on state are regarded as low resistance or wires, and the voltage difference across both ends is negligible, considering the generated static power consumption to be extremely small. LPC is enclosed by a solid-line rectangular box. Considering the case where the proportion of secondary leakage is similar to subthreshold leakage, for substrate leakage, when the order of magnitude of the substrate leakage current of the transistor is comparable to the drain current of the source, it is also LPC. For gate leakage, when the order of magnitude of the gate leakage current of the transistor is comparable to the drain current of the source, it is also LPC.

4. The low leakage unit circuit design method based on input vector analysis and stacking effect according to claim 3, characterized in that In step 2.3, label the voltages of each node through the model results in step 1 or re-simulate the entire target circuit for analysis.

5. The low leakage unit circuit design method based on input vector analysis and stacking effect according to claim 3, characterized in that Step 2.4 specifically includes the following steps: Define the common leakage path PLP: For a complex circuit with transistor drain cascades, the same transistors will be passed through among multiple leakage paths, which is the common part of these leakage paths, marked with a dashed box and denoted as PLP. The LPCs existing on the PLP are the key to the leakage source because these transistors will affect multiple leakage paths, thus dominating the static power consumption under this input vector.

6. The low leakage unit circuit design method based on input vector analysis and stacking effect according to claim 5, characterized in that Step 2.5 specifically includes the following steps: Define the critical leakage path CLP: Those leakage paths in the circuit with the largest proportion of leakage current. This definition aims to find the leakage paths and transistors that dominate the leakage in the circuit and ignore the LPs with a leakage current less than 40% of the maximum LP leakage current, facilitating the targeted and efficient suppression of the leakage current of the unit circuit. It is necessary to calculate the leakage current of each leakage path in combination with the leakage model in step 1.5 and compare them.

7. The low-leakage cell circuit design method based on input vector analysis and stacking effect according to claim 6, characterized in that Step 2.6 specifically includes the following steps: As much as possible, reduce the transistor width W or increase the transistor length L within the allowable range of the process, taking into account the performance requirements, and mainly adjust the transistor dimensions on the CLP.

8. The low leakage cell circuit design method based on input vector analysis and stacking effect according to claim 7, characterized in that In step 2.8, if the substrate leakage is comparable to the subthreshold leakage and the complexity of the layout design is acceptable, directly connect the transistor substrate to the source to reduce the substrate leakage.

Images