A PCIe interface circuit verification device and method based on alternative link width

Abstract

The application discloses a PCIe interface circuit verification device and method based on alternative link width, and by adding a path conversion device between the PIPE interface between the controller and the PHY of the verification FPGA, the hardware verification of the multi-path PCIe interface circuit is efficiently and conveniently realized, the problems encountered in the hardware verification of the multi-path and multi-port PCIe interface circuit in the prior art are effectively solved, and the hardware verification method of the PCIe interface circuit based on the alternative link width provided by the application greatly reduces the working frequency of the controller and the application logic of the multi-path PCIe interface circuit in the verification FPGA with very small resources, and the verification of the PCIe interface circuit can be easily realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and particularly relates to a PCIe interface circuit verification device and method based on alternative link width. BACKGROUND

[0002] The PCIe bus is a third-generation high-performance IO bus after the first-generation EISA, ISA and VESA buses and the second-generation AGP, PCI and PCI-X buses, and is widely used in computer systems.

[0003] Hardware verification of an integrated circuit is carried out in a design and development stage of the circuit before a design is implemented in an FPGA, and is used to prove various design functions of the circuit to be correct, and is an important link in the circuit design process. The hardware verification plays an irreplaceable role in system adaptability and reliability verification of the circuit under various working strengths, and is an important guarantee for the quality of the circuit design.

[0004] The PCIe interface circuit can be divided into a single-port circuit and a multi-port circuit, and a single PCIe interface of the circuit can be an x1 single channel or x2, x4, x8, x12, x16 or x32 multi-channels. Figure 1 As shown in the figure, the PCIe interface is generally composed of an application layer, a controller and a physical layer (PHY), and two PCIe interfaces are interconnected and communicate through a link. The controller and the PHY are connected through a PCIe physical layer interface (Physical Interface for PCI Express, PIPE) industry standard interface.

[0005] Generally, the PCIe interface circuit, especially the multi-port and multi-lane link interface circuit, has complex functions, large logic scale and high working frequency. The clock working frequency of the PCIe interface logic is as high as 62.5 MHz or even 1000 MHz, so that most of the PCIe interface circuits encounter the problem that the FPGA implementable clock frequency is far lower than the PCIe interface design frequency during hardware verification, or a large number of PCIe interfaces cannot be implemented in the FPGA due to resource limitations. The PCIe interface has a standard bus rate specified by the protocol, and cannot be verified by the method of simultaneously linearly reducing the FPGA frequency and the interface frequency of the external connection test equipment as some control circuits. Patent CN 103164314B proposes a PCIe interface chip hardware verification method based on an asynchronous physical layer interface, which can perform hardware verification on PCIe interface circuits with a single lane link and other moderate scales. However, with the continuous evolution of the PCIe bus protocol version and the explosive market demand for multi-lane and multi-port PCIe interface circuits, this method can only reduce the FPGA verification frequency to 2 / 5 of the design frequency, and still cannot meet the hardware verification needs of most PCIe interface circuits. If the PCIe interface function of the circuit cannot be hardware verified, it will bring great hidden dangers to the correctness and reliability of the design, or the design optimization and FPGA timing optimization time of several months will be invested for verification, which will seriously affect the development progress of the circuit, and even miss the product launch opportunity. SUMMARY

[0006] The present application aims to overcome the shortcomings of the prior art and provide a PCIe interface circuit verification device and method based on alternative link width to solve the problem that the hardware verification of the PCIe interface circuit in the prior art cannot meet the hardware verification needs of the PCIe interface circuit.

[0007] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0008] A PCIe interface circuit verification method based on alternative link width, comprising:

[0009] identifying the signal type received from the FPGA PHY, and representing the signal type as a 7-type packet sequence through a data_type[2:0] signal; converting the packet sequence according to different states of the indication signal output, so that the format, information and bit width of the converted packet sequence meet the PCIe controller interface requirements of the to-be-verified PCIe controller, and sending the packet sequence to the PIPE interface of the to-be-verified PCIe controller;

[0010] The application receives data signals output by a PIPE interface of a PCIe controller to be verified, converts the signals according to different states of an indication signal, and sends the converted packet sequences, wherein the converted packet sequences indicate seven types of packet sequence formats, information and bit widths conforming to the PIPE interface type of the PHY of the FPGA; the seven types of packet sequences include physical layer packets (PLP), data link layer packets (DLLP) and transaction layer packets (TLP); the physical layer packets (PLP) include a link training ordered set TS1, a link training ordered set TS2, a clock compensation ordered set SKIP, a fast training ordered set FTS and an electrical idle sequence EIEOS.

[0011] The application converts control signals or state signals output by a PIPE interface of a PCIe controller to be verified, and converts the control signals or state signals into receiving signals conforming to the PIPE interface requirements of the PHY of the FPGA, or converts the control signals or state signals output by the PIPE interface of the PHY of the FPGA into input signals conforming to the PIPE interface of the PCIe controller to be verified.

[0012] The application further improves in that:

[0013] Preferably, the indication signal includes a link training state machine indication signal ltssm_state, a fast training ordered set indication signal FTS_flag and an electrical idle indication signal EIE_flag.

[0014] Preferably, the conversion of the seven types of packet sequences includes path duplication of the physical layer packets (PLP) and data conversion of the PLP, disassembly and rearrangement of the TLP, and disassembly and rearrangement of the DLLP; the data conversion of the PLP includes conversion of the lane number in the link training ordered set TS1 and conversion of the lane number in the link training ordered set TS2.

[0015] Preferably, the path duplication of the physical layer packets (PLP) is to duplicate the received PLP packets of the lane 0 of the PHY by NLc-1 copies when the PLP packets are sent to the lane 0 of the PCIe controller to be verified, and to send the duplicated PLP packets to the other NLc-1 lanes of the PCIe controller to be verified.

[0016] Preferably, when the indication signal ltssm_state indicates that the PCIe controller is in the lane number negotiation state in the link training state, the duplicated lane number in the link training ordered set TS1 is converted according to the actual lane number corresponding to the PIPE interface of the PCIe controller, and the duplicated lane number in the link training ordered set TS2 is converted according to the actual lane number corresponding to the PIPE interface of the PCIe controller.

[0017] When the indication signal ltssm_state indicates that the PCIe controller is in normal working state, and the data signal and the data indication signal of the PIPE interface of the PHY are TLP, the start character STP is placed in lane 0 of the PCIe controller, and the subsequent characters are arranged according to the byte stripping rule and the lane number of the PCIe controller in turn; when the data signal and the data indication signal of the PIPE interface of the PHY are DLLP, the start character SDP is placed in lane 0 of the PCIe controller, and the subsequent characters are arranged according to the byte stripping rule and the lane number of the PCIe controller in turn.

[0018] Preferably, when receiving the data signal output by the PIPE interface of the PCIe controller to be verified, and the packet sequence is TLP or DLLP, the received data signal is combined and rearranged and then sent to the PIPE interface of the FPGA PHY

[0019] When receiving the data signal output by the PIPE interface of the PCIe controller to be verified, and the packet sequence is link training ordered set TS1 or link training ordered set TS2, if the indication signal indicates that the PCIe controller is in the link number negotiation state in the link training state, the link number of the link training ordered set TS1 and the link training ordered set TS2 is changed from the PAD character to the actual link number of the PHY; if the indication signal indicates that the PCIe controller is in the lane number negotiation state in the link training state, the lane number in the link training ordered set TS1 and the link training ordered set TS2 is changed from the PAD character to the actual lane number of the PHY.

[0020] Preferably, when the PCIe controller to be verified sends the fast training ordered set FTS, each valid lane of the PHY constructs the fast training ordered set FTS and sends it to the PIPE interface of the PHY and sends it, and the number of the constructed FTS is specified by the state indication signal output by the PCIe controller to be verified;

[0021] When the PCIe controller to be verified sends the electrical idle ordered set EIEOS, each valid lane of the PHY constructs the electrical idle ordered set EIEOS and sends it to the PIPE interface of the PHY and sends it;

[0022] The SKIP ordered set is constructed on each valid lane of the PHY according to the interval time required by the PCIe protocol, and the SKIP ordered set is sent to the PIPE interface of the PHY and sent.

[0023] Preferably, when the PHY PIPE interface outputs a clock compensation ordered set SKIP, the received SKIP ordered set of lane 0 of the PHY is sent to lane 0 of the PCIe controller to be verified; meanwhile, the physical layer packet is duplicated, and the duplicated SKIP is sent to the other NLc-1 lanes of the PCIe controller to be verified.

[0024] When the lane conversion device detects that the PHY PIPE interface outputs a fast training ordered set FTS, the received FTS ordered set of lane 0 of the PHY is sent to lane 0 of the PCIe controller to be verified; meanwhile, the physical layer packet is duplicated, and the duplicated FTS is sent to the other NLc-1 lanes of the PCIe controller to be verified.

[0025] When the lane conversion device detects that the PHY PIPE interface outputs an electrical idle ordered set EIEOS, the received EIEOS ordered set of lane 0 of the PHY is sent to lane 0 of the PCIe controller to be verified; meanwhile, the physical layer packet is duplicated, and the duplicated EIEOS is sent to the other NLc-1 lanes of the PCIe controller to be verified.

[0026] A PCIe interface circuit verification device based on alternative link width, comprising:

[0027] A detection module identifies the type of signal received from the PHY of the FPGA, and indicates the type of signal as a 7-type packet sequence through a data_type[2:0] signal;

[0028] A receiving module is configured to convert the packet sequence according to different states of an indication signal, so that the format, information and bit width of the converted packet sequence meet the interface requirements of the PCIe controller to be verified, and the packet sequence is sent to the PIPE interface of the PCIe controller to be verified;

[0029] A sending module receives a data signal output by the PIPE interface of the PCIe controller to be verified, converts the signal according to different states of an indication signal, and sends the converted packet sequence, wherein the 7-type packet sequence indicated by the converted signal meets the PIPE interface type of the PHY of the FPGA, and the 7-type packet sequence includes a TLP, a DLLP, a link training ordered set TS1, a link training ordered set TS2, a clock compensation ordered set SKIP, a fast training ordered set FTS and an electrical idle sequence EIEOS.

[0030] The signal conversion module is used for converting the control signal or the state signal output by the PIPE interface of the PCIe controller of the to-be-verified circuit, and the converted control signal or state signal is a receiving signal meeting the requirements of the PIPE interface of the FPGA PHY, or the control signal or state signal output by the PIPE interface of the FPGA PHY is converted into an input signal meeting the PIPE interface of the to-be-verified PCIe controller.

[0031] Compared with the prior art, the present application has the following beneficial effects:

[0032] The application discloses a PCIe interface circuit verification device and method based on a substitute link width, and the device is characterized in that a path conversion device is added between the PIPE interface between the controller and the PHY of the verification FPGA, so that the hardware verification of the multi-path PCIe interface circuit is efficiently and conveniently realized, the problems encountered in the hardware verification of the multi-path and multi-port PCIe interface circuit in the prior art are effectively solved, and the following advantages are achieved: 1. the clock working frequency of the verification FPGA is reduced by a high proportion, the working frequency can be reduced to 1 / 2-1 / 32 of the original circuit design, and the synthesis and layout and wiring can be easily realized in the verification FPGA; 2. the added path conversion device does not need to use large-capacity receiving and sending caches, more available storage and logic resources are left for the design in the FPGA, and the performance requirement of the FPGA is reduced; 3. the link width of the PHY in the FPGA is reduced, more PCIe interfaces can be realized in the same FPGA, and the problem that the number of channels of the high-speed PHY limits the hardware verification of the multi-port PCIe interface circuit in the FPGA is solved; 4. the link width of the PCIe interface to be verified is irrelevant, a standard x1 link interface can be used for external connection, the performance requirement of the link opposite end device and the requirement of the link width diversity in the hardware verification system are reduced, the complexity of the verification system is simplified, and the versatility of the verification system is improved; 5. the added path conversion device has a simple structure and is easy to design. The PCIe interface circuit hardware verification method provided by the application greatly reduces the working frequency of the controller and the application logic of the multi-path PCIe interface circuit in the verification FPGA with very small resources, and the verification of the PCIe interface circuit can be easily realized. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A communication link schematic diagram of a prior art PCIe interface circuit composition and two PCIe circuit compositions;

[0034] Figure 2 A principle block diagram of a single PCIe port in a PCIe interface circuit ASIC according to an embodiment of the application;

[0035] Figure 3The schematic diagram of a PCIe interface circuit hardware verification platform of the embodiment of the present application;

[0036] Figure 4 The schematic diagram of a PCIe interface circuit hardware verification platform of the embodiment of the present application; DETAILED DESCRIPTION

[0037] The present application will be further described below in conjunction with the accompanying drawings:

[0038] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application; the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance; in addition, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] The present application provides a PCIe interface circuit hardware verification method based on alternative link width, which, on the basis of keeping the PCIe controller and the application layer logic design of the to-be-verified circuit unchanged, reduces the working frequency of the to-be-verified PCIe controller and the application layer in the verification FPGA by adding a path conversion device between the PIPE interface between the PCIe controller of the to-be-verified circuit and the PHY of the FPGA, reduces the link width of the PHY in the verification FPGA, reduces the frequency in the FPGA, and connects the PCIe interface of the to-be-verified circuit with the standard PCIe device of the external narrower link width after realizing the function of the to-be-verified circuit, and then performs hardware function verification.

[0040] The link width NLc of the PCIe controller of the circuit to be verified can be 2, 4, 8, 12, 16 or 32 and must be greater than the link width NLp of the PHY of the FPGA; the link width NLp can be 1, 2, 4, 8, 12 or 16 and must be less than the link width NLc; the relationship between the working frequency ff of the PCIe controller and the application layer to be verified in the verification FPGA and the original design working frequency fs of the controller and the application layer of the PCIe interface circuit to be verified in the circuit is ff / fs=NLp / NLc; in relation to the link width NLc of the PCIe interface of the circuit to be verified, the minimum frequency reduction ratio ff / fs of the PCIe controller and the application layer to be verified is 1 / 2 and the maximum is 1 / 32. In order to realize the above-mentioned reduction of the working frequency, the link width of the PHY in the verification FPGA is reduced, the frequency is reduced in the FPGA, and the path conversion device in the application is used to realize it.

[0041] Referring to Figure 3 The application increases the path conversion device between the PIPE interface between the PCIe controller of the circuit to be verified in the verification FPGA and the PHY of the FPGA. The path conversion device is composed of a receiving conversion device and a sending conversion device; wherein the receiving conversion device comprises a detection module, a receiving module and a bit width conversion module, and each module is described as follows:

[0042] The detection module and the PHY and the receiving module interact to identify the type of data received from the PHY of the FPGA. The identifiable data types include TLP, DLLP and PLP. The length of the TLP is a multiple of 4 bytes, the start character is STP, and the end character is END or EDB. The PLP includes a link training ordered set TS1, a link training ordered set TS2, a clock compensation ordered set SKIP, a fast training ordered set FTS and an electrical idle sequence EIEOS. The length of the DLLP is 8 bytes, the start character is SDP, and the end character is END. The link training ordered sets TS1 and TS2 are composed of 16 characters, and the start character of each is COM. Symbol 0 of TS1 is the start character COM, symbol 1 is a PAD character or a link number, symbol 2 is a PAD character or a path number, symbol 3 is the number of FTS, symbol 4 is the link rate, symbol 5 carries link control information including hot reset, link disable, loopback, out-of-order enable and rate change, and symbols 6 to 15 are training sequence identifiers (TS ID). TS2 is the same as TS1 except that the TS ID is different. The start character of the SKIP ordered set is COM, which is composed of COM and 3 SKP characters. The start character of the FTS ordered set is COM, which is composed of COM and 3 FTS characters. The detection module detects and identifies the above 7 different packet formats and sends them to the receiving module for further processing. The detection module indicates the type of data received by the x1 PHY through the data_type[2:0] signal, and the values 1-7 of data_type[2:0] correspond to TLP, DLLP, link training ordered set TS1, link training ordered set TS2, clock compensation ordered set SKIP, fast training ordered set FTS and electrical idle sequence EIEOS respectively.

[0043] The receiving module interacts with the detecting module, the bit width conversion module and the PCIe controller, and is used for receiving the packet sequence identified by the detecting module, converting the packet sequence according to different states indicated by a link training state machine indication signal ltssm_state output by the PCIe controller to be verified, so that the format, information and bit width of the packet sequence of the PIPE interface data of the PHY of the FPGA after conversion by the channel conversion device meet the requirements of the x4 PIPE interface of the PCIe controller to be verified, and then the data signal rxdata_x4 and the data indication signal rxdatak_x4 are used to send the packet sequence to the PIPE interface of the PCIe controller to be verified. The ltssm_state indicates 17 states of the link training state machine of the PCIe controller to be verified from 0x00 to 0x11. During the jump of the ltssm_state from the state 00 to the state 11, the link is in the link training state, and the PLP is exchanged on the link. When the ltssm_state is the state 11, the link is in the link fully open state, and can send and receive TLP, DLLP and PLP. The receiving module converts the data of the PLP, replicates the channel and converts the channel number of the link training ordered set TS1 and TS2 during the link training process; and in the normal working state of the link, the TLP and the DLLP are disassembled and rearranged and then sent to the PIPE interface of the PCIe controller to be verified.

[0044] The bit width conversion module interacts with the PCIe controller and the receiving module, and is used for data bit width conversion and channel replication of the PLP in the link training state. When the single-channel data bit width of the PIPE interface of the PHY of the FPGA and the single-channel bit width of the PIPE interface of the PCIe controller to be verified are inconsistent, the bit width conversion module converts the link training ordered set TS1, TS2, the clock compensation ordered set SKIP, the fast training ordered set FTS and the electrical idle ordered set EIEOS according to the ltssm_state indication signal output by the PCIe controller to be verified and the data_type indication signal of the current data type output by the detecting module, so that the single-channel data bit width of the PIPE interface of the PHY and the single-channel bit width of the PIPE interface of the PCIe controller to be verified are consistent, and the converted bit width data is replicated into three parts and sent to the PCIe controller to be verified.

[0045] The sending conversion device is composed of a sending module and a signal conversion module, and the two modules are described as follows:

[0046] The sending module interacts with the PCIe controller and the PHY module, and is configured to receive a signal output by a PIPE interface of a PCIe controller of the to-be-verified interface circuit, convert PIPE interface data signals output by the to-be-verified PCIe controller according to different states indicated by ltssm_state output by the to-be-verified PCIe controller, so that the converted data signals indicate a format, information and bit width of a packet sequence that meet a PIPE interface of the PHY of the FPGA, and send the received packet sequence into the PIPE interface of the x1 PHY of the FPGA.

[0047] The signal conversion module interacts with the PCIe controller and the PHY module, and is configured to perform bidirectional conversion of control signals and state signals of a PIPE interface between the PCIe controller of the to-be-verified circuit and the PHY of the FPGA, convert mac_phy_*_x4 signals output by the PIPE interface of the PCIe controller of the to-be-verified circuit into received signals mac_phy_*_x1 that meet requirements of the PIPE interface of the PHY of the FPGA, and convert phy_mac_*_x4 signals output by the PIPE interface of the PHY into phy_mac_*_x1 input signals that meet the PIPE interface of the to-be-verified PCIe controller.

[0048] The above-mentioned path conversion device performs bidirectional conversion of control signals, state signals and data signals of a PIPE interface between the PCIe controller of the to-be-verified circuit and the PHY of the FPGA based on a PIPE interface protocol, so that the to-be-verified PCIe controller and an application layer can be connected to external PCIe devices of a standard and narrower link width through the path conversion device and the PHY after frequency reduction. The path conversion device can be asynchronous or synchronous.

[0049] The path conversion device further receives three state indication signals from the PCIe controller for conversion, and the three state indication signals specifically include a link training state machine indication signal ltssm_state, a fast training ordered set indication signal FTS_flag and an electrical idle indication signal EIE_flag.

[0050] The specific implementation method of the receiving conversion device includes the following steps.

[0051] The receiving and converting function of the channel converting device realizes signal conversion between the PIPE interface output of the PHY and the PIPE interface input of the PCIe controller to be verified, mainly including channel replication and data conversion of the physical layer packet (PLP), disassembly and rearrangement of TLP and DLLP, and conversion of channel numbers in training sequence sets TS1 and TS2.

[0052] The channel replication of the physical layer packet refers to replicating the PLP packet of channel 0 of the received PHY by NLc-1 copies and sending the replicated packets into other NLc-1 channels of the PCIe controller to be verified when the PLP packet is sent to channel 0 of the PCIe controller to be verified.

[0053] Further, when the single-channel data bit width of the PIPE interface of the PHY and the single-channel data bit width of the PIPE interface of the PCIe controller to be verified are inconsistent, the channel converting device needs to further convert the channel data and the data indication signal bit width between the two PIPE interfaces when performing the channel replication of the physical layer packet.

[0054] In the link training process, each channel of the link transmits complete training sequence sets TS1 and TS2, and when the data on the received channel of the PHY is the training sequence sets TS1 and TS2, the TS1 and TS2 sequence sets of channel 0 of the received PHY are sent to channel 0 of the PCIe controller to be verified; at the same time, the physical layer packet is replicated, and the replicated TS1 and TS2 are sent into other NLc-1 channels of the PCIe controller to be verified.

[0055] When the PCIe link training state machine indication signal ltssm_state indicates that the current state is the channel number negotiation state, the channel number indicated by symbol 2 in the replicated TS1 and TS2 sequence sets needs to be converted according to the actual channel number corresponding to the PIPE interface of the PCIe controller to be verified during the channel replication of the physical layer packet, so as to match the corresponding channel number of the PCIe interface controller to be verified.

[0056] When the PCIe link training state machine indication signal ltssm_state indicates that the current state is a normal working state of the link, the TLP and DLLP are transmitted on the link. When the path conversion device detects that the PIPE interface data signal and the data indication signal of the PHY are TLP, the start character STP is placed in path 0 of the controller, and the subsequent characters are arranged according to the byte stripping rule and the path number of the controller in turn; when it is detected that the data signal and the data indication signal of the PIPE interface of the PHY are DLLP, the start character SDP is placed in path 0 of the PCIe controller, and the subsequent characters are arranged according to the byte stripping rule and the path number of the PCIe controller in turn.

[0057] In any state, when the path conversion device detects that the PIPE interface output clock compensation ordered set SKIP of the PHY, the received SKIP ordered set of path 0 of the PHY is sent to path 0 of the PCIe controller to be verified; at the same time, the physical layer packet is copied, and the copied SKIP is sent to the other NLc-1 paths of the PCIe controller to be verified.

[0058] When the path conversion device detects that the PIPE interface output fast training ordered set FTS of the PHY, the received FTS ordered set of path 0 of the PHY is sent to path 0 of the PCIe controller to be verified; at the same time, the physical layer packet is copied, and the copied FTS is sent to the other NLc-1 paths of the PCIe controller to be verified.

[0059] When the path conversion device detects that the PIPE interface output electrical idle ordered set EIEOS of the PHY, the received EIEOS ordered set of path 0 of the PHY is sent to path 0 of the PCIe controller to be verified; at the same time, the physical layer packet is copied, and the copied EIEOS is sent to the other NLc-1 paths of the PCIe controller to be verified.

[0060] The method for implementing the sending conversion device includes the following steps:

[0061] The sending conversion function of the path conversion device realizes the signal conversion between the PIPE interface output of the PCIe controller to be verified and the PIPE interface input of the PHY. In the sending process, the corresponding physical layer packet is constructed according to the state indication signal output by the PCIe controller to be verified, to replace the PIPE interface data and data indication signal of the PCIe controller to be verified and is sent into the PIPE interface of the PHY; for the data link layer packet DLLP and the transaction layer packet TLP, the path conversion device receives the data combination of the PIPE interface of the PCIe controller and rearranges and sends it into the PIPE interface of the PHY for sending.

[0062] In the link training process, each lane of the link sends complete link training ordered sets TS1 and TS2, when the PCIe link training state machine indication signal ltssm_state indicates that the current state is the POLLING state for sending link training ordered sets TS1 and TS2, the lane conversion device constructs the link training ordered sets TS1 and TS2 conforming to the PIPE interface link width of the PHY and sends them into the PIPE interface of the PHY. When the PCIe link training state machine indication signal ltssm_state indicates that the current state is the link number negotiation state, the lane conversion device changes the link number in the current and subsequently constructed TS1 and TS2 ordered sets from a PAD character to the actual link number of the PHY; when the PCIe link training state machine indication signal ltssm_state indicates that the current state is the lane number negotiation state, the lane conversion device changes the lane number in the current and subsequently constructed TS1 and TS2 ordered sets from a PAD character to the actual lane number of the PHY.

[0063] After the completion of the link training, the link performs various transaction function verifications according to the functions of the PCIe interface circuit to be verified, at this time, the link mainly transmits TLPs and DLLPs. When transmitting TLPs or DLLPs, the start character STP or SDP of the TLP or DLLP output by the PCIe controller to be verified is placed on lane 0 of the PHY, and the remaining characters in the TLP or DLLP are arranged in sequence according to the actual lane number of the PHY, and are sent into the PIPE interface of the PHY according to the byte stripping rule for transmission.

[0064] When the PCIe fast training ordered set indication signal FTS_flag indicates that the PCIe controller to be verified sends a fast training ordered set FTS, the lane conversion device constructs a fast training ordered set FTS for each valid lane of the PHY and sends it into the PIPE interface of the PHY for transmission, and the number of the constructed FTS sequences is specified by the state indication signal output by the PCIe controller to be verified.

[0065] When the PCIe electrical idle ordered set indication signal EIE_flag indicates that the PCIe controller to be verified sends an electrical idle ordered set EIEOS, the lane conversion device constructs an electrical idle ordered set EIEOS for each valid lane of the PHY and sends it into the PIPE interface of the PHY for transmission.

[0066] In any state, the lane conversion device constructs a SKIP ordered set on each valid lane of the PHY at an interval time required by the PCIe protocol and sends it into the PIPE interface of the PHY for transmission.

[0067] Embodiment

[0068] The embodiment discloses a 3-port PCIe 2.0 interface circuit based on a 12-channel and 4-link-width. Figure 2 The principle block diagram of a single PCIe port in an ASIC (Application Specific Integrated Circuit) of the PCIe 2.0 interface circuit is shown in FIG. 1. Figure 2 As shown in FIG. 1, the link width of the PHY and the PCIe controller of the ASIC is x4, and the PHY and the PCIe controller in the ASIC are connected through an x4 PIPE interface.

[0069] The embodiment increases a channel conversion device between the three x4 PCIe controllers of the to-be-verified circuit in the verification FPGA and the PIPE interface between the three PHYs of the verification FPGA, reduces the working frequency of the to-be-verified PCIe controller and the application layer in the verification FPGA, uses a PHY smaller than the link width of the PHY in the ASIC, and connects a standard PCIe device to perform hardware function verification after the function of the to-be-verified circuit is realized in the FPGA.

[0070] The link width NLc of the PCIe controller of the three ports of the to-be-verified circuit is 4, and the link width NLp of the PHY of the verification FPGA must be smaller than the link width NLc; to achieve the maximum frequency reduction ratio, NLp is determined to be 1; the relationship between the working frequency ff of the to-be-verified PCIe controller and the related application layer in the verification FPGA and the original design working frequency fs of the to-be-verified PCIe interface circuit and the application layer in the circuit is ff / fs=NLp / NLc=1 / 4; the original design working frequency fs of the PCIe controller of the to-be-verified PCIe interface circuit and the related application layer in the circuit is 125 MHz under the GEN1 (Generation 1, i.e., the first generation of PCIe technology) interface rate and 250 MHz under the GEN2 (Generation 2, i.e., the second generation of PCIe technology) interface rate; the working frequency ff of the to-be-verified PCIe controller and the related application layer in the verification FPGA is 31.25 MHz under the GEN1 interface rate and 62.5 MHz under the GEN2 interface rate.

[0071] Figure 3 The principle block diagram of a single port channel conversion device of the PCIe 2.0 interface circuit in the embodiment and the position of the device in the port during hardware verification after the PCIe interface circuit hardware verification method based on an alternative link width is used is shown in FIG. 2. Figure 3As shown, the embodiment verifies that the link width of the PHY in the FPGA is x1, and the link width of the PCIe controller to be verified is x4. By adding a path conversion device between the PIPE interface between the PCIe controller of the to-be-verified circuit and the PHY of the FPGA, the PCIe controller of the to-be-verified circuit with a link width of x4 can be docked with the PHY of the FPGA with a link width of x1. The added path conversion device works in the same clock mode as the PIPE interface of the PCIe controller of the to-be-verified circuit and the PHY of the FPGA.

[0072] The PCIe interface circuit hardware verification method based on alternative link width of the present application adds a path conversion device between the PIPE interface between the PCIe controller of the to-be-verified circuit in the verification FPGA and the PHY of the FPGA in the present embodiment, which is composed of a receiving conversion device and a sending conversion device; wherein the receiving conversion device comprises a detection module, a receiving module and a bit width conversion module, and each module is described as follows:

[0073] The detection module and the PHY and the receiving module interact to identify the type of data received from the PHY of the FPGA. The identifiable data types include TLP, DLLP and PLP. The length of the TLP is a multiple of 4 bytes, the start character is STP, and the end character is END or EDB. The PLP includes a link training ordered set TS1, a link training ordered set TS2, a clock compensation ordered set SKIP, a fast training ordered set FTS and an electrical idle sequence EIEOS. The length of the DLLP is 8 bytes, the start character is SDP, and the end character is END. The link training ordered sets TS1 and TS2 are composed of 16 characters, and the start character of each is COM. Symbol 0 of TS1 is the start character COM, symbol 1 is a PAD character or a link number, symbol 2 is a PAD character or a path number, symbol 3 is the number of FTS, symbol 4 is the link rate, symbol 5 carries link control information including hot reset, link disable, loopback, out-of-order enable and rate change, and symbols 6 to 15 are training sequence identifiers (TS ID). TS2 is the same as TS1 except that the TS ID is different. The start character of the SKIP ordered set is COM, which is composed of COM and 3 SKP characters. The start character of the FTS ordered set is COM, which is composed of COM and 3 FTS characters. The detection module detects and identifies the above 7 different packet formats and sends them to the receiving module for further processing. The detection module indicates the type of data received by the x1 PHY through the data_type[2:0] signal, and the values 1-7 of data_type[2:0] correspond to TLP, DLLP, link training ordered set TS1, link training ordered set TS2, clock compensation ordered set SKIP, fast training ordered set FTS and electrical idle sequence EIEOS respectively.

[0074] The receiving module interacts with the detecting module, the bit width conversion module and the PCIe controller, and is used for receiving the packet sequence identified by the detecting module, converting the packet sequence according to different states indicated by a link training state machine indication signal ltssm_state output by the PCIe controller to be verified, so that the format, information and bit width of the packet sequence of the PIPE interface data of the PHY of the FPGA converted by the channel conversion device meet the requirements of the x4 PIPE interface of the PCIe controller to be verified, and then the data signal rxdata_x4 and the data indication signal rxdatak_x4 are sent to the PIPE interface of the PCIe controller to be verified. The ltssm_state indicates 17 states of the link training state machine of the PCIe controller to be verified from 0x00 to 0x11. During the jump of ltssm_state from state 00 to state 11, the link is in the link training state, and the PLP is exchanged on the link. When the ltssm_state is state 11, the link is in the link full-on state, and can send and receive TLP, DLLP and PLP. The receiving module converts the data of the PLP, replicates the channel and converts the channel number of the link training ordered set TS1 and TS2 in the link training process; in the normal working state of the link, the TLP and DLLP are disassembled and rearranged and sent to the PIPE interface of the PCIe controller to be verified.

[0075] The bit width conversion module interacts with the PCIe controller and the receiving module, and is used for data bit width conversion and channel replication of the PLP in the link training state. When the single-channel data bit width of the PIPE interface of the PHY of the FPGA and the single-channel bit width of the PIPE interface of the PCIe controller to be verified are inconsistent, the bit width conversion module converts the link training ordered set TS1, TS2, the clock compensation ordered set SKIP, the fast training ordered set FTS and the electrical idle ordered set EIEOS according to the ltssm_state indication signal output by the PCIe controller to be verified and the data_type indication signal of the current data type output by the detecting module, so that the single-channel data bit width of the PIPE interface of the PHY and the single-channel bit width of the PIPE interface of the PCIe controller to be verified are consistent, and the converted bit width data is replicated into three parts and sent to the PCIe controller to be verified.

[0076] 3、The sending conversion function of the PCIe interface circuit hardware verification method based on the alternative link width is realized by a sending conversion device. As shown in Figure 3 The sending conversion device is composed of a sending module and a signal conversion module, and the two modules are described as follows:

[0077] The sending module interacts with the PCIe controller and the PHY module, and is used for receiving a signal output by a PIPE interface of a PCIe controller of the interface circuit to be verified, converting PIPE interface data signals output by the PCIe controller to be verified according to different states indicated by ltssm_state output by the PCIe controller to be verified, so that the converted data signals indicate a format, information and bit width of a packet sequence that meet the PIPE interface of the PHY of the FPGA, and sending the received packet sequence into the PIPE interface of the x1 PHY of the FPGA.

[0078] The signal conversion module interacts with the PCIe controller and the PHY module, and is used for bidirectional conversion of control signals and state signals of the PIPE interface between the PCIe controller of the circuit to be verified and the PHY of the FPGA, converting mac_phy_*_x4 signals output by the PIPE interface of the PCIe controller of the circuit to be verified into received signals mac_phy_*_x1 that meet the requirements of the PIPE interface of the PHY of the FPGA, and converting phy_mac_*_x4 output by the PIPE interface of the PHY into phy_mac_*_x1 input signals that meet the PIPE interface of the PCIe controller to be verified.

[0079] The specific process of the receiving conversion of the PCIe interface in this embodiment is as follows: when the PCIe link of the to-be-verified circuit is in a link training state, the detection module detects the data signal and the data indication signal received by the PHY of the FPGA, and when the data_type output by the detection module is 0x03, it indicates that the type of the data signal analyzed by the PHY of the FPGA of the to-be-verified circuit is a link training ordered set TS1; when the data_type output by the detection module is 0x04, it indicates that the type of the data signal analyzed by the PHY of the FPGA of the to-be-verified circuit is a link training ordered set TS2. The receiving module sends the single-path data signal rxdata_x1 and the data indication signal rxdatak_x1 of the PHY of the to-be-verified FPGA into the bit width conversion module, and the bit width conversion module converts them into data and data indication signals conforming to the single-path bit width of the to-be-verified PCIe controller and sends them to the receiving module; at the same time, the bit width conversion module sends the single-path rxdata_x1 and rxdata_x1 to the receiving module in triplicate, and the receiving module forms the 4-path data signal rxdata_x4 and the data indication signal rxdatak_x4 from rxdata_x1, rxdatak_x1 and the triplicated signals and sends them to the to-be-verified PCIe controller. In particular, when the PCIe link training state machine indication signal ltssm_state indicates that the link is in a Configuration state, the link negotiates the path number through TS1 and TS2, and when the paths of TS1 and TS2 are duplicated, the path number indicated by symbol 2 in the duplicated TS1 and TS2 ordered sets needs to be converted according to the actual path number corresponding to the PIPE interface of the to-be-verified PCIe controller, so as to match the path number of the to-be-verified PCIe interface controller.

[0080] When the link training is completed, TLP and DLLP are transmitted on the link. The detection module detects the data signal and the data indication signal received by the PHY of the FPGA, and when the data_type output by the detection module is 0x01, it indicates that the PIPE interface data signal and the data indication signal of the PHY of the FPGA are TLP; when the data_type output by the detection module is 0x02, it indicates that the PIPE interface data signal and the data indication signal of the PHY of the FPGA are DLLP. When the detection module detects the start character STP of the TLP, the receiving module places the start character STP in path 0 of the to-be-verified PCIe controller, and the other characters of the TLP are sequentially sent into each path of the to-be-verified PCIe controller, at which time END and EDB are located on path 3. When the detection module detects the start character SDP of the DLLP, the receiving module places the start character SDP in path 0 of the to-be-verified PCIe controller, and the other characters are sequentially sent into each path of the to-be-verified PCIe controller, at which time END is located on path 3.

[0081] In any state, when the detection module outputs data_type=0x05, it means that the data type received by the PHY of the FPGA of the to-be-verified circuit is the clock compensation ordered set SKIP signal, at this time the receiving module sends the SKIP ordered set output by the detection module into lane 0 of the to-be-verified PCIe controller, and at the same time sends the 3-way SKIP ordered set copied by the detection module into the other 3 lanes of the to-be-verified PCIe controller; when the detection module outputs data_type=0x06, it means that the data type received by the PHY of the FPGA of the to-be-verified circuit is the fast training ordered set FTS signal, at this time the receiving module sends the FTS ordered set on the lane of the PHY output by the detection module into lane 0 of the to-be-verified PCIe controller, and at the same time sends the 3-way FTS ordered set copied by the detection module into the other 3 lanes of the to-be-verified PCIe controller; when the detection module outputs data_type=0x07, it means that the data type received by the PHY of the FPGA of the to-be-verified circuit is the electrical idle ordered set EIEOS signal, at this time the receiving module sends the EIEOS ordered set on the lane of the PHY output by the detection module into lane 0 of the to-be-verified PCIe controller, and at the same time sends the 3-way EIEOS ordered set copied by the detection module into the other 3 lanes of the to-be-verified PCIe controller.

[0082] 5. The specific process of PCIe interface transmission conversion in this embodiment is as follows: The transmission module receives the data signal txdata_x4 and data indication signal txdata_x4 output from the PIPE interface of the PCIe controller to be verified, and converts them into txdata_x1 and txdatak_x1 and outputs them to the PIPE interface of the FPGA PHY. When the link of the circuit to be verified is in the link training state, when the link status indication signal ltssm_state output by the PCIe controller to be verified indicates that the data signal and data indication signal output by the PIPE interface of the PCIe controller to be verified are TS1 and TS2, the transmitting module discards the signal output by the PIPE interface of the PCIe controller to be verified and constructs an ordered set of TS1 and TS2 that conforms to the PIPE interface width of the FPGA PHY to replace the signal output by the PIPE interface of the PCIe controller to be verified and sends it to the PIPE interface of the FPGA PHY and transmits it; when ltssm_state indicates that the current state is the link number negotiation sub-state of the Configuration state, the link performs link negotiation, and the transmitting module changes the link number in the currently constructed and subsequently constructed ordered sets of TS1 and TS2 from the PAD character to the actual link number 0 of the FPGA PHY; when ltssm_state indicates that the current state is the path number negotiation sub-state of the Configuration state, the transmitting module changes the path number in the currently constructed and subsequently constructed ordered sets of TS1 and TS2 from the PAD character to the actual path number 0 of the PHY. When the link is working normally, the sending module places the start character STP or SDP of the TLP or DLLP output by the PCIe controller to be verified on path 0 of the FPGA's PHY, and places the remaining characters sequentially after the start character on path 0.

[0083] When the FTS_flag output by the PCIe controller to be verified is set, it indicates that the PCIe controller to be verified sends a fast training ordered set (FTS). The transmitting module of the transmitting conversion device constructs the fast training ordered set FTS for the FPGA PHY, sends it to the PIPE interface of the FPGA PHY, and transmits it. When the EIE_flag output by the PCIe controller to be verified is set, it indicates that the PCIe controller to be verified sends an electrical idle ordered set (EIEOS). The transmitting module constructs the electrical idle ordered set EIEOS for the FPGA PHY, sends it to the PIPE interface of the FPGA PHY, and transmits it. In any state, the transmitting module constructs a SKIP ordered set for the FPGA PHY every 1180 clock cycles, sends it to the PIPE interface of the FPGA PHY, and transmits it.

[0084] In particular, in the link training process, when the link training state signal ltssm_state of the PCIe controller of the circuit to be verified indicates that the link enters the rate shift sub-state of Recovery, the sending module in the sending conversion device discards the data output by the PIPE interface of the PCIe controller to be verified, constructs the link training ordered sets TS1 and TS2, and sends the link training ordered sets TS1 and TS2 after setting bit7 of symbol 4 to 1 to the PIPE interface of the PHY of the FPGA and sends them.

[0085] 6、The embodiment verifies that the FPGA is selected from the Virtex7 series of Xilinx Company, the path conversion device is added between the PCIe controller of each port of the circuit to be verified and the corresponding FPGA PHY, the ASIC code of the PCIe interface circuit to be verified integrated with the path conversion device is migrated to the FPGA hardware verification platform, the synthesis, layout and routing are performed at a clock frequency much lower than that in the ASIC, and an executable file is generated and downloaded to the verification FPGA for verification. The embodiment constructs a hardware verification platform with a standard x1 link PCIe interface, and the hardware connection of the verification platform is shown in Fig. 6. In the figure, the port 0, the port 1 and the port 2 of the PCIe interface circuit to be verified are connected with the standard PCIe device 1, the standard PCIe device 2 and the standard PCIe device 3 through the x1 link respectively; different test transaction packets are transmitted between the standard PCIe device 1, the standard PCIe device 2, the standard PCIe device 3 and each port of the PCIe interface circuit to be verified through the test program to verify the function and performance of the PCIe interface circuit to be verified. Figure 4

[0086] The above only describes the preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. A PCIe interface circuit verification method based on alternative link width, characterized in that, include: Identify the signal type received from the FPGA's PHY and represent the signal type as a 7-type packet sequence using the data_type[2:0] signal; The packet sequence is converted according to the different states of the indicator signal output. After conversion, the format, information and bit width of the packet sequence meet the interface requirements of the PCIe controller to be verified. The packet sequence is then sent to the PIPE interface of the PCIe controller to be verified. The system receives data signals output from the PIPE interface of the PCIe controller to be verified, converts the signals according to different states of the indicator signal output, and the converted signals indicate seven packet sequence formats, information, and bit widths that conform to the PIPE interface type of the FPGA's PHY. The converted packet sequences are then sent. The seven types of packet sequences include Physical Layer Packet (PLP), Data Link Layer Packet (DLLP), and Transaction Layer Packet (TLP). The Physical Layer Packet (PLP) includes Link Training Ordered Set (TS1), Link Training Ordered Set (TS2), Clock Compensation Ordered Set (SKIP), Fast Training Ordered Set (FTS), and Electrical Idle Sequence (EIEOS). Add a path conversion device between the PCIe controller of the circuit to be verified in the FPGA and the PIPE interface of the FPGA PHY. The control signal or status signal output from the PIPE interface of the PCIe controller of the circuit to be verified is converted into a receive signal that conforms to the requirements of the PIPE interface of the FPGA PHY, or the control signal or status signal output from the PIPE interface of the FPGA PHY is converted into an input signal that conforms to the PIPE interface of the PCIe controller to be verified.

2. The PCIe interface circuit verification method based on alternative link width according to claim 1, characterized in that, The indication signals include the link training state machine indication signal ltssm_state, the fast training ordered set indication signal FTS_flag, and the electrical idle indication signal EIE_flag.

3. The PCIe interface circuit verification method based on alternative link width according to claim 1, characterized in that, Seven packet sequence transformations are included, including PLP path replication and PLP data transformation, TLP disassembly and rearrangement, and DLLP disassembly and rearrangement. The PLP data transformation includes the transformation of path numbers in the link training ordered set TS1 and the transformation of path numbers in the link training ordered set TS2.

4. The PCIe interface circuit verification method based on alternative link width according to claim 3, characterized in that, The PLP path copying is performed by copying the received PLP packet from path 0 of the PHY to path 0 of the PCIe controller to be verified by NLc-1 copies, and then sending the copied PLP packet to the other NLc-1 paths of the PCIe controller to be verified.

5. The PCIe interface circuit verification method based on alternative link width according to claim 3, characterized in that, When the indicator signal ltssm_state indicates that the PCIe controller is in the path number negotiation state in the link training state, the path numbers in the copied link training ordered set TS1 are converted according to the actual path numbers corresponding to the PCIe controller PIPE interface, and the path numbers in the copied link training ordered set TS2 are converted according to the actual path numbers corresponding to the PCIe controller PIPE interface. When the indicator signal ltssm_state indicates that the PCIe controller is in normal operating condition, and the PHY's PIPE interface data signal and data indicator signal are TLP, the start character STP is placed in path 0 of the PCIe controller, and the subsequent characters are arranged sequentially according to the PCIe controller's path number according to the byte stripping rules; when the PHY's PIPE interface data signal and data indicator signal are DLLP, the start character SDP is placed in path 0 of the PCIe controller, and the subsequent characters are arranged sequentially according to the PCIe controller's path number according to the byte stripping rules.

6. The PCIe interface circuit verification method based on alternative link width according to claim 1, characterized in that, When receiving data signals output from the PIPE interface of the PCIe controller to be verified, and the packet sequence is TLP or DLLP, the received data signals are combined and rearranged before being sent to the PIPE interface of the FPGA's PHY. When receiving data signals output from the PIPE interface of the PCIe controller to be verified, and the packet sequence is link training ordered set TS1 and link training ordered set TS2, if the indication signal indicates that the PCIe controller is in the link number negotiation state in the link training state, the link number in link training ordered set TS1 and link training ordered set TS2 changes from the PAD character to the actual link number of the PHY. If the indication signal indicates that the PCIe controller is in the path number negotiation state in the link training state, the path number in link training ordered set TS1 and link training ordered set TS2 changes from the PAD character to the actual path number of the PHY.

7. The PCIe interface circuit verification method based on alternative link width according to claim 1, characterized in that, When the PCIe controller to be verified sends a Fast Training Ordered Set (FTS), each valid path of the PHY constructs a Fast Training Ordered Set (FTS) and sends it to the PHY's PIPE interface. The number of FTSs constructed is specified by the status indication signal output by the PCIe controller to be verified. When the PCIe controller to be verified sends an Electrically Idle Ordered Set (EIEOS), each valid path of the PHY constructs an Electrically Idle Ordered Set (EIEOS), sends it to the PHY's PIPE interface, and transmits it. According to the intervals required by the PCIe protocol, an ordered set of SKIPs is constructed on each valid path of the PHY, and the ordered set of SKIPs is sent into the PIPE interface of the PHY.

8. The PCIe interface circuit verification method based on alternative link width according to claim 1, characterized in that, When the PHY's PIPE interface outputs a clock compensation ordered set SKIP, the received ordered set of SKIPs from the PHY's path 0 is sent to path 0 of the PCIe controller to be verified; at the same time, the physical layer packet is copied, and the copied SKIPs are sent to the other NLc-1 paths of the PCIe controller to be verified. When the path conversion device detects that the PHY's PIPE interface outputs a Fast Training Ordered Set (FTS), it sends the received FTS ordered set of the PHY's path 0 to path 0 of the PCIe controller to be verified; at the same time, it performs the copying of the physical layer packet and sends the copied FTS to the other NLc-1 paths of the PCIe controller to be verified. When the path conversion device detects that the PHY's PIPE interface outputs an electrical idle ordered set EIEOS, it sends the received EIEOS ordered set of path 0 of the PHY to path 0 of the PCIe controller to be verified; at the same time, it performs the copying of the physical layer packet and sends the copied EIEOS to the other NLc-1 paths of the PCIe controller to be verified.

9. A PCIe interface circuit verification device based on alternative link width, characterized in that, include: The detection module identifies the signal type received from the FPGA's PHY and represents the signal type as a 7-type packet sequence through the data_type[2:0] signal; The receiving module is used to convert the packet sequence according to the different states of the indicator signal output. After conversion, the format, information and bit width of the packet sequence meet the interface requirements of the PCIe controller to be verified, and the packet sequence is sent to the PIPE interface of the PCIe controller to be verified. The transmitting module receives data signals output from the PIPE interface of the PCIe controller to be verified, converts the signals according to different states of the indicator signal output, and the converted signals indicate seven packet sequence formats, information, and bit widths that conform to the PIPE interface type of the FPGA's PHY. The converted packet sequence is then transmitted. The seven types of packet sequences include TLP, DLLP, Link Training Ordered Set TS1, Link Training Ordered Set TS2, Clock Compensation Ordered Set SKIP, Fast Training Ordered Set FTS, and Electrical Idle Sequence EIEOS. A path conversion device is added between the PIPE interface of the PCIe controller of the circuit to be verified in the FPGA and the FPGA's PHY. The signal conversion module is used to convert the control signal or status signal output from the PIPE interface of the PCIe controller of the circuit to be verified into a receive signal that conforms to the requirements of the PIPE interface of the FPGA PHY, or to convert the control signal or status signal output from the PIPE interface of the FPGA PHY into an input signal that conforms to the PIPE interface of the PCIe controller to be verified.

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