Impedance calibration circuit

Abstract

The present disclosure provides an impedance calibration circuit, including: a calibration module, configured to receive a first calibration clock signal and perform impedance calibration based on the first calibration clock signal, and output a first stop signal when the calibration is completed; a first detection module, configured to detect the calibration time of the impedance calibration circuit and output a second stop signal when the calibration time reaches a preset value; a calibration control module, configured to receive the first stop signal, the second stop signal and output the first calibration clock signal; when the calibration control module receives the first stop signal or the second stop signal, it stops outputting the first calibration clock signal. In addition to stopping outputting the first calibration clock signal according to the first stop signal, the calibration control module also stops outputting the first calibration clock signal according to the second stop signal, which can enable the impedance calibration circuit to stop calibration in time, meet the design requirements, effectively reduce power consumption, and improve the reliability of the impedance calibration circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and more particularly to an impedance calibration circuit. Background Art

[0002] As the operating speed of electronic devices increases, the swing width of signals transmitted between semiconductor memory devices within the electronic devices decreases to minimize the delay time taken to transmit the signals. However, as the signal swing width of the transmitted signals decreases, signal transmission is more affected by external noise. If there is an impedance mismatch at the interface, the external noise will affect the reflection characteristics of the output signal. The impedance mismatch is caused by external noise or by variations in supply voltage, operating temperature, and manufacturing process. If an impedance mismatch occurs, it is difficult to transmit data at high speed because the impedance mismatch can distort the data from the semiconductor device. Therefore, problems such as setup / hold failures or misjudgment of signal levels may occur in semiconductor devices that receive distorted data.

[0003] To mitigate these adverse situations, a memory device may include on-die termination (ODT, also referred to as "on-die termination resistor") that can be used to provide an adjustable termination impedance value. For example, when a signal (such as a command, data, etc.) is provided to the memory device, the impedance value of the on-die termination can be adjusted to reduce the impedance mismatch.

[0004] In high-speed DRAM, impedance calibration is typically performed periodically to adjust the impedance value of the on-die termination, thereby facilitating impedance matching and maintaining and calibrating signal integrity and data window in real time. The integrated circuit design specification requires that the impedance calibration circuit complete the calibration within a set time. However, existing impedance calibration circuits may not be able to complete the calibration in a timely manner and cannot meet the requirements. Summary of the Invention

[0005] Embodiments of the present disclosure provide an impedance calibration circuit that can complete calibration within a set time and meet the requirements of the design specification.

[0006] To solve the above problems, embodiments of the present disclosure provide an impedance calibration circuit, which includes: a calibration module for receiving a first calibration clock signal and performing impedance calibration based on the first calibration clock signal, and outputting a first stop signal when the calibration is completed; a first detection module for detecting the calibration time of the impedance calibration circuit and outputting a second stop signal when the calibration time reaches a preset value; a calibration control module for receiving the first stop signal, the second stop signal, and outputting the first calibration clock signal; and when the calibration control module receives the first stop signal or the second stop signal, it stops outputting the first calibration clock signal.

[0007] In one embodiment, the calibration control module includes a first logic gate circuit, which is configured to receive the first stop signal and the second stop signal, perform logic operation processing to output a first control signal, and the calibration control module stops outputting the first calibration clock signal according to the first control signal.

[0008] In one embodiment, the first logic gate circuit includes an OR gate.

[0009] In one embodiment, the calibration module includes a first calibration unit, which performs impedance calibration on the first calibration unit when the calibration module receives the first calibration clock signal; the first calibration unit includes: a first resistor unit, whose first end is connected to a first power supply terminal; a reference resistor, whose first end is connected to the second end of the first resistor unit and the second end is connected to a second power supply terminal; a first comparison unit, configured to compare the voltage at the second end of the first resistor unit with a first reference voltage and output a first comparison signal; a first detection unit, taking the first comparison signal as an input signal and recording the change condition of the first comparison signal; when the change condition of the first comparison signal meets a preset condition, output the first stop signal.

[0010] In one embodiment, the first detection unit includes an odd number of cascaded flip - flops and a second logic gate circuit. The first output terminals of the odd - level flip - flops are connected to the input terminal of the second logic gate circuit, and the second output terminals of the even - level flip - flops are connected to the input terminal of the second logic gate circuit. After logical processing by the second logic gate circuit, the first stop signal is output.

[0011] In one embodiment, the first detection unit includes an odd number of cascaded flip - flops and a second logic gate circuit. The second output terminals of the odd - level flip - flops are connected to the input terminal of the second logic gate circuit, and the first output terminals of the even - level flip - flops are connected to the input terminal of the second logic gate circuit. After logical processing by the second logic gate circuit, the first stop signal is output.

[0012] In one embodiment, the first calibration unit further includes a first calibration code generation unit, which updates a first calibration code according to the first comparison signal, and the first calibration code is used to control the equivalent resistance value of the first resistor unit.

[0013] In one embodiment, the first detection module is configured to detect the calibration time of the first calibration unit and output the second stop signal when the calibration time of the first calibration unit reaches a preset value.

[0014] In one embodiment, the calibration control module is further configured to output a second calibration clock signal, and the calibration module is further configured to receive the second calibration clock signal. When the calibration control module receives the first stop signal or the second stop signal, it stops outputting the first calibration clock signal and starts outputting the second calibration clock signal.

[0015] In one embodiment, the calibration module further includes a second calibration unit. When the calibration module receives the second calibration clock signal, it performs impedance calibration on the second calibration unit. The second calibration unit includes: a second resistor unit, whose second end is connected to a second power supply terminal; a third resistor unit, whose first end is connected to a first power supply terminal and whose second end is connected to the first end of the second resistor unit. The first calibration code is further used to control the equivalent resistance value of the third resistor unit; a second comparison unit, configured to compare the voltage at the first end of the second resistor unit with a second reference voltage and output a second comparison signal; a second detection unit, taking the second comparison signal as an input signal and recording the change condition of the second comparison signal; when the change condition of the second comparison signal meets a preset condition, output a third stop signal; when the calibration control module receives the third stop signal or the second stop signal, it stops outputting the second calibration clock signal.

[0016] In one embodiment, the first detection module is further configured to detect the calibration time of the second calibration unit and output the second stop signal when the calibration time of the second calibration unit reaches a preset value.

[0017] In one embodiment, the impedance calibration circuit further includes a clock signal generation module configured to output an initial clock signal. When the calibration control module receives the initial clock signal, it outputs the first calibration clock signal and the second calibration clock signal; when the calibration module performs impedance calibration on the second calibration unit, when the calibration control module receives the third stop signal or the second stop signal, the calibration control module outputs a stop signal to the clock signal generation module to cause the clock signal generation module to stop outputting the initial clock signal.

[0018] In one embodiment, the first detection module includes a counting module. When the calibration module performs impedance calibration on the first calibration unit and / or when the calibration module performs impedance calibration on the second calibration unit, the counting module counts the initial clock signal and outputs the second stop signal when the count value reaches a preset value.

[0019] In one embodiment, the preset value is less than or equal to 40 clock cycles.

[0020] In one embodiment, the second calibration unit further includes a second calibration code generation unit, which updates a second calibration code according to the second comparison signal, and the second calibration code is used to control the equivalent resistance value of the second resistance unit.

[0021] The impedance calibration circuit provided by the embodiments of the present disclosure provides a second stop signal. In addition to stopping the output of the first calibration clock signal according to the first stop signal, the calibration control module also stops the output of the first calibration clock signal according to the second stop signal. The second stop signal is generated when the calibration time reaches a preset value. If the first stop signal is still an invalid signal when the calibration time of the impedance calibration circuit reaches the preset value, the impedance calibration circuit stops outputting the first calibration clock signal according to the second stop signal; if the first stop signal is a valid signal when the calibration time of the impedance calibration circuit reaches the preset value or before reaching the preset value, the impedance calibration circuit stops outputting the first calibration clock signal according to the first stop signal, so that the impedance calibration circuit can stop calibration in time, make the calibration time of the impedance calibration circuit meet the design requirements, effectively reduce power consumption, and improve the reliability of the impedance calibration circuit. Description of the Drawings

[0022] Figure 1 is a schematic diagram of an impedance calibration circuit provided by an embodiment of the present disclosure;

[0023] Figure 2 is a schematic diagram of an impedance calibration circuit provided by another embodiment of the present disclosure;

[0024] Figure 3 is a schematic diagram of a first comparison unit provided by another embodiment of the present disclosure;

[0025] Figure 4A is a schematic diagram of a first detection unit provided by another embodiment of the present disclosure;

[0026] Figure 4B is a schematic diagram of a first detection unit provided by still another embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of an impedance calibration circuit provided by still another embodiment of the present disclosure;

[0028] Figure 6 is a schematic diagram of an impedance calibration circuit provided by still another embodiment of the present disclosure. Detailed Embodiments

[0029] The following will describe in detail the specific embodiments of the impedance calibration circuit provided by the embodiments of the present disclosure with reference to the drawings.

[0030] Figure 1 is a schematic diagram of an impedance calibration circuit provided by an embodiment of the present disclosure. Please refer to Figure 1, the impedance calibration circuit includes a calibration module 10, a first detection module 20, and a calibration control module 30. The calibration module 10 is configured to receive a first calibration clock signal Pclk and perform impedance calibration based on the first calibration clock signal Pclk. When the calibration is completed, a first stop signal Stop1 is output. The first detection module 20 detects the calibration time of the impedance calibration circuit and outputs a second stop signal Stop2 when the calibration time reaches a preset value. The calibration control module 30 is configured to receive the first stop signal Stop1, the second stop signal Stop2, and output the first calibration clock signal Pclk. When the calibration control module 30 receives the first stop signal Stop1 or the second stop signal Stop2, it stops outputting the first calibration clock signal Pclk.

[0031] There is a situation where the calibration module 10 fails to output a valid first stop signal Stop1 in a timely manner, resulting in the impedance calibration circuit being unable to stop outputting the first calibration clock signal Pclk in a timely manner, that is, unable to stop calibration in a timely manner. The calibration time of the impedance calibration circuit exceeds the design requirements, cannot meet the needs, and has high power consumption. Therefore, the impedance calibration circuit provided in the embodiments of the present disclosure also provides a second stop signal Stop2. In addition to stopping outputting the first calibration clock signal Pclk according to the first stop signal Stop1, the calibration control module 30 also stops outputting the first calibration clock signal Pclk according to the second stop signal Stop2. The second stop signal Stop2 is generated when the calibration time reaches a preset value. If the first stop signal Stop1 is still an invalid signal when the calibration time of the impedance calibration circuit reaches the preset value, the impedance calibration circuit stops outputting the first calibration clock signal Pclk according to the second stop signal Stop2; if the first stop signal Stop1 is a valid signal when the calibration time of the impedance calibration circuit reaches the preset value or before reaching the preset value, the impedance calibration circuit stops outputting the first calibration clock signal Pclk according to the first stop signal Stop1, so that the impedance calibration circuit can stop calibration in a timely manner, the calibration time of the impedance calibration circuit meets the design requirements, effectively reduces power consumption, and improves the reliability of the impedance calibration circuit.

[0032] Figure 2 is a schematic diagram of an impedance calibration circuit provided by another embodiment of the present disclosure. Please refer to Figure 2 , in this embodiment, the first detection module 20 includes a counting module 21. The counting module 21 counts the first calibration clock signal Pclk and outputs a second stop signal Stop2 when the count value reaches a preset value. That is to say, in this embodiment, the first detection module 20 obtains the calibration time of the impedance calibration circuit by counting the first calibration clock signal Pclk, and the count value is the number of cycles of the first calibration clock signal Pclk. In other embodiments, for example, please refer to Figure 6The first detection module 20 obtains the calibration time of the detection impedance calibration circuit by counting the initial clock signal CLK-0 of the clock signal generation module 40, and outputs a second stop signal Stop2 when the count value reaches a preset value, where the count value is the number of cycles of the initial clock signal CLK-0.

[0033] The preset value can be determined according to the design requirements. For example, in an embodiment, it is required that the calibration time of the impedance calibration circuit does not exceed 40 clock cycles, then the preset value is less than or equal to 40 clock cycles of the first calibration clock signal Pclk. For example, in this embodiment, the preset value is 40 clock cycles of the first calibration clock signal Pclk, then the counting module 21 counts the clock cycles of the first calibration clock signal Pclk, and outputs a second stop signal Stop2 when the count value is 40, that is, when the count value is 40, the logic level of the output signal of the counting module 21 becomes high, that is, the logic level of the second stop signal Stop2 becomes high, and the second stop signal Stop2 is a valid signal. The calibration control module 30 can stop outputting the first calibration clock signal Pclk according to the second stop signal Stop2. In other cases, the logic level of the second stop signal Stop2 output by the counting module 21 is low, which is an invalid signal, and the calibration control module 30 cannot stop outputting the first calibration clock signal Pclk according to the second stop signal Stop2.

[0034] It can be understood that in other embodiments, in order to ensure that the impedance calibration circuit can stop outputting the calibration clock signal in time, the preset value can also be other values less than the design requirements. For example, the preset value is less than 40 clock cycles to ensure that the impedance calibration circuit can stop outputting the calibration clock signal in time.

[0035] In some embodiments, the calibration control module 30 can achieve the purpose of stopping outputting the first calibration clock signal Pclk when receiving the first stop signal Stop1 or the second stop signal Stop2 through logical operations. Specifically, the calibration control module 30 includes a first logic gate circuit 31. The first logic gate circuit 31 is used to receive the first stop signal Stop1 and the second stop signal Stop2, and perform logical operation processing to output a first control signal Ctr1. The calibration control module 30 stops outputting the first calibration clock signal Pclk according to the first control signal Ctr1.

[0036] For example, in this embodiment, the first logic gate circuit 31 includes an OR gate. The first stop signal Stop1 and the second stop signal Stop2 serve as input signals of the OR gate, and the OR gate outputs the first control signal Ctr1. The calibration control module 30 stops outputting the first calibration clock signal Pclk according to the first control signal Ctr1. When the logic level of the first stop signal Stop1 or the second stop signal Stop2 is high (i.e., the first stop signal Stop1 is valid or the second stop signal Stop2 is valid), the logic level of the first control signal Ctr1 is high, and then the calibration control module 30 stops outputting the first calibration clock signal Pclk; when the logic levels of both the first stop signal Stop1 and the second stop signal Stop2 are low (i.e., both the first stop signal Stop1 and the second stop signal Stop2 are invalid), the calibration control module continues to output the first calibration clock signal Pclk.

[0037] In this embodiment, the calibration module 10 includes a first calibration unit 11. When the calibration module 10 receives the first calibration clock signal Pclk, it performs impedance calibration on the first calibration unit 11. The first detection module 20 is further configured to detect the calibration time of the first calibration unit 11 and output the second stop signal Stop2 when the calibration time of the first calibration unit 11 reaches a preset value. Specifically, the counting module 21 counts the first calibration clock signal Pclk and outputs the second stop signal Stop2 when the count value reaches the preset value.

[0038] The first calibration unit 11 includes a first resistor unit 111, a reference resistor R1, a first comparison unit 112, and a first detection unit 113.

[0039] The first end of the first resistor unit 111 is connected to the first power supply terminal VDD; the first end of the reference resistor R1 is connected to the second end of the first resistor unit 111, and the second end of the reference resistor R1 is connected to the second power supply terminal VSS; the first comparison unit 112 is configured to compare the voltage Vp1 at the second end of the first resistor unit 111 with the first reference voltage Vref1, and output a first comparison signal Comp1; the first detection unit 113 takes the first comparison signal Comp1 as an input signal, and records the change condition of the first comparison signal Comp1. When the change condition of the first comparison signal Comp1 meets a preset condition, a first stop signal Stop1 is output. The change condition of the first comparison signal Comp1 refers to the change of the logic level of the first comparison signal Comp1. The preset condition may include whether the logic level of the first comparison signal Comp1 changes from a first value to a second value and then continues to change from the second value to the first value. In some embodiments, the first value may represent a logic high level, and its true value may be "1", and the second value may represent a logic low level, and its true value may be "0". In other embodiments, the first value may represent a logic low level, and its true value may be "0", and the second value may represent a logic high level, and its true value may be "1". If the logic level of the first comparison signal Comp1 changes from the first value to the second value and then continues to change from the second value to the first value, that is, the logic level of the first comparison signal Comp1 jitters between the high level and the low level, then the change condition of the first comparison signal Comp1 meets the preset condition. At this time, the first detection unit 113 outputs the first stop signal Stop1.

[0040] Among them, in this embodiment, the first resistor unit 111 may include a plurality of parallel MOS transistors, and the MOS transistors include, but are not limited to, PMOS transistors. Through the first calibration code Pcode <n:0>Adjust the conduction or cutoff of the MOS transistor, thereby controlling the equivalent resistance value of the first resistor unit 111. The second terminal voltage Vp1 of the first resistor unit 111 changes as the equivalent resistance value of the first resistor unit 111 changes. The reference resistor R1 is a fixed-value resistor with an accurate resistance value, for example, 240 ohms, and the equivalent resistance value of the first resistor unit 111 can be calibrated according to the reference resistor R1. In this embodiment, the first reference voltage Vref1 can be set to VDD / 2. In other embodiments, the first reference voltage Vref1 can be set to other values.

[0041] In this embodiment, the first comparison unit 112 can be a comparator. Please refer to Figure 3 , the first comparison unit 112 is a comparator. The positive input terminal of the comparator receives the first reference voltage Vref1, and the negative input terminal is connected to the first resistor unit 111 to receive the second terminal voltage Vp1 of the first resistor unit 111. The comparator responds to the second terminal voltage Vp1 of the first resistor unit 111 and the first reference voltage Vref1 and outputs a first comparison signal Comp1. If the second terminal voltage Vp1 of the first resistor unit 111 is less than the first reference voltage Vref1, the logic level of the first comparison signal Comp1 output by the output terminal of the comparator is a high level. If the second terminal voltage Vp1 of the first resistor unit 111 is greater than the first reference voltage Vref1, the logic level of the first comparison signal Comp1 output by the output terminal of the comparator is a low level.

[0042] The first detection unit 113 uses the first comparison signal Comp1 as an input signal and outputs a first stop signal Stop1. That is to say, the first stop signal Stop1 is generated based on the first comparison signal Comp1. When the sensitivity of the first comparison unit 112 is low, the first comparison unit 112 may fail to output the first comparison signal Comp1 or output an incorrect first comparison signal (the second terminal voltage Vp1 of the first resistor unit 111 is close to the first reference voltage Vref1, and the first comparison unit 112 cannot distinguish the magnitudes of the two and cannot output a valid first comparison signal Comp1). This causes the impedance calibration circuit to fail to generate the first stop signal Stop1 in a timely manner, resulting in the impedance calibration circuit being unable to stop the calibration in a timely manner. As described above, in addition to stopping the impedance calibration process according to the first stop signal Stop1, the calibration control module 30 also stops the impedance calibration process according to the second stop signal Stop2, so that the impedance calibration circuit can stop the calibration in a timely manner, making the calibration time of the impedance calibration circuit meet the design requirements, effectively reducing power consumption, and improving the reliability of the impedance calibration circuit.

[0043] As an example, an embodiment of the present disclosure provides a structure of a first detection unit 113. The first detection unit 113 includes an odd number of cascaded flip-flops and a second logic gate circuit. The first output terminals of the flip-flops at odd levels are connected to the input terminal of the second logic gate circuit, and the second input terminals of the flip-flops at even levels are connected to the input terminal of the second logic gate circuit. After logical processing by the second logic gate circuit, a first stop signal is output.

[0044] Specifically, please refer to Figure 4A , which is a schematic diagram of the first detection unit 113 provided by an embodiment of the present disclosure. In this embodiment, the first detection unit 113 includes flip-flops D11, D12, D13, and a second logic gate circuit 113A. The flip-flops D11, D12, and D13 are cascaded. The first output terminal Q11 of the flip-flop D11 and the first output terminal Q13 of the flip-flop D13 are connected to the input terminal of the second logic gate circuit 113A, and the second output terminal Qn12 of the flip-flop D12 is connected to the input terminal of the second logic gate circuit 113A. After logical processing by the second logic gate circuit 113A, a first stop signal Stop1 is output. In this embodiment, the second logic gate circuit 113A includes a logic AND gate AND-1. The output signals of the first output terminal Q11 of the flip-flop D11, the first output terminal Q13 of the flip-flop D13, and the second output terminal Qn12 of the flip-flop D12 are subjected to an AND logic operation by the second logic gate circuit 113A to output the first stop signal Stop1. That is, when the logic levels of the output signals of the first output terminal Q11 of the flip-flop D11, the first output terminal Q13 of the flip-flop D13, and the second output terminal Qn12 of the flip-flop D12 are all high levels, the logic level of the first stop signal Stop1 output by the first detection unit 113 is a high level, which is a valid signal. The calibration control module 30 can stop outputting the first calibration clock signal Pclk according to the first stop signal Stop1. In other cases, the logic level of the first stop signal Stop1 output by the first detection unit 113 is a low level, which is an invalid signal, and the calibration control module 30 cannot stop outputting the first calibration clock signal Pclk according to the first stop signal Stop1.

[0045] An embodiment of the present disclosure also provides another structure of the first detection unit 113. The first detection unit 113 includes an odd number of cascaded flip-flops and a second logic gate circuit. The second output terminals of the flip-flops at odd levels are connected to the input terminal of the second logic gate circuit, and the first input terminals of the flip-flops at even levels are connected to the input terminal of the second logic gate circuit. After logical processing by the second logic gate circuit, a first stop signal is output.

[0046] Specifically, please refer to Figure 4B , which is a schematic diagram of the first detection unit 113 provided in another embodiment of the present disclosure. In this embodiment, the first detection unit 113 includes a flip-flop D11, a flip-flop D12, a flip-flop D13, and a second logic gate circuit 113A, and the flip-flops D11, D12, and D13 are cascaded. The second output terminal Qn11 of the flip-flop D11, the second output terminal Qn13 of the flip-flop D13 are connected to the input terminal of the second logic gate circuit 113A, and the first output terminal Q12 of the flip-flop D12 is connected to the input terminal of the second logic gate circuit 113A. After logical processing by the second logic gate circuit 113A, a first stop signal Stop1 is output. In this embodiment, the second logic gate circuit 113A includes a logic AND gate AND-1. The output signal of the second output terminal Qn11 of the flip-flop D11, the output signal of the second output terminal Qn13 of the flip-flop D13, and the output signal of the first output terminal Q12 of the flip-flop D12 are subjected to an AND logical operation by the second logic gate circuit 113A to output the first stop signal Stop1. That is, when the logic levels of the output signals of the second output terminal Qn11 of the flip-flop D11, the second output terminal Qn13 of the flip-flop D13, and the first output terminal Q12 of the flip-flop D12 are all high levels, the logic level of the first stop signal Stop1 output by the first detection unit 113 is a high level, which is a valid signal, and the calibration control module 30 can stop outputting the first calibration clock signal Pclk according to the first stop signal Stop1. In other cases, the logic level of the first stop signal Stop1 output by the first detection unit 113 is a low level, which is an invalid signal, and the calibration control module 30 cannot stop outputting the first calibration clock signal Pclk according to the first stop signal Stop1.

[0047] In the above example, the first detection unit 113 includes three cascaded flip-flops. In other embodiments, the first detection unit 113 may further include five cascaded flip-flops or other odd numbers of cascaded flip-flops, which are all within the scope of the present disclosure embodiments.

[0048] In some embodiments, the first calibration unit further includes a first calibration code generation unit, and the first calibration code generation unit updates the first calibration code according to the first comparison signal, and the first calibration code is used to control the equivalent resistance value of the first resistance unit.

[0049] Specifically, please continue to refer to Figure 2 , the first calibration unit 11 further includes a first calibration code generation unit 114, and the first calibration code generation unit 114 updates the first calibration code Pcode according to the first comparison signal Comp1 <n:0>, the first calibration code Pcode <n:0>For controlling the equivalent resistance value of the first resistance unit 111. In some embodiments, the first calibration code generation unit 114 may be a counter.

[0050] According to the different magnitude relationships between the second terminal voltage Vp1 of the first resistance unit 111 and the first reference voltage Vref1, the first comparison signal Comp1 may be an upward signal and a downward signal. For example, when the second terminal voltage Vp1 of the first resistance unit 111 is less than the first reference voltage Vref1, the first comparison signal Comp1 is a downward signal; when the second terminal voltage Vp1 of the first resistance unit 111 is greater than the first reference voltage Vref1, the first comparison signal Comp1 is an upward signal. When the first comparison signal Comp1 is an upward signal, the count value of the first calibration code generation unit 114 is incremented by 1, and the first calibration code Pcode is output. <n:0>, according to the first calibration code Pcode <n:0>Reduce the equivalent resistance of the first resistance unit 111, thereby reducing the second terminal voltage Vp1 of the first resistance unit 111 until the second terminal voltage Vp1 of the first resistance unit 111 is equal to the first reference voltage Vref1; when the first comparison signal Comp1 is a down signal, the count value of the first calibration code generation unit 114 is decreased by 1, and the first calibration code Pcode is output <n:0>, according to the first calibration code Pcode <n:0>Increase the equivalent resistance of the first resistance unit 111, thereby increasing the second terminal voltage Vp1 of the first resistance unit 111 until the second terminal voltage Vp1 of the first resistance unit 111 is equal to the first reference voltage Vref1.

[0051] In addition to stopping the output of the first calibration clock signal Pclk according to the first stop signal Stop1, the calibration control module 30 provided in the embodiment of the present disclosure also stops the output of the first calibration clock signal Pclk according to the second stop signal Stop2, so that the impedance calibration circuit can stop calibration in time, making the calibration time of the impedance calibration circuit meet the design requirements, effectively reducing power consumption, and improving the reliability of the impedance calibration circuit.

[0052] The above only lists the case where the calibration module 10 includes one calibration unit (the first calibration unit 11). In the case where the calibration module 10 includes multiple calibration units, the multiple calibration units can perform calibration independently. For example, when one calibration unit completes calibration, another calibration unit can start to perform calibration. Each calibration unit corresponds to a stop signal, so that after the calibration unit completes calibration, the calibration control module 30 stops outputting the calibration clock signal corresponding to the calibration unit according to the stop signal.

[0053] Specifically, please refer to Figure 5 , which is a schematic diagram of an impedance calibration circuit provided in another embodiment of the present disclosure. In this embodiment, the calibration control module 30 is further configured to output a second calibration clock signal Nclk. When the calibration control module 30 receives the first stop signal Stop1 or the second stop signal Stop2, it stops outputting the first calibration clock signal Pclk and starts to output the second calibration clock signal Nclk. When the calibration module 10 receives the second calibration clock signal Nclk, it performs impedance calibration on the second calibration unit 11. The calibration module 10 includes a first calibration unit 11 and a second calibration unit 12. After the first calibration unit 11 completes calibration, the calibration control module 30 stops outputting the first calibration clock signal Pclk corresponding to the first calibration unit 11 according to the first stop signal Stop1 or the second stop signal Stop2. After an interval of several time, the calibration control module 30 starts to output the second calibration clock signal Nclk corresponding to the second calibration unit 12, and the second calibration unit 12 can start to perform impedance calibration. In some embodiments, after the first calibration unit 11 completes calibration, the calibration control module 30 can start to output the second calibration clock signal Nclk corresponding to the second calibration unit 12 without waiting for several time.

[0054] When the second calibration unit 12 performs an impedance calibration process, the first detection module 20 starts to detect the calibration time of the second calibration unit 12 and outputs a second stop signal Stop2 when the calibration time reaches a preset value. That is to say, when the second calibration unit 12 starts to execute the calibration process, the counting module 21 of the first detection module 20 counts the second calibration clock signal Nclk and outputs the second stop signal Stop2 when the count value reaches the preset value. The count value is the number of cycles of the first calibration clock signal Pclk, and the preset value is less than or equal to 40 clock cycles of the second calibration clock signal Nclk. In other embodiments, for example, please refer to Figure 6 , the counting module 21 of the first detection module 20 obtains the calibration time of the detection impedance calibration circuit by counting the initial clock signal CLK-0 of the clock signal generation module 40 and outputs the second stop signal Stop2 when the count value reaches the preset value. Wherein, the count value is the number of cycles of the initial clock signal CLK-0, and the preset value is less than or equal to 40 clock cycles of the initial clock signal CLK-0.

[0055] The second calibration unit 12 can output a third stop signal Stop3, and the calibration control module 30 stops outputting the second calibration clock signal Nclk corresponding to the second calibration unit 12 according to the third stop signal Stop3 or the second stop signal Stop2.

[0056] Please continue to refer to Figure 5 , the calibration control module 30 includes a third logic gate circuit 32. The third logic gate circuit 32 is used to receive the second stop signal Stop2 and the third stop signal Stop3 and perform logical operation processing to output a second control signal Ctr2. The calibration control module 30 stops outputting the second calibration clock signal Nclk according to the second control signal Ctr2. The structure and operating principle of the third logic gate circuit 32 are the same as those of the first logic gate circuit 31 and will not be elaborated here.

[0057] Please continue to refer to Figure 5 , in this embodiment, the second calibration unit 12 includes a second resistor unit 121, a third resistor unit 125, a second comparison unit 122 and a second detection unit 123.

[0058] The second end of the second resistor unit 121 is connected to the first power supply terminal VDD; the first end of the third resistor unit 125 is connected to the first power supply terminal VDD, the second end of the third resistor unit 125 is connected to the first end of the second resistor unit 121, and the first calibration code Pcode <n:0>It is also used to control the equivalent resistance value of the third resistor unit 125; the second comparison unit 122 is used to compare the first terminal voltage Vp2 of the second resistor unit 121 with the second reference voltage Vref2, and output a second comparison signal Comp2; the second detection unit 123 uses the second comparison signal Comp2 as an input signal to record the change of the second comparison signal Comp2; when the change of the second comparison signal Comp2 meets a preset condition, a third stop signal Stop3 is output. The definition of the change of the second comparison signal Comp2 and the preset condition is the same as that of the change of the first comparison signal Comp1 and the preset condition, which will not be elaborated here.

[0059] In this embodiment, the second resistor unit 121 may include multiple parallel MOS transistors, and the MOS transistors include but are not limited to NMOS transistors. Through the second calibration code Ncode <n:0>Adjust the on or off state of the MOS transistor, thereby controlling the equivalent resistance value of the second resistor unit 121. The voltage Vp2 at the first end of the second resistor unit 121 changes as the equivalent resistance value of the second resistor unit 121 changes. The third resistor unit 125 may have the same structure as the first resistor unit 111 and may adopt the first calibration code Pcode <n:0>Control the equivalent resistance value of the third resistor unit 125, and then the second resistor unit 121 can be calibrated through the third resistor unit 125.

[0060] In this embodiment, the second comparison unit 122 is a comparator, and its structure can be the same as that of the first comparison unit 112. The positive input terminal of the comparator receives the second reference voltage Vref2, and the negative input terminal is connected to the second resistor unit 121 to receive the first terminal voltage Vp2 of the second resistor unit 121. The comparator responds to the first terminal voltage Vp2 of the second resistor unit 121 and the second reference voltage Vref2 and outputs a second comparison signal Comp2. If the first terminal voltage Vp2 of the second resistor unit 121 is less than the second reference voltage Vref2, the logic level of the second comparison signal Comp2 output by the output terminal of the comparator is high level. If the first terminal voltage Vp2 of the second resistor unit 121 is greater than the second reference voltage Vref2, the logic level of the second comparison signal Comp2 output by the output terminal of the comparator is low level.

[0061] The second detection unit 123 uses the second comparison signal Comp2 as an input signal and outputs a third stop signal Stop3. That is to say, the third stop signal Stop3 is generated based on the second comparison signal Comp2. When the sensitivity of the second comparison unit 122 is low, the second comparison unit 122 may fail to output the second comparison signal Comp2 or output an incorrect second comparison signal (the first terminal voltage Vp2 of the second resistor unit 121 is close to the second reference voltage Vref2, and the second comparison unit 122 cannot distinguish their magnitudes and cannot output a valid second comparison signal Comp2). This causes the impedance calibration circuit to fail to generate the third stop signal Stop3 in a timely manner, resulting in the impedance calibration circuit being unable to stop the calibration in a timely manner. As described above, in addition to stopping the impedance calibration process according to the third stop signal Stop3, the calibration control module 30 also stops the impedance calibration process according to the second stop signal Stop2, so that the impedance calibration circuit can stop the calibration in a timely manner, making the calibration time of the impedance calibration circuit meet the design requirements, effectively reducing power consumption, and improving the reliability of the impedance calibration circuit.

[0062] In one embodiment, the structure of the second detection unit 123 is the same as that of the first detection unit 113. Please refer to Figure 4A and Figure 4B , which will not be elaborated here.

[0063] In this embodiment, the second calibration unit 12 further includes a second calibration code generation unit 124, and the second calibration code generation unit 124 updates the second calibration code Ncode according to the second comparison signal Comp <n:0>, the second calibration code Ncode <n:0>For controlling the equivalent resistance value of the second resistor unit 121. In some embodiments, the second calibration code generation unit 124 may be a counter.

[0064] According to the different magnitude relationships between the first terminal voltage Vp2 of the second resistor unit 121 and the second reference voltage Vref2, the second comparison signal Comp2 may be an upward signal and a downward signal (if the first terminal voltage Vp2 of the second resistor unit 121 is less than the second reference voltage Vref2, a downward signal is output; if the first terminal voltage Vp2 of the second resistor unit 121 is greater than the second reference voltage Vref2, an upward signal is output). When the second comparison signal Comp2 is an upward signal, the count value of the second calibration code generation unit 124 is incremented by 1, and the second calibration code Ncode is output. <n:0>, according to the second calibration code Ncode <n:0>Reduce the equivalent resistance value of the second resistance unit 121, thereby reducing the first terminal voltage Vp2 of the second resistance unit 121 until the first terminal voltage Vp2 of the second resistance unit 121 is equal to the second reference voltage Vref2; when the second comparison signal Comp2 is a downward signal, the count value of the second calibration code generation unit 124 is decremented by 1, and the second calibration code Ncode is output <n:0>, so as to increase the resistance value of the second resistance unit 121, and further increase the first-end voltage Vp2 of the second resistance unit 121 until the first-end voltage Vp2 of the second resistance unit 121 is equal to the second reference voltage Vref2. In addition to being able to stop the impedance calibration process according to the first stop signal Stop1 and the third stop signal Stop3 respectively, the calibration control module 30 of the impedance calibration circuit provided by the embodiments of the present disclosure also stops the impedance calibration process according to the second stop signal Stop2, so that the impedance calibration circuit can stop calibration in time, making the calibration time of the impedance calibration circuit meet the design requirements, effectively reducing power consumption, and improving the reliability of the impedance calibration circuit.

[0065] In one embodiment, the impedance calibration circuit further includes a clock signal generation module. Please refer to Figure 6 , which is a schematic diagram of the impedance calibration circuit provided by another embodiment of the present disclosure. In this embodiment, the impedance calibration circuit includes a clock signal generation module 40.

[0066] The impedance clock signal generation module 40 is used to output an initial clock signal CLK-0. When the calibration control module 30 receives the initial clock signal CLK-0, it outputs a first calibration clock signal Pclk and a second calibration clock signal Nclk; when the calibration module 10 performs impedance calibration on the second calibration unit 12, when the calibration control module 30 receives the third stop signal Stop3 or the second stop signal Stop2, it outputs a stop signal Stop4 to the clock signal generation module 40 to make the clock signal generation module 40 stop outputting the initial clock signal CLK-0. In some embodiments, the clock signal generation module 40 can be a ring oscillator.

[0067] In this embodiment, the first detection module 20 is used to generate the second stop signal Stop2 according to the initial clock signal CLK-0. The first detection module 20 includes a counting module 21. When the calibration module 10 performs impedance calibration on the first calibration unit 11 and / or when the calibration module 10 performs impedance calibration on the second calibration unit 12, the counting module 21 counts the initial clock signal CLK-0 and outputs the second stop signal Stop2 when the count value reaches a preset value. Wherein, the count value is the number of cycles of the initial clock signal CLK-0, and the preset value is less than or equal to 40 clock cycles of the initial clock signal CLK-0.

[0068] Specifically, when the calibration module 10 calibrates the first calibration unit 11, the counting module 21 counts the initial clock signal CLK-0, and outputs a second stop signal Stop2 when the count value reaches a preset value. When the calibration control module 30 receives the first stop signal Stop1 or the second stop signal Stop2, it stops outputting the first calibration clock signal Pclk. When the calibration module 10 finishes calibrating the first calibration unit 11, the counting module 21 resets to zero. When the calibration module 10 calibrates the second calibration unit 12, the counting module 21 counts the initial clock signal CLK-0, and outputs a second stop signal Stop2 when the count value reaches a preset value. When the calibration control module 30 receives the third stop signal Stop3 or the second stop signal Stop2, it stops outputting the second calibration clock signal Nclk, and outputs a stop signal Stop4 to the clock signal generation module 40 to make the clock signal generation module 40 stop outputting the initial clock signal CLK-0.

[0069] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An impedance calibration circuit, characterized in that, Including: A calibration module, configured to receive a first calibration clock signal, perform impedance calibration based on the first calibration clock signal, and output a first stop signal when the calibration is completed; A first detection module, detecting the calibration time of the impedance calibration circuit, and outputting a second stop signal when the calibration time reaches a preset value; A calibration control module, configured to receive the first stop signal, the second stop signal, and output the first calibration clock signal; When the calibration control module receives the first stop signal or the second stop signal, it stops outputting the first calibration clock signal; The calibration module includes a first calibration unit, and when the calibration module receives the first calibration clock signal, it performs impedance calibration on the first calibration unit; The first calibration unit includes: A first resistor unit, whose first end is connected to a first power supply terminal; A reference resistor, whose first end is connected to the second end of the first resistor unit, and the second end is connected to a second power supply terminal; A first comparison unit, configured to compare the voltage at the second end of the first resistor unit with a first reference voltage, and output a first comparison signal; A first detection unit, taking the first comparison signal as an input signal, and recording the change condition of the first comparison signal; when the change condition of the first comparison signal meets a preset condition, it outputs the first stop signal; The first detection unit includes an odd number of cascaded flip - flops and a second logic gate circuit. In the cascaded odd number of flip - flops, the first output terminal of the previous - stage flip - flop is connected to the data input terminal of the next - stage flip - flop. The data input terminal of the first - stage flip - flop receives the first comparison signal. The first output terminal of the odd - numbered flip - flops is connected to the input terminal of the second logic gate circuit, and the second output terminal of the even - numbered flip - flops is connected to the input terminal of the second logic gate circuit. After the logical processing of the second logic gate circuit, the first stop signal is output; or, The first detection unit includes an odd number of cascaded flip - flops and a second logic gate circuit. In the cascaded odd number of flip - flops, the first output terminal of the previous - stage flip - flop is connected to the data input terminal of the next - stage flip - flop. The data input terminal of the first - stage flip - flop receives the first comparison signal. The second output terminal of the odd - numbered flip - flops is connected to the input terminal of the second logic gate circuit, and the first output terminal of the even - numbered flip - flops is connected to the input terminal of the second logic gate circuit. After the logical processing of the second logic gate circuit, the first stop signal is output.

2. The impedance calibration circuit according to claim 1, wherein The calibration control module includes a first logic gate circuit, which is configured to receive the first stop signal and the second stop signal, and perform logical operation processing to output a first control signal. The calibration control module stops outputting the first calibration clock signal according to the first control signal.

3. The impedance calibration circuit according to claim 2, wherein The first logic gate circuit includes an OR gate.

4. The impedance calibration circuit according to claim 1, wherein The first calibration unit further includes a first calibration code generation unit, which updates a first calibration code according to the first comparison signal, and the first calibration code is used to control the equivalent resistance value of the first resistor unit.

5. The impedance calibration circuit according to claim 4, wherein The first detection module is used to detect the calibration time of the first calibration unit, and output the second stop signal when the calibration time of the first calibration unit reaches a preset value.

6. The impedance calibration circuit according to claim 5, wherein The calibration control module is further used to output a second calibration clock signal, and the calibration module is further used to receive the second calibration clock signal. When the calibration control module receives the first stop signal or the second stop signal, it stops outputting the first calibration clock signal and starts outputting the second calibration clock signal.

7. The impedance calibration circuit according to claim 6, wherein The calibration module further includes a second calibration unit. When the calibration module receives the second calibration clock signal, it performs impedance calibration on the second calibration unit. The second calibration unit includes: A second resistor unit, whose second end is connected to a second power supply terminal; A third resistor unit, whose first end is connected to a first power supply terminal, and whose second end is connected to the first end of the second resistor unit. The first calibration code is further used to control the equivalent resistance value of the third resistor unit; A second comparison unit, which is used to compare the voltage at the first end of the second resistor unit with a second reference voltage, and output a second comparison signal; A second detection unit, which uses the second comparison signal as an input signal and records the change condition of the second comparison signal; when the change condition of the second comparison signal meets a preset condition, it outputs a third stop signal; When the calibration control module receives the third stop signal or the second stop signal, it stops outputting the second calibration clock signal.

8. The impedance calibration circuit according to claim 7, wherein The first detection module is further used to detect the calibration time of the second calibration unit, and output the second stop signal when the calibration time of the second calibration unit reaches a preset value.

9. The impedance calibration circuit according to claim 7, wherein The impedance calibration circuit further includes a clock signal generation module, which is used to output an initial clock signal. When the calibration control module receives the initial clock signal, it outputs the first calibration clock signal and the second calibration clock signal; When the calibration module performs impedance calibration on the second calibration unit, when the calibration control module receives the third stop signal or the second stop signal, the calibration control module outputs a stop signal to the clock signal generation module to make the clock signal generation module stop outputting the initial clock signal.

10. The impedance calibration circuit according to claim 9, wherein The first detection module includes a counting module. When the calibration module performs impedance calibration on the first calibration unit and / or when the calibration module performs impedance calibration on the second calibration unit, the counting module counts the initial clock signal, and outputs the second stop signal when the count value reaches a preset value.

11. The impedance calibration circuit according to any one of claims 1 to 10, characterized in that, The preset value is less than or equal to 40 clock cycles.

12. The impedance calibration circuit according to claim 7, wherein The second calibration unit further includes a second calibration code generation unit, which updates the second calibration code according to the second comparison signal. The second calibration code is used to control the equivalent resistance value of the second resistor unit.

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