Preparation method of semiconductor surface slot and preparation of IGBT device surface slot

Abstract

The present invention proposes a method for preparing a semiconductor surface slot and an IGBT device surface slot, the preparation method comprising: S101, coating an organic carbon layer on a silicon substrate surface; S102, preparing a first protective portion on the sidewall of the organic carbon layer; S103, preparing an organic carbon protective portion on the outer surface of the first protective portion; S104, etching to prepare a groove under the protection of the organic carbon protective portion; S105, removing the organic carbon layer and the organic carbon protective portion; S106, performing a high-temperature oxidation process on the silicon substrate to form an oxide layer; S107, filling the trench with polysilicon; S108, implanting N into the silicon substrate. + S109, forming an ILD layer on the silicon substrate surface; S110, forming a second protective portion and a metal hole adjacent to the first protective portion; S111, filling the metal hole with metal under the protection of the second protective portion. The present invention provides barrier protection during the trench and contact hole fabrication and filling processes by providing a first and second protective portion and utilizing different material selection ratios, thereby improving the yield rate of trench and contact hole fabrication.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a semiconductor surface slot and an IGBT device surface slot. Background Art

[0002] The fabrication of semiconductor devices involves the preparation of surface trenches and contact holes. For highly integrated, small-sized semiconductor devices, creating contact holes between closely spaced trenches can damage the trenches. Furthermore, when metal is filled into the contact holes, it can easily short-circuit with the metal in the trenches, impacting the yield of the semiconductor device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to improve the success rate of preparing contact holes between trenches with smaller distances on the semiconductor surface. The present invention proposes a method for preparing trench holes on the surface of a semiconductor and a method for preparing trench holes on the surface of an IGBT device.

[0004] A method for preparing a semiconductor surface trench according to an embodiment of the present invention includes:

[0005] S101, coating an organic carbon layer on a silicon substrate;

[0006] S102, preparing a first protective portion on a side wall of the organic carbon layer;

[0007] S103, preparing an organic carbon protective portion on the outer surface of the first protective portion;

[0008] S104, etching to prepare a groove under the protection of the organic carbon protective portion;

[0009] S105, removing the organic carbon layer and the organic carbon protection portion;

[0010] S106, performing a high-temperature oxidation process on the silicon substrate to form an oxide layer;

[0011] S107, filling the trench with polysilicon;

[0012] S108, injecting N into the silicon base + ;

[0013] S109, preparing an ILD layer on the silicon substrate surface;

[0014] S110, preparing a second protective portion and a metal hole near the position of the first protective portion;

[0015] S111 , filling the metal hole with metal under the protection of the second protective portion.

[0016] According to the method for preparing semiconductor surface grooves in an embodiment of the present invention, during the preparation process of IGBT devices or other semiconductor devices, the present invention provides a first protective portion and a second protective portion, and utilizes different etching selectivity ratios between the first protective portion and the second protective portion and the silicon base to perform blocking protection during the preparation and filling of grooves and contact holes, thereby avoiding the problem of short circuit between the grooves and the contact holes, facilitating the preparation of contact holes between small-sized grooves, and improving the preparation yield of semiconductor devices.

[0017] According to some embodiments of the present invention, in step S105 , oxygen-containing plasma etching is used to remove the organic carbon layer and the organic carbon protection portion.

[0018] In some embodiments of the present invention, in step S108, when injecting the N+, different preset tilt angles are used through the ion implantation equipment to perform the implantation in multiple times, or the ion implantation equipment is set to a preset tilt angle and the N+ implantation is completed by rotating the silicon base.

[0019] According to some embodiments of the present invention, the first guarding parts are divided into multiple groups, each group of the first guarding parts includes two first guarding parts spaced apart from each other, and the groove is prepared by etching between two adjacent first guarding parts in each group.

[0020] In some embodiments of the present invention, two second guarding portions are provided at intervals between two adjacent grooves, and the metal hole is prepared by etching between the two adjacent second guarding portions.

[0021] According to some embodiments of the present invention, in step S110, a metal hole is first prepared at a position adjacent to the first protective portion, and then the second protective portion is prepared on the inner wall of the metal hole; or a partial segment of the metal hole is first prepared at a position adjacent to the first protective portion, and after the second protective portion is prepared on the inner wall of the partial segment, the remaining portion of the metal hole is prepared.

[0022] In some embodiments of the present invention, the first guard portion and the second guard portion are silicon nitride guard portions.

[0023] According to some embodiments of the present invention, the distance between the two grooves on both sides of the metal hole is not less than the inner diameter of the contact hole.

[0024] According to the manufacturing process of the IGBT device of the embodiment of the present invention, the manufacturing process of the IGBT device adopts the above-mentioned method for manufacturing semiconductor surface grooves to manufacture the surface grooves of the IGBT.

[0025] According to some embodiments of the present invention, the manufacturing process of the IGBT device adopts the above-mentioned method for manufacturing semiconductor surface slots to manufacture metal holes on the surface of the IGBT.

[0026] In the process of preparing IGBT devices or other semiconductor devices, the present invention provides a first protective portion and a second protective portion, and utilizes different etching selectivities of an organic carbon layer and silicon nitride to provide blocking protection during the preparation and filling of trenches and contact holes, thereby avoiding the problem of short circuit caused by the connection between polysilicon in the trench and the metal in the contact hole. In addition, the first protective portion and the second protective portion can protect the N-type silicon nitride below when preparing the contact hole. + Perform blocking protection to avoid N + In addition, the method facilitates the preparation of small-sized contact holes between trenches, thereby improving the yield rate of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Flowchart of a method for preparing semiconductor surface trenches according to an embodiment of the present invention;

[0028] Figure 2 Schematic diagram of coating an organic carbon layer on a silicon-based surface in a method for preparing semiconductor surface trenches according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of preparing a first protective portion on the sidewall of an organic carbon layer in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of preparing an organic carbon protective portion on the outer surface of a first protective portion in a method for preparing a semiconductor surface groove according to an embodiment of the present invention;

[0031] Figure 5 Schematic diagram of etching to prepare trenches under the protection of the organic carbon protective portion in the method for preparing trenches on the surface of a semiconductor according to an embodiment of the present invention;

[0032] Figure 6 Schematic diagram of removing the organic carbon layer and the organic carbon protection portion in the method for preparing semiconductor surface trenches according to an embodiment of the present invention;

[0033] Figure 7 A schematic diagram of forming an oxide layer by performing a high-temperature oxidation process on a silicon substrate in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0034] Figure 8 Schematic diagram of filling polysilicon in a trench in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0035] Figure 9 In the method for preparing the semiconductor surface slot according to the embodiment of the present invention, N is implanted into the silicon substrate. + ;

[0036] Figure 10Schematic diagram of preparing an ILD layer on a silicon-based surface in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0037] Figure 11 A schematic diagram of a partial segment of a metal hole formed near a first protective portion in a method for forming a semiconductor surface slot according to an embodiment of the present invention;

[0038] Figure 12 A schematic diagram of preparing a second protective portion on the inner wall of a partial segment of a contact hole in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0039] Figure 13 Schematic diagram of the remaining portion of a contact hole in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0040] Figure 14 In the method for preparing the semiconductor surface slot according to the embodiment of the present invention, P is injected + Schematic diagram;

[0041] Figure 15 Schematic diagram of contact hole filling metal in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0042] Figure 16 A schematic diagram of preparing a complete contact hole in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0043] Figure 17 Schematic diagram of preparing a second protective portion on the inner wall of a metal hole in a method for preparing a semiconductor surface slot according to an embodiment of the present invention;

[0044] Figure 18 In the method for preparing the semiconductor surface slot according to the embodiment of the present invention, P is injected + Schematic diagram;

[0045] Figure 19 Schematic diagram of contact hole filling metal in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0046] Figure 20 A schematic diagram of preparing a complete contact hole in a method for preparing a semiconductor surface trench according to an embodiment of the present invention;

[0047] Figure 21 Schematic diagram of preparing a second protective portion on the inner wall of a metal hole in a method for preparing a semiconductor surface slot according to an embodiment of the present invention;

[0048] Figure 22 In the method for preparing the semiconductor surface slot according to the embodiment of the present invention, P is injected + Schematic diagram;

[0049] Figure 23 Schematic diagram of contact hole filling metal in a method for preparing a semiconductor surface trench according to an embodiment of the present invention.

[0050] Reference numerals:

[0051] Silicon base 10, organic carbon layer 110, organic carbon protection portion 120, trench 130, oxide layer 140, polysilicon 150, ILD layer 160, contact hole 170,

[0052] A first protection portion 210 and a second protection portion 220 . DETAILED DESCRIPTION

[0053] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose, the present invention is described in detail below with reference to the accompanying drawings and preferred embodiments.

[0054] The description of the method flow in the specification and the steps in the flowcharts in the drawings of the specification do not necessarily need to be strictly executed according to the step numbers. The method steps may be executed in a different order. Furthermore, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0055] like Figure 1-Figure 23 As shown, the method for preparing a semiconductor surface slot according to an embodiment of the present invention includes:

[0056] S101, such as Figure 2 As shown, an organic carbon layer 110 is coated on the surface of the silicon substrate 10;

[0057] For example, SOC (organic carbon layer 110 coating) can be prepared on the surface of the silicon substrate 10. Thus, the different etching selectivities between the organic carbon layer 110 and the silicon substrate 10 can be used to protect the predetermined portion during the etching process.

[0058] S102, such as Figure 3 As shown, a first protective portion 210 is prepared on the side wall of the organic carbon layer 110;

[0059] For example, the first protection portion 210 may be PESiON (silicon nitride).

[0060] S103, such as Figure 4 As shown, an organic carbon protective portion 120 is prepared on the outer surface of the first protective portion 210;

[0061] The organic carbon protection portion 120 may be a SOC (coated organic carbon layer 110 ) to provide protection during etching by utilizing different selectivity ratios between silicon nitride and the organic carbon layer 110 .

[0062] S104, such as Figure 5 As shown, under the protection of the organic carbon protection portion 120, the trench 130 is prepared by etching;

[0063] When preparing the trench 130, due to the difference in etching selectivity between the organic carbon protection portion 120 and the silicon substrate 10,

[0064] S105, such as Figure 6 As shown, the organic carbon layer 110 and the organic carbon protection portion 120 are removed;

[0065] According to some embodiments of the present invention, in step S105 , oxygen-containing plasma etching is used to remove the organic carbon layer 110 and the organic carbon protection portion 120 .

[0066] S106, such as Figure 7 As shown, a high temperature oxidation process is performed on the silicon substrate 10 to form an oxide layer 140;

[0067] For example, the oxide layer 140 formed on the surface of the silicon substrate 10 is SiO 2 .

[0068] S107, such as Figure 8 As shown, the trench 130 is filled with polysilicon 150;

[0069] When filling the polysilicon 150 , it is necessary to first deposit the polysilicon 150 in the trench 130 and then perform a planarization process.

[0070] S108, such as Figure 9 As shown, N is implanted into the silicon base 10. + ;

[0071] In some embodiments of the present invention, in step S108, after injecting N + When the ion implantation device is used, different tilt preset angles are used to implant the ion implantation device multiple times. Alternatively, the ion implantation device is set to a tilt preset angle, and the N + injection.

[0072] It should be noted that due to the provision of the first guard 210, when performing ion implantation, if the ion implantation equipment performs vertical implantation, the first guard 210 blocks the implantation and prevents the implantation from reaching below the first guard 210. Therefore, the ion implantation equipment needs to be tilted at a preset angle for ion implantation. For example, the tilt angle of the ion implantation equipment can range from 15° to 60°.

[0073] S109, such as Figure 10 As shown, an ILD layer 160 is prepared on the surface of the silicon substrate 10;

[0074] When preparing the ILD layer 160 , a planarization process is required after depositing the material of the ILD layer 160 .

[0075] S110, such as Figure 11-Figure 23 As shown, the second protection portion 220 and the contact hole 170 are prepared near the first protection portion 210;

[0076] According to some embodiments of the present invention, in step S110, Figure 16-Figure 23 As shown, a contact hole 170 is first formed at a position adjacent to the first protective portion 210, and then a second protective portion 220 is formed on the inner wall of the contact hole 170; or as shown in FIG. Figure 11-Figure 15 As shown, a partial segment of the contact hole 170 is first prepared at a position adjacent to the first protective portion 210 , and the second protective portion 220 is prepared on the inner wall of the partial segment, and then the remaining portion of the contact hole 170 is prepared.

[0077] Among them, such as Figure 20-23 As shown, when the contact hole 170 is too large, by preparing a second protective portion 220 on the inner wall of the contact hole 170, the problem of short circuit between the contact hole 170 and the trench 130 when the contact hole 170 is filled with metal can be avoided.

[0078] S111, such as Figure 15 As shown, the metal-filled contact hole 170 is protected by the second protection portion 220 .

[0079] According to some embodiments of the present invention, Figure 3-Figure 8 As shown, there are multiple groups of first guarding portions 210 , each group of first guarding portions 210 includes two first guarding portions 210 spaced apart from each other, and a groove 130 is prepared by etching between two adjacent first guarding portions 210 in each group.

[0080] In some embodiments of the present invention, Figure 12 As shown, two second protection portions 220 are disposed at intervals between two adjacent trenches 130 , and a contact hole 170 is formed by etching between the two adjacent second protection portions 220 .

[0081] In some embodiments of the present invention, the first protection portion 210 and the second protection portion 220 are silicon nitride protection portions.

[0082] According to some embodiments of the present invention, the distance between the two trenches 130 on both sides of the contact hole 170 is not less than the inner diameter of the contact hole 170. The distance between the two trenches 130 may be in the range of 20 nm to 1 μm.

[0083] According to the manufacturing process of the IGBT device of the embodiment of the present invention, the manufacturing process of the IGBT device adopts the above-mentioned method for manufacturing semiconductor surface grooves to manufacture the surface grooves 130 of the IGBT.

[0084] According to some embodiments of the present invention, the manufacturing process of the IGBT device adopts the above-mentioned method for manufacturing the semiconductor surface slot to manufacture the metal hole on the surface of the IGBT.

[0085] In summary, in the process of preparing an IGBT device or other semiconductor device, the present invention provides a first protective portion 210 and a second protective portion 220, and utilizes different etching selectivities between the organic carbon layer 110 and the silicon nitride to provide blocking protection during the preparation and filling of the trench 130 and the contact hole 170, thereby avoiding the problem of short circuit caused by the polysilicon in the trench 130 being connected to the metal in the contact hole 170. Moreover, the first protective portion 210 and the second protective portion 220 can protect the N-type silicon nitride below when preparing the contact hole 170. + Perform blocking protection to avoid N + The problem of being removed when preparing the contact hole 170. In addition, the preparation of the contact hole 170 between the small-sized trenches 130 is facilitated, thereby improving the preparation yield of the semiconductor device.

[0086] Through the description of the specific implementation methods, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose should be obtained. However, the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.

Claims

1. A method for preparing a semiconductor surface slot, characterized in that: include: S101, coating an organic carbon layer on a silicon substrate; S102, preparing a first protective portion on a side wall of the organic carbon layer; S103, preparing an organic carbon protective portion on the outer surface of the first protective portion; S104, etching to prepare a groove under the protection of the organic carbon protective portion; S105, removing the organic carbon layer and the organic carbon protection portion; S106, performing a high-temperature oxidation process on the silicon substrate to form an oxide layer; S107, filling the trench with polysilicon; S108, injecting N into the silicon base + ; S109, preparing an ILD layer on the silicon substrate surface; S110, preparing a second protective portion and a metal hole near the position of the first protective portion; S111 , filling the metal hole with metal under the protection of the second protective portion.

2. The method for preparing a semiconductor surface slot according to claim 1, wherein: In step S105 , the organic carbon layer and the organic carbon protection portion are removed by etching with oxygen-containing plasma.

3. The method for preparing a semiconductor surface slot according to claim 1, wherein: In step S108, the N + When the ion implantation device is used with different preset tilt angles, the implantation is performed multiple times, or the ion implantation device is set to a preset tilt angle, and the N + injection.

4. The method for preparing a semiconductor surface slot according to claim 1, wherein: There are multiple groups of the first guarding parts, each group of the first guarding parts includes two first guarding parts that are spaced apart, and the groove is prepared by etching between two adjacent first guarding parts in each group.

5. The method for preparing semiconductor surface slots according to claim 1, wherein: Two second protection parts are arranged at intervals between two adjacent grooves, and the metal hole is prepared by etching between the two adjacent second protection parts.

6. The method for preparing a semiconductor surface slot according to claim 1, wherein: In step S110, a metal hole is first prepared at a position adjacent to the first protective part, and then the second protective part is prepared on the inner wall of the metal hole; or a partial segment of the metal hole is first prepared at a position adjacent to the first protective part, and after the second protective part is prepared on the inner wall of the partial segment, the remaining part of the metal hole is prepared.

7. The method for preparing semiconductor surface slots according to claim 1, wherein: The first protection portion and the second protection portion are silicon nitride protection portions.

8. The method for preparing semiconductor surface slots according to claim 1, wherein: The distance between the two grooves on both sides of the metal hole is not less than the inner diameter of the contact hole.

9. A process for preparing an IGBT device, characterized in that: The manufacturing process of the IGBT device adopts the method for manufacturing semiconductor surface grooves according to any one of claims 1 to 8 to manufacture surface grooves of the IGBT.

10. The process for preparing an IGBT device according to claim 9, wherein: The manufacturing process of the IGBT device adopts the method for manufacturing a semiconductor surface slot according to any one of claims 1 to 8 to manufacture the metal holes on the surface of the IGBT.

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