Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate comprising a first surface and a second surface disposed opposite each other, with a device layer formed on the second surface; at least one groove is formed between the first and second surfaces, the groove being used to accommodate a coolant. According to the semiconductor device and method for manufacturing the same, a groove for accommodating a coolant is formed within the semiconductor substrate, utilizing in-chip water cooling to reduce the core temperature of the chip, improve the chip's heat dissipation, and thereby enhance the chip's peak power and performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As chip integration and transistor density increase, the power consumption per unit area of the chip also increases. Traditional chip cooling technology uses good thermal conductors, such as metal components like copper and aluminum, to conduct heat generated by the chip to a heat sink. This heat is then exchanged with the heat sink using flowing low-temperature air or coolant to control the chip temperature.

[0003] However, the heat conduction distance from the chip's transistors to the heat sink is long, resulting in a significant temperature difference between the transistor's core temperature and the heat sink's temperature. This temperature difference increases as the chip's power density increases. Traditional cooling technologies using air cooling and external water cooling are gradually failing to meet the cooling needs of new high-performance chips and their systems. Chip heat dissipation has become one of the main factors limiting chip performance. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] The present invention provides a semiconductor device, comprising:

[0006] a semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein a device layer is formed on the second surface;

[0007] At least one groove is formed between the first surface and the second surface, and the groove is used to accommodate cooling liquid.

[0008] Furthermore, a support structure is formed between the first surface and the second surface, the groove is an internally connected integral structure, and the support structure is located in the groove.

[0009] Furthermore, the semiconductor device further includes: a water inlet and a water outlet, wherein the water inlet and the water outlet are connected to the groove.

[0010] Furthermore, the device layer is bonded to the packaging substrate via a welding ring, and the water inlet and the water outlet are arranged at the junction of the device layer and the packaging substrate.

[0011] Furthermore, one or more pipes are formed in the packaging substrate, and the water inlet and the water outlet are respectively connected to the one or more pipes.

[0012] The present invention also provides a method for manufacturing a semiconductor device, comprising the steps of:

[0013] Providing a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other, a device layer formed on the second surface;

[0014] etching the first surface to form a recess in the first semiconductor substrate;

[0015] A second semiconductor substrate is bonded onto the first surface of the first semiconductor substrate to cover the groove, wherein the groove is used to accommodate a cooling liquid.

[0016] Furthermore, the forming of the groove in the first semiconductor substrate includes the steps of: forming a patterned photoresist layer on the first semiconductor substrate, etching the first semiconductor substrate using the patterned photoresist layer as a mask to form the groove and the support structure, and then removing the photoresist layer;

[0017] The groove is an internally connected integral structure, and the supporting structure is located in the groove.

[0018] Furthermore, after forming the groove in the first semiconductor substrate, the method further includes: continuing to etch the first semiconductor substrate to form a water inlet and a water outlet on the second surface, wherein the water inlet and the water outlet are connected to the groove.

[0019] Furthermore, the method further comprises:

[0020] providing a packaging substrate having one or more channels formed therein;

[0021] The packaging substrate is bonded to the device layer such that the water inlet and the water outlet are respectively connected to the one or more pipes.

[0022] Furthermore, the packaging substrate is bonded to the device layer via a welding ring to connect the groove and the one or more channels.

[0023] According to the semiconductor device and its manufacturing method provided by the present invention, a groove for accommodating coolant is formed in the semiconductor substrate, and a water cooling method is used inside the chip to reduce the core temperature of the chip and improve the heat dissipation effect of the chip, thereby improving the peak power and performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0025] In the attached figure:

[0026] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention;

[0027] Figures 2A-2D 1 and 2 are schematic cross-sectional views of devices obtained by sequentially implementing the steps of a method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0028] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0029] It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0030] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0031] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0033] In order to fully understand the present invention, detailed steps and detailed structures will be provided in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0034] Since traditional heat dissipation technologies using air cooling and external water cooling can no longer meet the heat dissipation needs of high-performance chips and their systems, the present invention provides a semiconductor device comprising:

[0035] a semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein a device layer is formed on the second surface;

[0036] At least one groove is formed between the first surface and the second surface, and the groove is used to accommodate cooling liquid.

[0037] A support structure is formed between the first surface and the second surface, the groove is an internally connected integral structure, and the support structure is located in the groove; the semiconductor device also includes: a water inlet and a water outlet, the water inlet and the water outlet are connected to the groove; the device layer is joined to the packaging substrate through a welding ring, and the water inlet and the water outlet are arranged at the junction of the device layer and the packaging substrate; one or more pipes are formed in the packaging substrate, and the water inlet and the water outlet are respectively connected to the one or more pipes.

[0038] According to the semiconductor device provided by the present invention, a groove for accommodating coolant is formed in the semiconductor substrate, and a water cooling method is used inside the chip to reduce the core temperature of the chip, improve the heat dissipation effect of the chip, and thus improve the peak power and performance of the chip.

[0039] [Example 1]

[0040] Reference below Figure 1 and Figures 2A-2D ,in Figure 1 1 is a schematic flow chart showing a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. Figures 2A-2D Schematic cross-sectional views of devices obtained by sequentially implementing steps of a method according to an exemplary embodiment of the present invention are shown.

[0041] The present invention provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, the main steps of the preparation method include:

[0042] Step S101: providing a first semiconductor substrate, wherein the first semiconductor substrate comprises a first surface and a second surface opposite to each other, wherein a device layer is formed on the second surface;

[0043] Step S102: etching the first surface to form a groove in the first semiconductor substrate;

[0044] Step S103 : bonding a second semiconductor substrate onto the first surface of the first semiconductor substrate to cover the groove, wherein the groove is used to accommodate a cooling liquid.

[0045] Next, a specific embodiment of the method for manufacturing a semiconductor device of the present invention is described in detail.

[0046] First, execute step S101, as Figure 2A As shown, a first semiconductor substrate 200 is provided. The first semiconductor substrate 200 includes a first surface 200A and a second surface 200B opposite to each other. A device layer 210 is formed on the second surface 200B.

[0047] In one embodiment, the first semiconductor substrate 200 may be made of at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, the first semiconductor substrate 200 is made of single crystal silicon.

[0048] In one embodiment, the device layer 210 includes multiple chips. It should be noted that the process of forming the device layer 210 can be placed before or after the process of forming the groove. Considering that the device layer 210 requires the first semiconductor substrate 200 as support during its formation, it is preferably placed before the process of forming the groove.

[0049] Next, execute step S102, as shown in FIG. Figure 2B As shown, the first surface 200A is etched to form a groove 220 in the first semiconductor substrate 200 .

[0050] Exemplarily, a support structure is formed between the first surface 200A and the second surface 200B.

[0051] In one embodiment, the support structure includes a first support structure 231 , which includes a portion of the first semiconductor substrate 200 located around the groove 220 and surrounding the groove 220 . The first support structure 231 is located between the first surface 200A and the second surface 200B and can play a supporting role.

[0052] Preferably, the support structure further includes a second support structure 232. The second support structure 232 is located within the groove 220 and is supported between the first surface 200A and the second surface 200B in the form of a column. The groove 220 is an internally connected integral structure, and the provision of the second support structure 232 does not affect the circulation of the coolant within the groove 220. It should be noted that the cross-sectional shape of the second support structure 232 includes, but is not limited to, circular, square, rectangular, or a combination thereof.

[0053] Exemplarily, the forming of the groove 220 in the first semiconductor substrate 200 includes the following steps:

[0054] forming a patterned photoresist layer on the first semiconductor substrate 200;

[0055] Etching the first semiconductor substrate 200 using the patterned photoresist layer as a mask to form the groove 220 and the support structure;

[0056] The photoresist layer is removed.

[0057] In one embodiment, the patterned photoresist layer may be formed by a spin coating process, followed by exposure, development, cleaning, and other processes.

[0058] In one embodiment, etching the first semiconductor substrate 200 can be performed using any conventional technique known to those skilled in the art, including wet etching and dry etching. Exemplarily, dry etching processes include, but are not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination thereof. A single etching method or more than one etching method may be used, and the present invention is not limited thereto.

[0059] In one embodiment, a cleaning process and / or an ashing process are performed to completely remove the photoresist layer. The cleaning process and the ashing process steps may be repeated multiple times.

[0060] Further, refer to Figure 2C As shown, the first semiconductor substrate 200 is further etched to form a water inlet and a water outlet on the second surface 200B, wherein the water inlet and the water outlet are connected to the groove 220 .

[0061] It should be noted that the water inlet and the water outlet can be formed on the first surface 200A, the second surface 200B or the first supporting structure 231 around the groove 220. By forming the water inlet and the water outlet on the second surface 200B and further connecting them with one or more pipes in the subsequent packaging substrate, the chip packaged on the packaging substrate can be made more stable.

[0062] Next, execute step S103, as shown in FIG. Figure 2C As shown, a second semiconductor substrate 240 is bonded onto the first surface 200A of the first semiconductor substrate 200 to cover the groove 220 , and the groove 220 is used to accommodate a cooling liquid.

[0063] In one embodiment, the second semiconductor substrate 240 may be made of at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Preferably, the second semiconductor substrate 240 is made of the same material as the first semiconductor substrate 200.

[0064] In one embodiment, the cooling liquid includes industrial water. It should be noted that the cooling liquid can also be any organic solution or inorganic solution as needed.

[0065] Further, if Figure 2DAs shown, the steps include:

[0066] Providing a packaging substrate 250 , wherein one or more channels 260 are formed in the packaging substrate 250 ;

[0067] The packaging substrate 250 is bonded to the device layer 210 so that the water inlet and the water outlet are connected to the one or more pipes 260 , respectively.

[0068] In one embodiment, package substrate 250 may be an epoxy-based laminate substrate, or may be other suitable types of substrates, including, for example, substrates formed of glass, ceramic, or semiconductor materials.

[0069] In one embodiment, forming one or more channels 260 in the package substrate 250 includes the following steps:

[0070] Providing a first packaging substrate, wherein the first packaging substrate includes a third surface and a fourth surface opposite to each other, wherein the third surface is bonded to the device layer 210;

[0071] Etching the fourth surface to form one or more pipes 260 in the first packaging substrate, wherein the water inlet and the water outlet are respectively connected to the one or more pipes 260;

[0072] A second packaging substrate is bonded onto the fourth surface of the first packaging substrate to cover the one or more channels 260 .

[0073] Illustratively, the package substrate 250 is bonded to the device layer 210 via a welding ring 270 to connect the groove 220 and the one or more channels 260 .

[0074] At this point, the process steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention have been completed. It can be understood that the method for manufacturing a semiconductor device in this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0075] According to the method for manufacturing a semiconductor device provided by the present invention, a groove for accommodating a coolant is formed in a semiconductor substrate, and a water cooling method is used within the chip to reduce the core temperature of the chip, improve the heat dissipation effect of the chip, and thereby improve the peak power and performance of the chip.

[0076] [Example 2]

[0077] The following is combined with Figure 2D , describing the structure of the semiconductor device provided by an embodiment of the present invention, including:

[0078] A semiconductor substrate 200, comprising a first surface 200A and a second surface 200B opposite to each other, wherein a device layer 210 is formed on the second surface 200B;

[0079] At least one groove 220 is formed between the first surface 200A and the second surface 200B. The groove 220 is used to accommodate cooling liquid.

[0080] In one embodiment, the semiconductor substrate 200 may be made of at least one of the following materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, the semiconductor substrate 200 is made of single crystal silicon.

[0081] Exemplarily, the device layer 210 includes a plurality of chips.

[0082] Exemplarily, a support structure is formed between the first surface 200A and the second surface 200B.

[0083] In one embodiment, the support structure includes a first support structure 231 , which includes a portion of the semiconductor substrate 200 located around the groove 220 and surrounding the groove 220 . The first support structure 231 is located between the first surface 200A and the second surface 200B and can play a supporting role.

[0084] Preferably, the support structure further includes a second support structure 232. The second support structure 232 is located within the groove 220 and is supported between the first surface 200A and the second surface 200B in the form of a column. The groove 220 is an internally connected integral structure, and the provision of the second support structure 232 does not affect the circulation of the coolant within the groove 220. It should be noted that the cross-sectional shape of the second support structure 232 includes, but is not limited to, circular, square, rectangular, or a combination thereof.

[0085] Exemplarily, the semiconductor device further includes a water inlet and a water outlet, wherein the water inlet and the water outlet are connected to the groove 220 .

[0086] In one embodiment, the cooling liquid includes industrial water. It should be noted that the cooling liquid can also be any organic solution or inorganic solution as needed.

[0087] Exemplarily, the device layer 210 is bonded to the package substrate 250 via a welding ring 270 , and the water inlet and the water outlet are provided at the junction between the device layer 210 and the package substrate 250 .

[0088] In one embodiment, package substrate 250 may be an epoxy-based laminate substrate, or may be other suitable types of substrates, including, for example, substrates formed of glass, ceramic, or semiconductor materials.

[0089] Furthermore, one or more pipes 260 are formed in the packaging substrate 250 , and the water inlet and the water outlet are respectively connected to the one or more pipes 260 .

[0090] According to the semiconductor device provided by the present invention, a groove for accommodating coolant is formed in the semiconductor substrate, and a water cooling method is used inside the chip to reduce the core temperature of the chip, improve the heat dissipation effect of the chip, and thus improve the peak power and performance of the chip.

[0091] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other, a device layer formed on the second surface; At least one groove is formed between the first surface and the second surface, and the groove is used to accommodate a cooling liquid; the groove is located on one side of the first surface of the first semiconductor substrate; a water inlet and a water outlet, wherein the water inlet and the water outlet are formed on one side of the second surface of the first semiconductor substrate and in the device layer, and the water inlet and the water outlet are connected to the groove; a second semiconductor substrate bonded to the first surface of the first semiconductor substrate and covering the groove; a packaging substrate, the packaging substrate being bonded to the device layer, the water inlet and the water outlet being provided at a junction of the device layer and the packaging substrate; One or more pipes are formed in the packaging substrate, and the water inlet and the water outlet are respectively connected to the one or more pipes.

2. The semiconductor device according to claim 1, wherein A supporting structure is formed between the first surface and the second surface. The groove is an internally connected integral structure, and the supporting structure is located in the groove.

3. The semiconductor device according to claim 1, wherein The device layer is bonded to the package substrate via solder rings.

4. A method for manufacturing a semiconductor device, characterized in that: Including steps: Providing a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other, a device layer formed on the second surface; etching the first surface to form a groove in the first semiconductor substrate, wherein the groove is located on one side of the first surface of the first semiconductor substrate; Etching the device layer and the first semiconductor substrate to form a water inlet and a water outlet on one side of the second surface of the first semiconductor substrate and in the device layer, wherein the water inlet and the water outlet are connected to the groove; bonding a second semiconductor substrate on the first surface of the first semiconductor substrate to cover the groove, wherein the groove is used to accommodate a cooling liquid; A packaging substrate is bonded to the device layer, wherein the water inlet and the water outlet are provided at the junction of the device layer and the packaging substrate; One or more pipes are formed in the packaging substrate. After the packaging substrate is bonded to the device layer, the water inlet and the water outlet are respectively connected to the one or more pipes.

5. The method according to claim 4, wherein Forming the groove in the first semiconductor substrate comprises the steps of: forming a patterned photoresist layer on the first semiconductor substrate, etching the first semiconductor substrate using the patterned photoresist layer as a mask to form the groove and the support structure, and then removing the photoresist layer; The groove is an internally connected integral structure, and the supporting structure is located in the groove.

6. The method according to claim 4, wherein The package substrate is bonded to the device layer via a welding ring to connect the groove and the one or more channels.

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