Controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path

Abstract

The present invention provides a controllable low trigger voltage silicon controlled rectifier structure with a uniform conduction path, comprising a P-type substrate, on which adjacent N-wells and P-wells are formed; the N-well is provided with a first and a second shallow trench isolations which are spaced in sequence, a first N-type ion implantation layer is formed between the first and the second shallow trench isolations, and a first gate, a first and a second P-type ion implantation layer are formed on one side of the second shallow trench isolation; the P-well is provided with a third and a fourth shallow trench isolations which are spaced in sequence, a third P-type ion implantation layer is formed between the third and the fourth shallow trench isolations; a fifth shallow trench isolation is provided between the second P-type ion implantation layer and the second N-type ion implantation layer, so that the second P-type ion implantation layer and the second N-type ion implantation layer are adjacent to each other and cross the junction of the N-well and the P-well in half. The present invention can reduce the trigger voltage; increase the sustaining voltage; and adjust the trigger voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a controllable low trigger voltage silicon-controlled rectifier structure with a uniform conduction path. Background Art

[0002] As the manufacturing process continues to shrink, the thickness of the gate oxide layer of the transistor is getting thinner and thinner, and the gate oxide breakdown voltage and operating voltage are constantly decreasing. In addition, the rate of decrease of the chip operating voltage is lower than the rate of decrease of the gate oxide breakdown voltage and the source-drain breakdown voltage of the transistor. Therefore, when performing ESD (low capacitance electrostatic) design, a 10% safety margin must be considered, resulting in the ESD design window becoming narrower and narrower, and the available ESD solutions are extremely limited. The silicon-controlled rectifier (SCR) is the most robust ESD protection device per unit area, and can be regarded as a positive feedback loop composed of two parasitic transistors PNP and NPN. Its IV (current-voltage) characteristics show obvious hysteresis characteristics, and the holding voltage is often very low, which is very easy to cause latch-up effect.

[0003] GGNMOS (grounded NMOS tube) is triggered by N ion implantation and the junction breakdown voltage of the P well, and has a relatively low trigger voltage. Studies have shown that embedding GGNMOS into SCR can effectively reduce the trigger voltage, and this new structure is named low trigger voltage silicon controlled rectifier containing GGNMOS (NLVTSCR). GGNMOS accelerates the triggering process of SCR, but the strong hysteresis of SCR causes the maintenance voltage of LVTSCR to be still very low, facing a high risk of latch-up. Similarly, by embedding GDPMOS (Gate-to-Drain PMOS, gate-to-drain PMOS) in the SCR structure, a low trigger voltage silicon controlled rectifier containing PMOS (PLVTSCR) was developed. The crossover region in the SCR provides an ESD shunt path, which can reduce the ESD current of the parasitic SCR path in the body, thereby increasing the maintenance voltage of the MLSCR (modulated lateral silicon controlled rectifier), but the trigger voltage of the MLSCR may be higher than the breakdown voltage of the gate oxide under low voltage operation, which is still not enough to protect the internal circuit from failure.

[0004] In order to solve the above problems, a new type of silicon-controlled rectifier structure with high holding voltage and low trigger voltage is needed. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a controllable low trigger voltage silicon-controlled rectifier structure with a uniform conduction path, which is used to solve the problem that the current-voltage characteristics of the silicon-controlled rectifier in the prior art show obvious hysteresis characteristics, the holding voltage is often very low, and it is very easy to cause a latch effect.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a controllable low trigger voltage silicon-controlled rectifier structure with a uniform conduction path, comprising:

[0007] A P-type substrate having an N-well and a P-well adjacent to each other formed thereon;

[0008] The N-well is provided with a first shallow trench isolation and a second shallow trench isolation which are sequentially spaced apart, a first N-type ion implantation layer is formed between the first shallow trench isolation and the second shallow trench isolation, a first gate and a first P-type ion implantation layer and a second P-type ion implantation layer which are respectively arranged on both sides of the first gate are formed on the side of the second shallow trench isolation away from the first N-type ion implantation layer, one side of the second P-type ion implantation layer 11 is an irregular structure, so that a part of the second P-type ion implantation layer spans the boundary between the N-well and the P-well, and another part of the second P-type ion implantation layer is located in the N-well;

[0009] A first connection structure connecting the first N-type ion implantation layer, the first P-type ion implantation layer and the first gate is provided on the first N-type ion implantation layer, the first P-type ion implantation layer and the first gate, and is used to lead out the anode;

[0010] The P-well is provided with a third shallow trench isolation and a fourth shallow trench isolation which are distributed in sequence, a third P-type ion implantation layer is formed between the third shallow trench isolation and the fourth shallow trench isolation, a second gate and a second N-type ion implantation layer and a third N-type ion implantation layer which are respectively arranged on both sides of the second gate are formed on the side of the third shallow trench isolation away from the third P-type ion implantation layer, the second N-type ion implantation layer 12 is an irregular structure on the side close to the second P-type ion implantation layer 11, and the structures on both sides close to the two are cross-distributed, so that a part of the second N-type ion implantation layer spans the junction of the N-well and the P-well, and another part of the second N-type ion implantation layer is located in the P-well;

[0011] A fifth shallow trench isolation is provided between the second P-type ion implantation layer and the second N-type ion implantation layer;

[0012] A second connection structure connecting the second gate, the third N-type ion implantation layer and the third P-type ion implantation layer is provided on the second gate, the third N-type ion implantation layer and the third P-type ion implantation layer, and is used to lead out a cathode.

[0013] Preferably, the P-type substrate is a silicon substrate.

[0014] Preferably, the adjacent sides of the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12 respectively cross and cross the boundary between the N-well 02 and the P-well 03 in half.

[0015] Preferably, the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12 are close to each other and are respectively a plurality of cross-distributed rectangular structures. Preferably, the ions doped in the N-well are boron ions.

[0016] Preferably, the ions doped in the P-well are phosphorus ions.

[0017] Preferably, the ions doped in the first N-type ion implantation layer, the second N-type ion implantation layer, and the third N-type ion implantation layer are all arsenic ions.

[0018] Preferably, the ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer, and the third P-type ion implantation layer are all boron ions.

[0019] Preferably, the gate is made of doped polysilicon.

[0020] As described above, the controllable low trigger voltage silicon-controlled rectifier structure with a uniform conduction path of the present invention has the following beneficial effects:

[0021] The adjustable holding voltage silicon-controlled rectifier structure of the present invention can reduce the trigger voltage through two trigger points of GGNMOS or GDPMOS; GGNMOS and GDPMOS can be used as current release paths to shunt ESD current after the device is turned on, thereby reducing the ESD current in the SCR body and increasing the holding voltage; the trigger voltage can be adjusted by adjusting the structure of GGNMOS or GDPMOS; and the surface shunt level can also be set by changing the GGNMOS and GDPMOS structures separately or simultaneously, so as to achieve the purpose of regulating the holding voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a schematic diagram of the three-dimensional structure of a silicon-controlled rectifier of the present invention;

[0023] Figure 2 Shown is a cross-sectional view of the silicon-controlled rectifier structure of the present invention on the A side and a schematic diagram of a low-capacitance electrostatic current path;

[0024] Figure 3 Shown is a cross-sectional view of the silicon-controlled rectifier structure on side B of the present invention and a schematic diagram of a low-capacitance electrostatic current path.

[0025] Reference numerals:

[0026] P-type substrate-01

[0027] N-well-02

[0028] P-well-03

[0029] First shallow trench isolation-04

[0030] Second shallow trench isolation-05

[0031] First Gate-06

[0032] The third shallow trench isolation-07

[0033] Fourth Shallow Trench Isolation-08

[0034] The first N-type ion implantation layer-09

[0035] The first P-type ion implantation layer-10

[0036] The second P-type ion implantation layer-11

[0037] The second N-type ion implantation layer-12

[0038] Second Gate-13

[0039] The third N-type ion implantation layer-14

[0040] The third P-type ion implantation layer-15

[0041] First connection structure-16

[0042] Second connection structure-17

[0043] Fifth shallow trench isolation-18 DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] See also Figure 1 The present invention provides a controllable low trigger voltage silicon-controlled rectifier structure with a uniform conduction path, comprising:

[0046] A P-type substrate 01, on which adjacent N-well 02 and P-well 03 are formed;

[0047] In an embodiment of the present invention, the P-type substrate 01 is a silicon substrate, and an N-well 02 and a P-well 03 can be first formed on the silicon substrate by ion implantation, and then a groove for forming a shallow trench isolation (STI) is formed on the substrate by photolithography and etching, and then a shallow trench isolation structure is formed in the groove by depositing insulating material and grinding.

[0048] The N-well 02 is provided with a first shallow trench isolation 04 and a second shallow trench isolation 05 which are distributed in sequence. The shallow trench isolation is usually made of insulating material, such as silicon dioxide. A first N-type ion implantation layer 09 is formed between the first shallow trench isolation 04 and the second shallow trench isolation 05. A first gate 06 and a first P-type ion implantation layer 10 and a second P-type ion implantation layer 11 which are respectively arranged on both sides of the first gate 06 are formed on the side of the second shallow trench isolation 05 away from the first N-type ion implantation layer 09. One side of the second P-type ion implantation layer 11 is an irregular structure, so that a part of the second P-type ion implantation layer 11 spans the boundary between the N-well 02 and the P-well 03, and another part of the second P-type ion implantation layer 11 is located in the N-well 02.

[0049] A first connection structure 16 connecting the first N-type ion implantation layer 09, the first P-type ion implantation layer 10 and the first gate 06 is provided to connect the three and is used to lead out the anode;

[0050] In the embodiment of the present invention, after the device is manufactured by the front-end process, the devices are interconnected by the back-end process to form the first connection structure 16. Specifically, an interlayer dielectric layer can be deposited on the device after the ion implantation by chemical vapor deposition, and the material of the interlayer dielectric layer can be silicon dioxide, and then the interlayer dielectric layer is etched to form a contact hole connected to the first N-type ion implantation layer 09, the first P-type ion implantation layer 10 and the first gate 06, and then the contact hole is filled with a conductive material, and the filling material is tungsten (W), and the interconnection is Al.

[0051] A third shallow trench isolation 07 and a fourth shallow trench isolation 08 are arranged on the P-well 03, and a third P-type ion implantation layer 15 is formed between the third shallow trench isolation 07 and the fourth shallow trench isolation 08. A second gate 13 and a second N-type ion implantation layer 12 and a third N-type ion implantation layer 14 are respectively arranged on both sides of the second gate 13, and a side of the second N-type ion implantation layer 12 close to the second P-type ion implantation layer 11 is an irregular structure, and the structures on both sides close to the two are cross-distributed, so that a part of the second N-type ion implantation layer 12 spans the junction of the N-well 02 and the P-well 03, and another part of the second N-type ion implantation layer 12 is located in the P-well 03;

[0052] A fifth shallow trench isolation 18 is provided between the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12;

[0053] In the embodiment of the present invention, the adjacent sides of the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12 cross and cross the boundary between the N-well 02 and the P-well 03 in half.

[0054] In the embodiment of the present invention, the second P-type ion implantation layer 11 and the second N-type ion implantation layer 12 are close to each other and are respectively formed of a plurality of cross-distributed rectangular structures.

[0055] A second connection structure 17 connecting the second gate 13, the third N-type ion implantation layer 14 and the third P-type ion implantation layer 15 is provided for leading out the cathode, that is, GGNMOS is introduced into the traditional SCR structure to design NLVTSCR, GDPMOS is introduced into the traditional SCR structure to design PLVTSCR, GGNMOS and GDPMOS are embedded into LVTSCR, and the source region of GDPMOS and the drain region of GGNMOS are respectively half-crossed across the junction of Nwell and Pwell to design a LVTSCR structure.

[0056] In the embodiment of the present invention, after the device is manufactured by the front-end process, the devices are interconnected by the back-end process to form the second connection structure 17. Specifically, an interlayer dielectric layer can be deposited on the device after the ion implantation by chemical vapor deposition, and the material of the interlayer dielectric layer can be silicon dioxide, and then the interlayer dielectric layer is etched to form a contact hole connected to the second gate 13, the third N-type ion implantation layer 14 and the third P-type ion implantation layer 15, and then the contact hole is filled with a conductive material, and the filling material is tungsten (W), and the interconnection is Al.

[0057] See also Figure 2 In the embodiment of the present invention, the structure at the A surface forms a structure similar to the existing PLVTSCR structure and ESD current path.

[0058] See also Figure 3 In the embodiment of the present invention, the structure at the B surface forms a structure and an ESD current path similar to the existing NLVTSCR structure.

[0059] That is to say, in the embodiments of the present invention, GGNMOS is introduced into the SCR structure to design NLVTSCR; GDPMOS is introduced into the traditional SCR structure to design PLVTSCR; GGNMOS and GDPMOS are embedded into the LVTSCR, and the source region of GDPMOS and the drain region of GGNMOS are respectively crossed in half across the junction of Nwell and Pwell to design the LVTSCR structure.

[0060] In an embodiment of the present invention, the ions doped in the N-well 02 are boron ions.

[0061] In the embodiment of the present invention, the ions doped in the P-well 03 are phosphorus ions.

[0062] In the embodiment of the present invention, the ions doped in the first N-type ion implantation layer 09 , the second N-type ion implantation layer 12 , and the third N-type ion implantation layer 14 are all arsenic ions.

[0063] In the embodiment of the present invention, the ions doped in the first P-type ion implantation layer 10 , the second P-type ion implantation layer 11 , and the third P-type ion implantation layer 15 are all boron ions.

[0064] In an embodiment of the present invention, the material of the gate is doped polysilicon.

[0065] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0066] In summary, the adjustable holding voltage silicon controlled rectifier structure of the present invention can reduce the trigger voltage through two trigger points of GGNMOS or GDPMOS; GGNMOS and GDPMOS can be used as current release paths to shunt ESD current after the device is turned on, thereby reducing the ESD current in the SCR body and increasing the holding voltage; the trigger voltage can be adjusted by adjusting the structure of GGNMOS or GDPMOS; and the surface shunt level can also be set by changing the structure of GGNMOS and GDPMOS separately or simultaneously, so as to achieve the purpose of regulating the holding voltage. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A controllable low trigger voltage silicon controlled rectifier structure with a uniform conduction path, characterized in that: include: A P-type substrate having an N-well and a P-well adjacent to each other formed thereon; The N-well is provided with a first shallow trench isolation and a second shallow trench isolation which are sequentially spaced apart, a first N-type ion implantation layer is formed between the first shallow trench isolation and the second shallow trench isolation, a first gate and a first P-type ion implantation layer and a second P-type ion implantation layer which are respectively provided on both sides of the first gate are formed on the side of the second shallow trench isolation away from the first N-type ion implantation layer, one side of the second P-type ion implantation layer is an irregular structure, so that a part of the second P-type ion implantation layer spans the boundary between the N-well and the P-well, and another part of the second P-type ion implantation layer is located in the N-well; A first connection structure connecting the first N-type ion implantation layer, the first P-type ion implantation layer and the first gate is provided on the first N-type ion implantation layer, the first P-type ion implantation layer and the first gate, and is used to lead out the anode; The P-well is provided with a third shallow trench isolation and a fourth shallow trench isolation which are distributed in sequence, a third P-type ion implantation layer is formed between the third shallow trench isolation and the fourth shallow trench isolation, a second gate and a second N-type ion implantation layer and a third N-type ion implantation layer which are respectively arranged on both sides of the second gate are formed on the side of the third shallow trench isolation away from the third P-type ion implantation layer, a side of the second N-type ion implantation layer close to the second P-type ion implantation layer is an irregular structure, and the structures on both sides close to the two are cross-distributed, so that a part of the second N-type ion implantation layer spans the boundary between the N-well and the P-well, and another part of the second N-type ion implantation layer is located in the P-well; A fifth shallow trench isolation is provided between the second P-type ion implantation layer and the second N-type ion implantation layer; A second connection structure connecting the second gate, the third N-type ion implantation layer and the third P-type ion implantation layer is provided on the second gate, the third N-type ion implantation layer and the third P-type ion implantation layer, and is used to lead out a cathode.

2. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The P-type substrate is a silicon substrate.

3. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The adjacent sides of the second P-type ion implantation layer and the second N-type ion implantation layer cross and halfway across the boundary between the N-well and the P-well.

4. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 3, characterized in that: The second P-type ion implantation layer and the second N-type ion implantation layer are close to each other and are respectively formed of a plurality of cross-distributed rectangular structures.

5. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The ions doped in the N-well are boron ions.

6. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The ions doped in the P-well are phosphorus ions.

7. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The ions doped in the first N-type ion implantation layer, the second N-type ion implantation layer, and the third N-type ion implantation layer are all arsenic ions.

8. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The ions doped in the first P-type ion implantation layer, the second P-type ion implantation layer, and the third P-type ion implantation layer are all boron ions.

9. The controllable low trigger voltage silicon controlled rectifier structure with uniform conduction path according to claim 1, characterized in that: The materials of the first gate and the second gate are both doped polysilicon.

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