Asymmetric trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; performing ion implantation to form a freewheeling region; forming a barrier layer, etching, carrying out ion implantation, and forming a masking layer, a P-type well region and an N-type source region; re-forming a barrier layer, etching, etching the drift layer and the masking layer to form a groove, and oxidizing to form an insulating dielectric layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the follow current region, metal is deposited, and a source electrode metal layer is formed; according to the invention, the body diode conduction loss of the device can be effectively reduced, the reverse recovery speed of the device can be improved, and the gate reliability and the source large current impact reliability of the device can be improved.

Description

Technical Field

[0001] The invention relates to an asymmetric trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC) VDMOS (vertical double diffused metal-oxide-semiconductor field-effect transistor) is a typical representative of silicon carbide power devices. Due to its excellent performance, it has been widely used in many high-tech fields such as electric vehicles, aerospace, and power conversion. However, different application scenarios have different performance requirements for silicon carbide power VDMOS, but in general, its core requirements are mainly concentrated in the following aspects: 1. Lower on-resistance: In high-power applications, such as electric drive systems and power conversion equipment in electric vehicles, the on-resistance of the device is directly related to energy conversion efficiency and system heating. Lower on-resistance can significantly reduce energy loss during conduction and improve overall energy efficiency, thereby extending the range of electric vehicles or reducing the heat dissipation requirements of power conversion equipment.

[0003] 2. Faster switching speed: Fast switching capability is essential for high-frequency power electronic equipment. In the aerospace field, high-frequency switching power supplies and pulse power systems require fast response and high-precision control to achieve efficient energy distribution and conversion. The fast switching characteristics of silicon carbide VDMOS can effectively reduce switching losses and improve the dynamic performance and power density of the system.

[0004] 3. Higher reliability: Gate reliability: In complex working environments, such as high temperature, high humidity, and high voltage shock, gate reliability is a key factor affecting device life. The high thermal and chemical stability of silicon carbide materials enables its gate structure to remain stable under extreme conditions, thereby extending the service life of the device.

[0005] Drain voltage shock reliability: In power conversion systems, devices may be subjected to voltage spikes and transient shocks. The high voltage withstand characteristics and fast recovery capabilities of silicon carbide VDMOS enable it to withstand these shocks and reduce the risk of device damage caused by voltage overshoot.

[0006] 4. Lower body diode conduction loss: In many applications, such as electric vehicle motor drives and renewable energy conversion systems, the conduction loss of the body diode directly affects the overall efficiency of the system. Silicon carbide VDMOS effectively reduces the conduction loss of the body diode by optimizing the device structure, while increasing the reverse recovery speed and reducing the retention and loss of energy in the diode. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide an asymmetric trench gate silicon carbide VDMOS and a preparation method, which can effectively reduce the body diode conduction loss of the device, increase the reverse recovery speed of the device, and improve the gate reliability and source large current impact reliability of the device.

[0008] In a first aspect, the present invention provides a method for preparing an asymmetric trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; Step 2, injecting ions into the drift layer to form a freewheeling region; Step 3, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a masking layer; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer and the masking layer to form a groove, and oxidize to form an insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the freewheeling region, deposit metal to form a source metal layer; remove the barrier layer to complete the preparation.

[0009] In a second aspect, the present invention provides an asymmetric trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing an asymmetric trench gate silicon carbide VDMOS according to the first aspect.

[0010] The advantages of the present invention are: 1. The masking layer of the present invention wraps the area below the trench gate insulating dielectric layer, which can effectively improve the gate reliability of the device; Second, the masking layer of the present invention is also directly connected to the source metal layer, forming an ohmic contact with the source metal layer. The pn junction formed by the masking layer and the freewheeling region can effectively increase the body pn junction diode area of ​​the device and effectively improve the freewheeling capability of the body diode of the device; 3. The freewheeling region of the present invention is connected to the source metal layer on the left and right sides respectively, forming a Schottky diode between the source metal layer and the freewheeling region, which can effectively reduce the body diode conduction voltage drop of the device; 4. The cathode distribution position of the Schottky diode of the present invention is the same as that of the pn junction cathode, but the reverse recovery of the Schottky diode is faster and the on-state voltage drop is lower, so under normal circumstances the device has a fast recovery characteristic. In extreme cases, when the device has a large current from the source to the drain, the pn junction diode assists in conduction, which can effectively improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0012] Figure 1 The schematic diagram of an asymmetric trench gate silicon carbide VDMOS of the present invention.

[0013] Figure 2 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0014] Figure 3 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0015] Figure 4 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0016] Figure 5 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0017] Figure 6 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0018] Figure 7 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0019] Figure 8 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0020] Fig. 9 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0021] Fig.10 A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0022] Fig.11A cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the present invention Figure 10 . DETAILED DESCRIPTION

[0023] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0025] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0026] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0027] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing an asymmetric trench gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially growing on the silicon carbide substrate 1 to form a drift layer 2; Step 2, injecting ions into the drift layer 2 to form a freewheeling region 3, the ion injection energy is 100-400kev; Step 3, forming a barrier layer 8 on the drift layer 2, etching the barrier layer 8 to form a through hole, and performing ion implantation to form a masking layer 33, wherein the ion implantation energy is 100-330kev; Step 4, remove the original barrier layer, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation to form a P-type well region 31, with the ion implantation energy being 200-300kev; Step 5, removing the original barrier layer, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation to form an N-type source region 32, wherein the ion implantation energy is 100-200 keV; Step 6: remove the original barrier layer, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the drift layer 2 and the masking layer 33 to form a groove 34, and oxidize to form an insulating dielectric layer 4; Step 7, removing the original barrier layer, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing metal, and forming a gate metal layer 5; Step 8, remove the original barrier layer, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and etch the drift layer 2 to the upper side of the freewheeling region 3, deposit metal to form a source metal layer 6; remove the barrier layer 8, and complete the preparation.

[0029] In this embodiment, preferably, the width of the P-type well region 31 is greater than the width of the N-type source region 32 .

[0030] In this embodiment, preferably, the silicon carbide substrate 1 , the drift layer 2 and the freewheeling region 3 are all of N type, and the masking layer 33 is of P type.

[0031] In this embodiment, preferably, the upper side surfaces of the N-type source region 32 , the freewheeling region 3 and the shielding layer 33 are located in the same plane.

[0032] In this embodiment, preferably, the doping concentration of the freewheeling region 3 is greater than the doping concentration of the drift layer 2 .

[0033] In this embodiment, preferably, the doping concentration of the masking layer 33 is greater than the doping concentration of the freewheeling region 3 .

[0034] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1; A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; A freewheeling region 3, wherein the lower side of the freewheeling region 3 is connected to the upper side of the drift layer 2; a P-type well region 31, an N-type source region 32, a shielding layer 33 and a groove 34 are provided in the freewheeling region 3; the lower side of the N-type source region 32 is connected to the upper side of the P-type well region 31; the P-type well region 31 and the N-type source region 32 are located on one side of the groove 34; the shielding layer 33 is located below and on the other side of the groove 34; An insulating dielectric layer 4, wherein the lower portion of the insulating dielectric layer 4 is disposed in the groove 34, and the lower side surface of the insulating dielectric layer 4 is connected to the masking layer 33; the outer side surface of the insulating dielectric layer 4 is respectively connected to the N-type source region 32, the P-type well region 31 and the masking layer 33; and a groove 41 is disposed in the insulating dielectric layer 4; A gate metal layer 5, wherein the gate metal layer 5 is disposed in the groove 41; A source metal layer 6, wherein the source metal layer 6 is respectively connected to the freewheeling region 3, the N-type source region 31 and the shielding layer 33; and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the silicon carbide substrate 1 .

[0035] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2e18cm -3 , the doping concentration of the N-type drift layer 2 is 1e16cm -3 , the doping concentration of the N-type freewheeling region 3 is 1e17cm -3 , the doping concentration of the P-type shielding layer 33 is 1e18cm -3 , the doping concentration of the P-type well region 31 is 5e17 cm -3 The material of the insulating dielectric layer 4 can be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide. The doping concentration of the N-type source region 32 is 2e18cm -3; The doping concentration of the N-type silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 7, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the N-type freewheeling region 3 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 6, thereby forming a Schottky body diode inside the device; the doping concentration of the P-type shielding layer 33 is to suppress the electric field concentration at the gate corner of the device and the influence of the drain voltage shock on the gate of the device, the P-type shielding layer 33 forms an ohmic contact with the source metal layer 6, thereby forming a pn junction diode inside the device, and the doping concentration of the N-type source region 32 is to form an ohmic contact with the source metal layer 6 and reduce the contact resistance.

[0036] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 15-25 μm. The thickness is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the N-type freewheeling region 3 below the P-type shielding layer 33 is 200 nm, the thickness of the N-type freewheeling region 3 below the P-type well region 31 is 300 nm, and the thickness of the N-type freewheeling region 3 below the source metal layer 6 is 900 nm; the contact surface width between the N-type freewheeling region 3 on one side of the N-type source region 32 and the source metal layer 6 is 500 nm; the width of the N-type freewheeling region 3 next to the P-type well region 31 is 100 nm; the contact surface width between the N-type freewheeling region 3 on one side of the P-type shielding layer 33 and the source metal layer 6 is 200 nm, ensuring When a positive voltage is applied to the drain of the device, ensure that the region is a space charge region to ensure the turn-off characteristics of the device; the N-type freewheeling region 3 in the region below the P-type shielding layer 33 can effectively shield the capacitance effect of the gate on the drain, reduce the gate-drain charge of the device, increase the switching speed of the device and guide the carriers from one side of the device to other regions of the device at the same time, avoid current concentration inside the device, and reduce the on-resistance of the device; the thickness of the P-type shielding layer 33 below the insulating dielectric layer 4 is 100nm, in order to protect the gate of the device and suppress the breakdown problem caused by the electric field concentration at the corner of the gate, the bottom thickness of the insulating dielectric layer 4 is 50nm, the thickness of the N-type source region 32 is 300nm, and the thickness of the P-type well region 31 is 300nm; The P-type shielding layer 33 of the device is directly connected to the source metal layer 6, forming an ohmic contact with the source metal layer 6. The pn junction formed by the P-type shielding layer 3 and the N-type freewheeling region 3 can effectively increase the body pn junction diode area of ​​the device and effectively improve the freewheeling capability of the body diode of the device. The N-type freewheeling region 3 of the device is connected to the source metal layer 6 on the left and right sides respectively, forming a Schottky diode of the source metal layer 6 and the N-type freewheeling region 3, which can effectively reduce the conduction voltage drop of the body diode of the device. The cathode distribution position of the Schottky diode of the device is the same as that of the pn junction cathode, but the reverse recovery of the Schottky diode is faster and the conduction voltage drop is lower. Therefore, under normal circumstances, the device has a fast recovery characteristic. In extreme cases, when the device has a large current from the source to the drain, the pn junction diode assists in conduction, which can improve the source current freewheeling capability of the device. This structure can effectively improve the reliability of the large source current in the off state of the device.

[0037] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing an asymmetric trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the silicon carbide substrate to form a drift layer; Step 2, injecting ions into the drift layer to form a freewheeling region; Step 3, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a masking layer; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer and the masking layer to form a groove, and oxidize to form an insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the freewheeling region, deposit metal to form a source metal layer; remove the barrier layer to complete the preparation.

2. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the P-type well region is greater than the width of the N-type source region.

3. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate, drift layer and freewheeling region are all N-type, and the masking layer is P-type.

4. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The upper side surfaces of the N-type source region, the freewheeling region and the shielding layer are located in the same plane.

5. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the freewheeling region is greater than the doping concentration of the drift layer.

6. The method for preparing an asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the masking layer is greater than the doping concentration of the freewheeling region.

7. An asymmetric trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

Images