Method for manufacturing array substrate and array substrate

Abstract

This application discloses a method for fabricating an array substrate and the array substrate. The method includes providing a substrate; sequentially forming a first metal layer and a second metal layer on the substrate; forming a mask layer on the second metal layer; etching the first and second metal layers to form patterned first and second metal layers; removing the mask layer with a stripping solution to obtain a gate layer composed of the patterned first and second metal layers; introducing oxygen into a metal trench between the patterned first and second metal layers, and using ionized oxygen to ashed the residual stripping solution in the metal trench to remove the residual stripping solution. This application adds an ionized oxygen ashing process after removing the mask layer to remove residual stripping solution, reduce metal hollowing in the metal trench, avoid electrostatic discharge, and improve product quality.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a method for preparing an array substrate and the array substrate. Background Technology

[0002] With the continuous development of display technology, display panels such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED) are becoming increasingly popular. A display panel includes an array substrate, which in turn includes structures such as a gate layer.

[0003] In the prior art, the fabrication process of the gate layer includes a photoresist removal process. After the photoresist removal process is completed, some stripping solution will remain. The residual stripping solution will react with the metal in the gate layer in subsequent processes, causing metal hollowing. This can easily cause electron migration of the metal, resulting in electrostatic discharge and reducing product quality. Summary of the Invention

[0004] This application provides a method for preparing an array substrate and an array substrate, which removes residual stripping liquid, reduces the occurrence of metal hollowing in metal trenches, avoids electrostatic discharge, and improves product quality.

[0005] In a first aspect, embodiments of this application provide a method for fabricating an array substrate, comprising:

[0006] Provide a substrate;

[0007] A first metal layer and a second metal layer are sequentially formed on the substrate;

[0008] A mask layer is formed on the second metal layer;

[0009] The first metal layer and the second metal layer are etched to form a patterned first metal layer and a patterned second metal layer;

[0010] The mask layer is removed by a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer;

[0011] Oxygen is introduced into the metal trench between the patterned first metal layer and the patterned second metal layer, and the residual stripping liquid in the metal trench is ashed by the ionized oxygen to remove the residual stripping liquid in the metal trench.

[0012] Optionally, the step of introducing oxygen into the metal trench between the patterned first metal layer and the patterned second metal layer, and using ionized oxygen to ashing the residual stripping liquid in the metal trench to remove the residual stripping liquid, includes:

[0013] The amine in the stripping solution remaining in the metal trench between the patterned first metal layer and the patterned second metal layer reacts with the metal atoms in the patterned second metal layer to generate reaction products.

[0014] Oxygen is introduced into the metal trench;

[0015] Oxygen ions formed from oxygen ionized oxygen react with the reaction products to generate gas and water.

[0016] The gas and water are removed by vacuuming to eliminate the stripping fluid remaining in the metal trench.

[0017] Optionally, in some embodiments, the oxygen ions formed by the ionization treatment of oxygen react with the reaction products to generate gas and water, including:

[0018] The oxygen is ionized using a radio frequency power supply or a high-power power supply.

[0019] The oxygen ions formed by the ionization treatment react with the reaction products to generate gas and water, wherein the gas includes carbon dioxide and / or carbon monoxide.

[0020] Optionally, in some embodiments, forming a mask layer on the second metal layer includes:

[0021] A photoresist layer is formed on the second metal layer;

[0022] The photoresist layer is exposed and developed to form the mask layer.

[0023] Optionally, in some embodiments, etching the first metal layer and the second metal layer to form a patterned first metal layer and a patterned second metal layer includes:

[0024] The substrate, the first metal layer, the second metal layer, and the mask layer are immersed in a copper acid etching solution;

[0025] The first metal layer and the second metal layer are wet-etched using the copper acid etching solution to form the patterned first metal layer and the patterned second metal layer, wherein the orthographic projection area of ​​the patterned first metal layer on the substrate and the orthographic projection area of ​​the patterned second metal layer on the substrate are both located within the orthographic projection area of ​​the mask layer on the substrate.

[0026] Optionally, in some embodiments, removing the mask layer with a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer includes:

[0027] The photoresist in the mask layer is removed by a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer, wherein the orthogonal projection region of the patterned second metal layer on the substrate is located within the orthogonal projection region of the patterned first metal layer on the substrate.

[0028] Optionally, in some embodiments, the metal material in the first metal layer includes molybdenum, titanium, or a molybdenum-titanium alloy, and the metal material in the second metal layer includes copper or aluminum.

[0029] Optionally, in some embodiments, after oxygen is introduced into the metal trench between the patterned first metal layer and the patterned second metal layer, and the residual stripping liquid in the metal trench is ashed by ionized oxygen to remove the residual stripping liquid in the metal trench, the method further includes:

[0030] A gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the gate layer;

[0031] An active layer is formed on the gate insulating layer;

[0032] A source layer and a drain layer are formed on the active layer;

[0033] A passivation layer is formed on the gate insulating layer, wherein the passivation layer covers the active layer, the source layer and the drain layer.

[0034] Secondly, embodiments of this application also provide an array substrate, comprising:

[0035] Substrate;

[0036] A gate layer is disposed on the substrate;

[0037] A gate insulating layer is disposed on the substrate and covers the gate layer;

[0038] An active layer is disposed on the gate insulating layer;

[0039] Both the source layer and the drain layer are disposed on the active layer;

[0040] A passivation layer is disposed on the gate insulating layer and covers the active layer, the source layer and the drain layer.

[0041] Optionally, in some embodiments, the gate layer includes a first metal layer and a second metal layer, the first metal layer and the second metal layer are stacked, and the first metal layer is disposed between the substrate and the second metal layer, and the orthogonal projection area of ​​the second metal layer on the substrate is located within the orthogonal projection area of ​​the first metal layer on the substrate.

[0042] Optionally, in some embodiments, the metal material of the first metal layer includes molybdenum, titanium, or a molybdenum-titanium alloy, and the metal material of the second metal layer includes copper or aluminum.

[0043] The method for fabricating an array substrate provided in this application includes providing a substrate; sequentially forming a first metal layer and a second metal layer on the substrate; forming a mask layer on the second metal layer; etching the first and second metal layers to form a patterned first metal layer and a patterned second metal layer; removing the mask layer with a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer; introducing oxygen into a metal trench between the patterned first metal layer and the patterned second metal layer, and using ionized oxygen to ashed the residual stripping solution in the metal trench to remove the residual stripping solution. This application adds an ionized oxygen ashing process after removing the mask layer to remove residual stripping solution, reduce metal hollowing in the metal trench, avoid electrostatic discharge, and improve product quality. Attached Figure Description

[0044] The technical solution and its beneficial effects will become apparent from the following detailed description of specific embodiments of this application, in conjunction with the accompanying drawings.

[0045] Figure 1 This is a schematic flowchart of the method for fabricating an array substrate provided in an embodiment of this application.

[0046] Figure 2 This is a schematic diagram of the first intermediate product of the array substrate provided in the embodiments of this application.

[0047] Figure 3 This is a schematic diagram of the second intermediate product of the array substrate provided in the embodiments of this application.

[0048] Figure 4 This is a schematic diagram of the third intermediate product of the array substrate provided in the embodiments of this application.

[0049] Figure 5 This is a schematic diagram of the first structure of the array substrate provided in the embodiments of this application.

[0050] Figure 6 This is a schematic diagram of a second structure of the array substrate provided in the embodiments of this application. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] In the prior art, display panels include array substrates, which include structures such as gate layers. The fabrication process of the gate layer typically includes gate layer deposition, photoresist patterning, etching, and photoresist removal. The gate layer deposition process forms a film layer with a first metal layer and a second metal layer stacked together; the photoresist patterning process forms a patterned photoresist film layer disposed on the second metal layer; the etching process forms a gate layer composed of the patterned first metal layer and the patterned second metal layer; and the photoresist removal process removes the photoresist film layer.

[0054] During the etching process, metal trenches are formed at the edge of the contact surface between the first and second metal layers due to over-etching. These trenches are small and do not affect product quality. However, after removing the photoresist film with a stripping solution during the photoresist removal process, stripping solution can remain in the metal trenches. This residual solution reacts with the metal in the second metal layer, causing metal voids. Subsequent high-temperature processes accelerate this reaction, exacerbating the voids and increasing the size of the metal trenches. This can lead to cracks or breaks in the gate insulating layer protecting the gate layer on the second metal layer, causing electron migration in the second metal layer, resulting in electrostatic discharge and reduced product quality.

[0055] To address the problems existing in the prior art, this application provides a method for fabricating an array substrate. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic flowchart illustrating the fabrication method of the array substrate provided in this application embodiment. The array substrate can be applied to a display panel, which can be an LCD display panel, an OLED display panel, a Micro LED display panel, an LED display panel, etc. The specific steps of the fabrication method of this array substrate are as follows:

[0056] 201, providing a substrate.

[0057] In this embodiment, please refer to Figure 2 , Figure 2 This is a schematic diagram of the first intermediate product of the array substrate provided in the embodiments of this application. The substrate 101 can be a glass substrate or a flexible substrate, etc.

[0058] 202, a first metal layer and a second metal layer are sequentially formed on the substrate.

[0059] Continue reading Figure 2 In the gate layer deposition process, a first metal layer 102 is formed on a substrate 101, and a second metal layer 103 is formed on the first metal layer 102, i.e., the first metal layer 102 and the second metal layer 103 are stacked, with the first metal layer 102 disposed between the substrate 101 and the second metal layer 103. The metal material in the first metal layer 102 may include molybdenum, titanium, or a molybdenum-titanium alloy, etc., and the metal material in the second metal layer 103 may include copper or aluminum, etc.

[0060] 203, a mask layer is formed on the second metal layer.

[0061] Continue reading Figure 2 A photoresist layer 104 is formed on the second metal layer 103 by coating it with photoresist. (See also...) Figure 3 , Figure 3This is a schematic diagram of the second intermediate product of the array substrate provided in the embodiments of this application. In the photoresist patterning process, the photoresist layer 104 is exposed and developed to form a mask layer 105. During the development process after exposure, depending on the development time, the photoresist layer 104 may collapse on both sides, causing a patterned change in the photoresist layer 104 to form the mask layer 105.

[0062] 204. The first metal layer and the second metal layer are etched to form a patterned first metal layer and a patterned second metal layer.

[0063] Please see Figure 4 , Figure 4 This is a schematic diagram of the third intermediate product of the array substrate provided in the embodiments of this application. In the etching process, the substrate 101, the first metal layer 102, the second metal layer 103, and the mask layer 105 are immersed in a copper acid etching solution; the first metal layer 102 and the second metal layer 103 are wet-etched by the copper acid etching solution to form a patterned first metal layer 102 and a patterned second metal layer 103. Specifically, through the wet etching of the copper acid etching solution, with the mask layer 105 as a shield, collapse occurs on both sides of the first metal layer 102 and the second metal layer 103, causing the first metal layer 102 and the second metal layer 103 to undergo patterning changes to form a patterned first metal layer 102 and a patterned second metal layer 103, wherein the orthographic projection area of ​​the patterned first metal layer 102 on the substrate 101 and the orthographic projection area of ​​the patterned second metal layer 103 on the substrate 101 are located within the orthographic projection area of ​​the mask layer 105 on the substrate.

[0064] It should be noted that during the wet etching process of the first metal layer 102 and the second metal layer 103, since the contact surface between the first metal layer 102 and the second metal layer 103 is a dense metal area, it is easy for metal to be over-etched. Specifically, the copper metal in the first metal layer 102 may be over-etched, resulting in metal hollowing out, such as copper hollowing out. As a result, a metal trench 50 is formed in the edge area of ​​the contact surface between the first metal layer 102 and the second metal layer 103. The size of the metal trench 50 is small and will not affect the product quality.

[0065] The metal material of the first metal layer 102 may include molybdenum, titanium, or a molybdenum-titanium alloy. The size of the metal trench 50 formed by using molybdenum is larger than the size of the metal trench 50 formed by using molybdenum-titanium alloy. The size of the metal trench 50 formed by using molybdenum-titanium alloy is larger than the size of the metal trench 50 formed by using titanium. That is, using titanium can reduce the generation of metal hollowing during wet etching and reduce the size of the metal trench 50.

[0066] 205. The mask layer is removed by stripping solution to obtain a gate layer consisting of a patterned first metal layer and a patterned second metal layer.

[0067] Please see Figure 4 and Figure 5 , Figure 5 This is a schematic diagram of the first structure of the array substrate provided in the embodiments of this application. In the photoresist removal process, the photoresist is removed from the mask layer 105 by stripping liquid to obtain a gate layer 60 composed of a patterned first metal layer 102 and a patterned second metal layer 103, wherein the orthogonal projection region of the patterned second metal layer 103 on the substrate 101 is located within the orthogonal projection region of the patterned first metal layer 102 on the substrate 101.

[0068] Optionally, the refractive index of the first metal layer 102 can be greater than that of the second metal layer 103, so that light rays incident from the side of the first metal layer 102 away from the second metal layer 103 can be refracted in the first metal layer 102, ensuring that more light rays are emitted to the outside of the array substrate 100 and improving the light output efficiency of the array substrate 100.

[0069] 206. Oxygen is introduced into the metal trench between the patterned first metal layer and the patterned second metal layer. The residual stripping liquid in the metal trench is ashed by the ionized oxygen to remove the residual stripping liquid in the metal trench.

[0070] It should be noted that after the photoresist removal process, residual stripping solution may easily remain in the metal trench 50 between the patterned first metal layer 102 and the patterned second metal layer 103 in the gate layer 60. The residual stripping solution contains amines, such as hydroxylamine RNH2OH and primary amine RNH2. The amines react with metal atoms in the patterned second metal layer 103, such as copper Cu or aluminum Al, to generate reaction products such as copper hydroxytetramine complex Cu(RNH2)4(OH)2 and aluminum hydroxytetramine complex Al(RNH2)4(OH)2. The generated reaction products will corrode the metal in the second metal layer 103, causing metal hollowing, thereby increasing the size of the metal trench 50.

[0071] After the gate layer 60 fabrication process is completed, structures such as a gate insulating layer, active layer, source layer, drain layer, and passivation layer are fabricated on the gate layer 60 to form a thin-film transistor to meet the display requirements of the array substrate. However, the fabrication of the active layer, source layer, drain layer, and passivation layer is a high-temperature process. The high temperature will accelerate the reaction between the residual stripping solution and the metal in the second metal layer 103, causing the metal to be hollowed out more quickly. This can lead to cracks or breaks in the gate insulating layer on the gate layer 60. The metal in the second metal layer 103 will undergo electron migration, migrating from the cracks or breaks in the gate insulating layer to the top of the gate insulating layer, inducing electrostatic discharge and causing problems such as black screens, thus reducing product quality.

[0072] To prevent electrostatic discharge, in this embodiment, oxygen is introduced into the metal trench 50 between the patterned first metal layer 102 and the patterned second metal layer 103. The ionized oxygen ashing process removes the residual stripping liquid from the metal trench 50. Specifically, the amine in the residual stripping liquid in the metal trench 50 reacts with the metal atoms in the patterned second metal layer 103 to generate reaction products; oxygen is then introduced into the metal trench 50; the oxygen ions formed by the ionized oxygen react with the reaction products to generate gas and water; and the gas and water are removed by vacuuming to remove the residual stripping liquid from the metal trench 50.

[0073] It should be noted that the amines such as hydroxylamine RNH2OH and primary amine RNH2 in the stripping solution remaining in the metal trench 50 between the patterned first metal layer 102 and the patterned second metal layer 103 react with metal atoms such as copper Cu or aluminum Al in the patterned second metal layer 103 to form reaction products such as copper hydroxytetramine complex Cu(RNH2)4(OH)2 and aluminum hydroxytetramine complex Al(RNH2)4(OH)2, which have a relatively slow corrosion rate on the metal in the second metal layer 103. However, the reaction rate between oxygen treated by ionization and the reaction products is faster than the corrosion rate of the reaction products on the second metal layer 103. Therefore, before the reaction products corrode the second metal layer 103, the oxygen ionization reacts with the reaction products to generate gas and water, and the gas and water are discharged by vacuum treatment. This can prevent the size of the metal trench 50 from continuing to increase, thereby avoiding cracks or breaks in the gate insulating layer, reducing the risk of electrostatic discharge, and improving product quality.

[0074] Optionally, oxygen can be ionized using a radio frequency (RF) power supply or a high-power power supply. The oxygen ions formed by the ionization react with the reaction products to generate gas and water, wherein the gas may include carbon dioxide and / or carbon monoxide. It should be noted that using an RF power supply or a high-power power supply can accelerate the dissociation rate of oxygen, allowing for faster ionization and thus increasing the ashing rate of the oxygen ions. This ensures that the reaction products are removed in the form of gas and water before they corrode the metal in the second metal layer 103, i.e., removing the stripping fluid remaining in the metal trench 50, preventing the size of the metal trench 50 from continuing to increase, and preventing electrostatic discharge.

[0075] Additionally, please see Figure 6 , Figure 6 This is a schematic diagram of a second structure of the array substrate provided in this application embodiment. After the gate layer 60 is fabricated through the above steps, a gate insulating layer 106 can be formed on the substrate 101, wherein the gate insulating layer 106 covers the gate layer 60; an active layer 107 is formed on the gate insulating layer 106; a source layer 108 and a drain layer 109 are formed on the active layer 107; and a passivation layer 110 is formed on the gate insulating layer 106, wherein the passivation layer 110 covers the active layer 107, the source layer 108, and the drain layer 109.

[0076] Specifically, a gate insulating layer 106 is disposed on the substrate 101 and covers the gate layer 60 to prevent electron migration in the metal of the gate layer 60 and avoid electrostatic discharge. A conductive film layer is coated on the gate insulating layer 106, and an active layer 107 is formed by patterning. The orthographic projection region of the gate layer 60 on the substrate 101 is located within the orthographic projection region of the active layer 107 on the substrate 101. A patterned source layer 108 and a patterned drain layer 109 are formed on both sides of the active layer 107, thereby forming a thin-film transistor composed of the gate layer 60, the source layer 108, and the drain layer 109. A passivation layer 110 is formed on the gate insulating layer 106, and the passivation layer 110 covers the active layer 107, the source layer 108, and the drain layer 109 to protect the thin-film transistor.

[0077] As described above, this embodiment provides a substrate 101; a first metal layer 102 and a second metal layer 103 are sequentially formed on the substrate 101; a mask layer 105 is formed on the second metal layer 103; the first metal layer 102 and the second metal layer 103 are etched to form patterned first metal layer 102 and second metal layer 103; the mask layer 105 is removed using a stripping solution to obtain a gate layer 60 composed of patterned first metal layer 102 and patterned second metal layer 103; oxygen is introduced into the metal trench 50 between the patterned first metal layer 102 and the patterned second metal layer 103, and the residual stripping solution in the metal trench 50 is ashed by ionized oxygen to remove the residual stripping solution in the metal trench 50. By adding an ionized oxygen ashing process after removing the mask layer 105, the residual stripping solution is removed, the generation of metal hollowing in the metal trench 50 is reduced, electrostatic discharge is avoided, and product quality is improved.

[0078] Accordingly, this application also provides an array substrate, please refer to the following embodiments. Figure 6 The array substrate 100 may include a substrate 101, a gate layer 60, a gate insulating layer 106, an active layer 107, a source layer 108, a drain layer 109, and a passivation layer 110.

[0079] The gate layer 60 is disposed on the substrate 101. Please refer to the following. Figures 2 to 5 The gate layer 60 may include a patterned first metal layer 102 and a patterned second metal layer 103, which are stacked together. The patterned first metal layer 102 is disposed between the substrate 101 and the patterned second metal layer 103. The orthogonal projection region of the patterned second metal layer 103 on the substrate 101 is located within the orthogonal projection region of the patterned first metal layer 102 on the substrate 101. The metal material of the patterned first metal layer 102 may include molybdenum, titanium, or a molybdenum-titanium alloy, and the metal material of the patterned second metal layer 103 may include copper or aluminum.

[0080] The fabrication process of the gate layer 60 may include: providing a substrate 101, and sequentially forming a first metal layer 102 and a second metal layer 103 on the substrate 101; forming a mask layer 105 on the second metal layer 103; etching the first metal layer 102 and the second metal layer 103 to form patterned first metal layer 102 and second metal layer 103; removing the mask layer 105 with a stripping solution to obtain the gate layer 60 composed of the patterned first metal layer 102 and the patterned second metal layer 103; introducing oxygen into a metal trench 50 between the patterned first metal layer 102 and the patterned second metal layer 103, and using ionized oxygen to ashed the residual stripping solution in the metal trench 50 to remove the residual stripping solution. It should be noted that the specific fabrication process of the gate layer 60 can be referred to the previous embodiment, and will not be repeated here.

[0081] A gate insulating layer 106 is disposed on the substrate 101 and covers the gate layer 60 to prevent electron migration in the metal of the gate layer 60 and avoid electrostatic discharge.

[0082] The active layer 107 is disposed on the gate insulating layer 106. A conductive film layer can be coated on the gate insulating layer 106 and the active layer 107 can be formed by patterning. The orthogonal projection region of the gate layer 60 on the substrate 101 is located within the orthogonal projection region of the active layer 107 on the substrate 101.

[0083] Both the source layer 108 and the drain layer 109 are disposed on the active layer 107. Specifically, a patterned source layer 108 and a patterned drain layer 109 are formed on both sides of the active layer 107, thereby forming a thin film transistor composed of the gate layer 60, the source layer 108 and the drain layer 109.

[0084] The passivation layer 110 is disposed on the gate insulating layer 106, and the passivation layer 110 covers the active layer 107, the source layer 108 and the drain layer 109. The passivation layer 110 covers the active layer 107, the source layer 108 and the drain layer 109 to achieve the protection of the thin film transistor.

[0085] In the process of preparing the gate layer 60, the array substrate 100 provided in this embodiment removes the residual stripping liquid from the photoresist removal process by oxygen ionization treatment, so as to avoid the residual stripping liquid reacting with the metal in the patterned second metal layer 103 to produce metal hollowing, thereby avoiding electrostatic discharge induced by the metal electron migration reaction, and thus improving product quality.

[0086] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0087] The preparation method of the array substrate and the array substrate provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principle and implementation of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this application. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating an array substrate, characterized in that, include: Provide a substrate; A first metal layer and a second metal layer are sequentially formed on the substrate; A mask layer is formed on the second metal layer; The first metal layer and the second metal layer are etched to form a patterned first metal layer and a patterned second metal layer; The mask layer is removed by a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer; Oxygen is introduced into the metal trench between the patterned first metal layer and the patterned second metal layer, and the residual stripping liquid in the metal trench is ashed by the ionized oxygen to remove the residual stripping liquid in the metal trench.

2. The method for fabricating an array substrate according to claim 1, characterized in that, Oxygen is introduced into the metal trench between the patterned first metal layer and the patterned second metal layer, and the residual stripping liquid in the metal trench is ashed by ionized oxygen to remove the residual stripping liquid in the metal trench, including: The amine in the stripping solution remaining in the metal trench between the patterned first metal layer and the patterned second metal layer reacts with the metal atoms in the patterned second metal layer to generate reaction products. Oxygen is introduced into the metal trench; Oxygen ions formed from oxygen ionized oxygen react with the reaction products to generate gas and water. The gas and water are removed by vacuuming to eliminate the stripping fluid remaining in the metal trench.

3. The method for fabricating an array substrate according to claim 2, characterized in that, The oxygen ions formed by the ionization treatment of oxygen react with the reaction products to generate gas and water, including: The oxygen is ionized using a radio frequency power supply or a high-power power supply. The oxygen ions formed by the ionization treatment react with the reaction products to generate gas and water, wherein the gas includes carbon dioxide and / or carbon monoxide.

4. The method for fabricating an array substrate according to claim 1, characterized in that, The step of forming a mask layer on the second metal layer includes: A photoresist layer is formed on the second metal layer; The photoresist layer is exposed and developed to form the mask layer.

5. The method for fabricating an array substrate according to claim 4, characterized in that, The etching of the first metal layer and the second metal layer to form a patterned first metal layer and a patterned second metal layer includes: The substrate, the first metal layer, the second metal layer, and the mask layer are immersed in a copper acid etching solution; The first metal layer and the second metal layer are wet-etched using the copper acid etching solution to form the patterned first metal layer and the patterned second metal layer, wherein the orthographic projection area of ​​the patterned first metal layer on the substrate and the orthographic projection area of ​​the patterned second metal layer on the substrate are both located within the orthographic projection area of ​​the mask layer on the substrate.

6. The method for fabricating an array substrate according to claim 5, characterized in that, The step of removing the mask layer with a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer includes: The photoresist in the mask layer is removed by a stripping solution to obtain a gate layer composed of the patterned first metal layer and the patterned second metal layer, wherein the orthogonal projection region of the patterned second metal layer on the substrate is located within the orthogonal projection region of the patterned first metal layer on the substrate.

7. The method for fabricating an array substrate according to claim 1, characterized in that, The metal material in the first metal layer includes molybdenum, titanium, or a molybdenum-titanium alloy, and the metal material in the second metal layer includes copper or aluminum.

8. The method for fabricating an array substrate according to claim 1, characterized in that, After introducing oxygen into the metal trench between the patterned first metal layer and the patterned second metal layer, and using ionized oxygen to ashing the residual stripping solution in the metal trench to remove the residual stripping solution, the method further includes: A gate insulating layer is formed on the substrate, wherein the gate insulating layer covers the gate layer; An active layer is formed on the gate insulating layer; A source layer and a drain layer are formed on the active layer; A passivation layer is formed on the gate insulating layer, wherein the passivation layer covers the active layer, the source layer and the drain layer.

9. An array substrate, characterized in that, The array substrate is prepared using the fabrication method described in any one of claims 1-8, wherein the array substrate comprises: Substrate; A gate layer is disposed on the substrate; A gate insulating layer is disposed on the substrate and covers the gate layer; An active layer is disposed on the gate insulating layer; Both the source layer and the drain layer are disposed on the active layer; A passivation layer is disposed on the gate insulating layer and covers the active layer, the source layer and the drain layer.

10. The array substrate according to claim 9, characterized in that, The gate layer includes a first metal layer and a second metal layer, the first metal layer and the second metal layer are stacked, and the first metal layer is disposed between the substrate and the second metal layer. The orthogonal projection area of ​​the second metal layer on the substrate is located within the orthogonal projection area of ​​the first metal layer on the substrate.

11. The array substrate according to claim 10, characterized in that, The first metal layer is made of molybdenum, titanium, or a molybdenum-titanium alloy, and the second metal layer is made of copper or aluminum.

Images