Patterned layout of interlayer oxide layer wafer and method of making same

Abstract

The application discloses a kind of patterned layout interlayer oxide layer wafer and its manufacturing method.The manufacturing method includes: providing epitaxial structure, and form first protective layer on the silicon epitaxial layer, wherein the epitaxial structure includes sequentially stacked silicon substrate, silicon oxide insulating layer and silicon epitaxial layer;Mask is set on the first protective layer, and more than one recess is etched to form in the area not covered by mask, the recess is continuously through the first protective layer, silicon epitaxial layer and extends to the silicon oxide insulating layer in thickness direction;Second protective layer is formed on the side wall of the recess;The remaining silicon oxide insulating layer at the bottom of the recess is etched away;Silicon layer is formed in the recess, and the first protective layer and second protective layer are removed.The application can obtain better quality patterned SOI substrate, avoid the impurity defects introduced by other processes at the interface of silicon substrate and insulating layer, and ensure that the quality of silicon epitaxial layer on the insulating layer is better.

Description

TECHNICAL FIELD

[0001] The present application relates to a wafer manufacturing method, in particular to a patterned layout sandwiched oxide layer wafer and a manufacturing method thereof, and belongs to the technical field of semiconductors. BACKGROUND

[0002] A traditional SOI substrate has a cross-sectional structure as shown in FIG. 1, wherein 00 is a silicon substrate, 01 is a silicon oxide insulating layer, and 02 is an epitaxial layer. The silicon oxide insulating layer is integrally connected. The thermal conductivity of the silicon oxide insulating layer is only one-twentieth of that of bulk silicon. Therefore, heat dissipation is a big problem for traditional SOI, and the main reason for the failure of development for many years is self-heating effect. Figure 1

[0003] In order to solve the self-heating effect of SOI radio frequency power, the thickness of the upper silicon layer of SOI is usually made to be more than 4 microns to reduce junction temperature by increasing silicon heat melting. However, the effect of the thick silicon layer is not superior to that of bulk silicon, and the parasitic capacitance cannot be significantly reduced, so the high-frequency performance cannot be improved. In addition, the silicon oxide insulating layer of the traditional SOI is integrally connected, and TSV technology must be used to form a back ground. The TSV technology needs to etch a through hole through the silicon epitaxial layer, the silicon oxide insulating layer and the silicon substrate layer. Different etching selection ratios will affect the appearance of the through hole, such as consistency and uniformity, and thus the reliability and consistency of the device will be reduced. More importantly, the two-layer insulating layer in one piece is not conducive to the integration of power amplification chips, switches, low-noise amplifiers, digital control circuits and other functional modules, and high integration is an important trend of chip development. SUMMARY

[0004] The main purpose of the present application is to provide a patterned layout sandwiched oxide layer wafer and a manufacturing method thereof to overcome the shortcomings of the prior art.

[0005] To achieve the above-mentioned purposes, the technical scheme adopted by the present application comprises:

[0006] The present application provides a patterned layout sandwiched oxide layer wafer and a manufacturing method thereof. The manufacturing method comprises the following steps:

[0007] 1) providing an epitaxial structure, and forming a first protective layer on the silicon epitaxial layer, wherein the epitaxial structure comprises a silicon substrate, a silicon oxide insulating layer and a silicon epitaxial layer which are sequentially stacked, and the first protective layer is arranged on the silicon epitaxial layer;

[0008] 2) arranging a mask on the first protective layer, and etching to form one or more recesses in the region not covered by the mask, the recesses continuously penetrate the first protective layer, the silicon epitaxial layer and extend into the silicon oxide insulating layer along the thickness direction;

[0009] ​3) forming a second protective layer on the sidewall of the recess, the second protective layer covering at least the silicon epitaxial layer;

[0010] 4) etching the remaining silicon oxide insulating layer at the bottom of the recess to expose the silicon substrate from the recess;

[0011] 5) forming a silicon layer in the recess, and electrically connecting the silicon layer with the silicon substrate and the silicon epitaxial layer, and removing the first protective layer and the second protective layer.

[0012] Compared with the prior art, the advantages of the present application include:

[0013] 1) the manufacturing method provided by the embodiment of the present application has a simple process flow, and the silicon substrate and the insulating layer are integrally formed, so that a better quality patterned SOI substrate can be obtained, and the impurity defects introduced by other processes at the interface between the silicon substrate and the insulating layer are avoided, so that the quality of the silicon epitaxial layer on the insulating layer is better, and meanwhile, the defects at the interface between the oxide layer and the silicon are reduced;

[0014] 2) the manufacturing method provided by the embodiment of the present application arranges the insulating layer according to the needs of the circuit or the device to form a patterned insulating layer, and the part outside the coverage area of the insulating layer is still silicon and is connected with the silicon epitaxial layer and the silicon substrate, so that the heat generated by the upper silicon epitaxial layer can be introduced into the silicon substrate, so as to reduce the junction temperature of the silicon device, so that the thickness of the silicon epitaxial layer is reduced, the parasitic capacitance is reduced, the high-frequency performance and efficiency of the device are improved, and the Q value of the passive device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a schematic diagram of the cross-sectional structure of a traditional SOI substrate;

[0016] Figure 2 is a schematic diagram of the cross-sectional structure of a patterned sandwiched oxide layer wafer provided in a typical embodiment of the present application;

[0017] Figures 3a-3h are schematic diagrams of the manufacturing process structure of a patterned sandwiched oxide layer wafer provided in a typical embodiment of the present application, respectively;

[0018] Figure 4a 、 Figure 4b are schematic diagrams of the structure of an LDMOS device formed based on a global insulating layer and a patterned insulating layer wafer, respectively;

[0019] Explanation of reference signs: 20-silicon substrate, 21-insulating layer, 22-drift region, 23-gate region, 24-source region, 25-drain region, 26-body region contact region, 27-body region, 30-silicon substrate, 31-insulating layer, 32-drift region of LDMOS device, 33-gate region, 34-source region, 35-drain region, 36-body region contact region, 37-body region. DETAILED DESCRIPTION

[0020] In view of the deficiencies in the prior art, the present inventors have, through long-term research and a large number of practices, come up with the technical solution of the present application. The technical solution, its implementation process and principles will be further explained as follows.

[0021] The present application proposes a SOI wafer structure manufacturing method for sandwiched oxide layer patterning layout for radio frequency single-chip integration in view of the defects of the current SOI substrate. The sandwiched oxide layer patterning layout can greatly reduce the parasitic capacitance of the wafer, and at the same time, make the wafer have good heat dissipation performance. More importantly, the corresponding patterning layout scheme can be adopted according to the requirements of different components, i.e. the layout matching of the patterning layout and different components, to realize the integration of different components, such as power amplification, low-noise amplification, switching, power division, digital control circuit and other functional chips. The wafer structure manufacturing method provided in the embodiments of the present application has simple process, is compatible with the existing silicon manufacturing process, and can manufacture the required SOI pattern according to the pattern requirements of the components, so that the silicon layer on the thin insulating layer can be very conveniently manufactured.

[0022] The embodiment of the present application provides a sandwiched oxide layer wafer manufacturing method with patterning layout, which comprises:

[0023] 1) providing an epitaxial structure, and forming a first protective layer on the silicon epitaxial layer, wherein the epitaxial structure comprises a silicon substrate, a silicon oxide insulating layer and a silicon epitaxial layer which are sequentially stacked, and the first protective layer is arranged on the silicon epitaxial layer;

[0024] 2) arranging a mask on the first protective layer, and etching to form one or more than one recess in the region not covered by the mask, the recess continuously penetrates the first protective layer, the silicon epitaxial layer and extends into the silicon oxide insulating layer along the thickness direction;

[0025] 3) forming a second protective layer on the side wall of the recess, and the second protective layer at least covers the silicon epitaxial layer;

[0026] 4) etching to remove the remaining silicon oxide insulating layer at the bottom of the recess, and exposing the silicon substrate from the recess;

[0027] 5) forming a silicon layer in the recess, and electrically connecting the silicon layer with the silicon substrate and the silicon epitaxial layer, and removing the first protective layer and the second protective layer.

[0028] Further, the first protective layer comprises a silicon oxide layer and a silicon nitride layer which are sequentially stacked on the silicon epitaxial layer.

[0029] Further, the thickness of the silicon oxide layer is 5-30 nm, and the thickness of the silicon nitride layer is 100-200 nm.

[0030] Further, the step 3) specifically comprises: performing an oxidation treatment on the silicon epitaxial layer exposed from the recess, so as to locally oxidize the silicon epitaxial layer close to the recess to form the second protective layer.

[0031] Further, the material of the second protective layer comprises silicon oxide.

[0032] Further, the thickness of the second protective layer is 2-5 nm.

[0033] Further, the step 5) specifically comprises: performing a high-temperature annealing treatment on the second protective layer under the condition of a temperature above 1200 ℃ and an inert gas atmosphere, so as to decompose and remove the second protective layer.

[0034] Further, the time of the high-temperature annealing treatment is not more than 3 h.

[0035] Further, the silicon layer is flush with the top surface of the silicon epitaxial layer.

[0036] Further, the manufacturing method specifically comprises: etching a plurality of recesses in the epitaxial structure; preferably, the plurality of recesses are distributed in an array manner.

[0037] Further, the shape of the recess comprises any one or a combination of two or more of a rectangle, an ellipse and a circle.

[0038] Further, the thickness of the silicon oxide insulation layer is 0.1-4 μm, and the thickness of the silicon epitaxial layer is 0.1-4 μm.

[0039] Further, the silicon oxide insulation layer is formed by performing an oxidation treatment on a part of the silicon substrate.

[0040] The embodiment of the present application also provides a wafer structure with a patterned layout of a sandwiched oxide layer, which is manufactured by the manufacturing method.

[0041] The technical solutions, implementation processes and principles will be further explained in combination with the drawings. Unless specifically stated, the epitaxy, etching and oxidation processes used in the embodiments of the present application can be the processes known to those skilled in the art.

[0042] Please refer to Figure 2 A patterned interlayer oxide wafer includes a silicon substrate 10, a silicon oxide insulating layer 11 and a silicon epitaxial layer 12 arranged in sequence, wherein the silicon oxide insulating layer 11 is patterned, and the silicon substrate 10 and the silicon epitaxial layer 12 are connected at the patterned windows in the silicon oxide insulating layer 11.

[0043] Embodiment 1

[0044] In some specific embodiments, a method for manufacturing a patterned interlayer oxide wafer includes the following steps:

[0045] Step 1: An epitaxial structure as shown in Figure 3a is manufactured, which includes a silicon substrate 10, a silicon oxide insulating layer 11 and a silicon epitaxial layer 12 arranged in sequence, wherein the thickness of the silicon oxide insulating layer 11 is between 0.1 um and 4 um, and the thickness of the silicon epitaxial layer 12 is between 0.1 um and 4 um, and the silicon oxide insulating layer 11 is formed by oxidizing part of the silicon substrate 10.

[0046] Step 2: A silicon oxide layer 13 and a silicon nitride layer 14 are formed on the surface of the silicon epitaxial layer 12 of the epitaxial structure as a first protective layer including the silicon epitaxial layer 12, as shown in Figure 3b , wherein the thickness of the silicon oxide layer 13 is between 5 nm and 30 nm, and the thickness of the silicon nitride layer 14 is between 100 nm and 200 nm.

[0047] Step 3: A patterned mask is arranged on the surface of the silicon nitride layer 14, and the area not covered by the mask is etched along the thickness direction of the epitaxial structure, so as to form one or more recesses, which continuously extend through the silicon nitride layer 14, the silicon oxide layer 13, the silicon epitaxial layer 12 and the silicon oxide insulating layer 11 along the thickness direction, as shown in Figure 3c The specific etching depth can be achieved by controlling the etching time.

[0048] Of course, considering the etching process conditions fluctuation and other factors, the depth of the etching formed recess hole can not be accurate to reach or stay inside the silicon oxide insulating layer 11, or the etching process conditions can be controlled to make the recess hole continuously penetrate the silicon nitride layer 14, the silicon oxide layer 13, the silicon epitaxial layer 12 along the thickness direction, and the etching stops when reaching the silicon oxide insulating layer 11, because the subsequent steps will still etch away the silicon oxide insulating layer in the region corresponding to the recess hole and select the growth of the silicon layer 16, and when the silicon oxide layer 15 is formed on the sidewall of the recess hole as the second protective layer, the silicon oxide layer will be formed on the surface layer of the silicon substrate, which will also be etched away before the selective growth of the silicon layer;

[0049] Step four: oxidizing the silicon epitaxial layer 12 exposed from the recess hole to oxidize the local part of the silicon epitaxial layer 12 close to the recess hole to form a thin silicon oxide layer 15, and taking the thin silicon oxide layer 15 as the second protective layer for the silicon epitaxial layer 12, the thickness of the silicon oxide layer 15 is between 2nm and 5nm, and the epitaxial structure after oxidation is as shown in Figure 3d

[0050] Step five: etching away the remaining silicon oxide insulating layer 11 at the bottom of the recess hole, and stopping etching when reaching the silicon substrate 10, which is exposed from the recess hole, and the epitaxial structure formed in this step is as shown in Figure 3e

[0051] Step six: growing a silicon layer 16 in the corresponding region in the recess hole, and connecting the silicon layer 16 with the silicon substrate 10, and the epitaxial structure formed in this step is as shown in Figure 3f

[0052] Step seven: removing the silicon nitride layer 14, and then performing high-temperature annealing treatment on the epitaxial structure under the condition of inert gas atmosphere at a temperature above 1200℃, and the annealing treatment time is not more than 3h, so that the silicon oxide layer 15 on the sidewall of the recess hole is decomposed and removed, and at the same time, the silicon layer 16 is connected with the silicon epitaxial layer 12 and the silicon substrate 10, and the epitaxial structure formed in this step is as shown in Figure 3g Through high-temperature annealing treatment, the silicon oxide layer 15 on the sidewall of the recess hole is decomposed, the silicon layer 16, the silicon epitaxial layer 12 and the silicon substrate 10 are connected, and a heat dissipation channel of the device is formed, at the same time, the high-temperature annealing treatment can also grow a new oxide layer at the silicon interface, eliminate the defects introduced by the previous process, and the high-temperature annealing treatment can also eliminate the defects at the interface of the oxide layer;

[0053] Step eight: removing the top silicon oxide layer 13, and using the CMP process to grind the silicon layer 16 to the desired thickness, for example, making the surface of the silicon layer 16 flush with the surface of the silicon epitaxial layer 12, and the finally formed wafer structure is as shown in Figure 3h

[0054] ​​​​It should be noted that the annealing treatment within 3h in the environment of inert gas such as argon at the temperature above 1200℃ can decompose the silicon oxide with the thickness below 10nm, so the silicon oxide layer 15 below 10nm can be decomposed and removed, and the thickness of the silicon oxide insulation layer 11 is greater than 100nm, so only the partial silicon oxide insulation layer 11 of the surface layer can be decomposed under the annealing condition, and the partial silicon oxide insulation layer can be ignored.

[0055] The silicon oxide insulation layer 11 provided by the embodiment of the present application is formed by oxidizing the silicon substrate 10, so that the best oxide layer interface quality can be obtained, the silicon dioxide of the clean interface is etched before the step of selectively growing the silicon layer 16, and then the silicon is selectively grown, and the present application can repair the defects of the epitaxial structure generated in the process while decomposing and removing the silicon oxide layer 15 of the hole sidewall, so that the better quality of the silicon oxide interface can be obtained.

[0056] Comparative Example 1

[0057] A method for manufacturing a patterned sandwiched oxide layer wafer, specifically comprising the following steps:

[0058] Step one: manufacturing an epitaxial structure as shown in Figure 3a , the epitaxial structure comprises a silicon substrate 10, a silicon oxide insulation layer 11 and a silicon epitaxial layer 12 which are sequentially stacked, the thickness of the silicon oxide insulation layer 11 is between 0.1um and 4um, and the thickness of the silicon epitaxial layer 12 is between 0.1um and 4um;

[0059] Step two: sequentially manufacturing a silicon oxide layer 13 and a silicon nitride layer 14 on the surface of the silicon epitaxial layer 12 of the epitaxial structure as a first protective layer comprising the silicon epitaxial layer 12, the manufactured epitaxial structure is as shown in Figure 3b , wherein the thickness of the silicon oxide layer 13 is between 5nm and 30nm, and the thickness of the silicon nitride layer 14 is between 100nm and 200nm;

[0060] Step three: setting a patterned mask on the surface of the silicon nitride layer 14, and etching the area not covered by the mask, the etching is performed along the thickness direction of the epitaxial structure and stops at the surface of the silicon substrate 10, so as to form one or more than one hole, the hole continuously penetrates the silicon nitride layer 14, the silicon oxide layer 13, the silicon epitaxial layer 12 and the silicon oxide insulation layer 11 along the thickness direction, and the silicon substrate 10 is exposed from the hole;

[0061] Step four: growing a silicon layer 16 in the corresponding area of the hole, and connecting the silicon layer 16 with the silicon substrate 10 and the silicon epitaxial layer 12;

[0062] Step five: remove the silicon nitride layer 14 and the silicon oxide layer 13, and polish the silicon layer 16 to a desired thickness by using a CMP process, for example, to make the surface of the silicon layer 16 flush with the surface of the silicon epitaxial layer 12, thereby forming a final wafer structure as shown in Figure 3h .

[0063] The manufacturing method provided by the embodiments of the present application can obtain a better quality patterned SOI substrate, avoids impurity defects introduced by other processes at the interface between the silicon substrate and the insulating layer, and can ensure that the quality of the silicon epitaxial layer on the insulating layer is better; and the manufacturing method provided by the embodiments of the present application can layout the insulating layer according to the needs of a circuit or a device, form a patterned insulating layer, and the part outside the coverage area of the insulating layer is still silicon and is connected with the silicon epitaxial layer and the silicon substrate, so that the heat generated by the upper silicon epitaxial layer can be conducted to the silicon substrate, the purpose of reducing the junction temperature of the silicon device is achieved, the thickness of the silicon epitaxial layer is reduced, the parasitic capacitance is reduced, the high-frequency performance and efficiency of the device are improved, and the Q value of the passive device is improved.

[0064] The structures of the LDMOS devices formed based on the global insulating layer and the patterned insulating layer are shown in Figure 4a and Figure 4b respectively, the performances of the two kinds of LDMOS devices are tested respectively, and the test results show that the capacitance of the LDMOS device based on the patterned insulating layer is 2% higher than that of the LDMOS device based on the global insulating layer, but the temperature rise of the LDMOS device based on the patterned insulating layer is reduced by 45% under the same output power, and the overall efficiency is improved by 3 percentage points.

[0065] The wafer structure manufacturing method of the present application has a simple process, is compatible with the existing silicon manufacturing process, can manufacture the required SOI pattern according to the pattern needs of the device by using a mask, and can very conveniently manufacture a thin silicon layer on an insulating layer.

[0066] It should be understood that the above embodiments are only for illustrating the technical concept and characteristics of the present application, the purpose is to enable those skilled in the art to understand the content of the present application and implement it, and cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and essence of the present application should be covered within the protection scope of the present application.

Claims

1. A method for fabricating a patterned sandwich oxide layer wafer, characterized in that... include: 1) Provide an epitaxial structure and form a first protective layer on the epitaxial structure, wherein the epitaxial structure includes a silicon substrate, a silicon oxide insulating layer and a silicon epitaxial layer stacked sequentially, and the first protective layer is disposed on the silicon epitaxial layer; 2) A mask is provided on the first protective layer, and one or more recesses are etched in the area not covered by the mask. The recesses continuously penetrate the first protective layer and the silicon epitaxial layer along the thickness direction and extend into the silicon oxide insulating layer. 3) A second protective layer is formed on the sidewall of the recess, the second protective layer at least covering the silicon epitaxial layer, and the material of the second protective layer includes silicon oxide; 4) Etch away the remaining silicon oxide insulating layer at the bottom of the recess, and expose the silicon substrate from the recess; 5) Form a silicon layer in the recess and electrically connect the silicon layer to the silicon substrate and the silicon epitaxial layer, and remove the first protective layer and the second protective layer.

2. The manufacturing method according to claim 1, characterized in that: The first protective layer includes a silicon oxide layer and a silicon nitride layer sequentially stacked on a silicon epitaxial layer.

3. The manufacturing method according to claim 2, characterized in that: The thickness of the silicon oxide layer is 5-30 nm, and the thickness of the silicon nitride layer is 100-200 nm.

4. The manufacturing method according to claim 1, characterized in that, Step 3) specifically includes: oxidizing the silicon epitaxial layer exposed from the recess to form the second protective layer by locally oxidizing the silicon epitaxial layer near the recess.

5. The manufacturing method according to claim 1 or 4, characterized in that: The thickness of the second protective layer is 2-5 nm.

6. The manufacturing method according to claim 1, characterized in that, Step 5) specifically includes: annealing the second protective layer at a temperature above 1200°C under an inert gas atmosphere to decompose and remove the second protective layer.

7. The manufacturing method according to claim 6, characterized in that: The annealing process takes no more than 3 hours.

8. The manufacturing method according to claim 1, characterized in that: The silicon layer is flush with the top surface of the silicon epitaxial layer.

9. The manufacturing method according to claim 1, characterized in that... Specifically, it includes: Multiple recesses are etched into the epitaxial structure.

10. The manufacturing method according to claim 9, characterized in that: The multiple recessed holes are distributed in an array.

11. The manufacturing method according to claim 1 or 9, characterized in that: The shape of the concave hole includes any one or a combination of two or more of the following: rectangular, elliptical, and circular.

12. The manufacturing method according to claim 1, characterized in that: The thickness of the silicon oxide insulating layer is 0.1-4 μm, and the thickness of the silicon epitaxial layer is 0.1-4 μm.

13. The manufacturing method according to claim 12, characterized in that: The silicon oxide insulating layer is formed by locally oxidizing the silicon substrate.

14. A wafer structure with a patterned layout of sandwich oxide layers obtained by the fabrication method according to any one of claims 1-13.

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