Sonos memory based on ultra-thin ito film and preparation method thereof

Abstract

The application discloses a SONOS memory based on an ultrathin ITO film and a preparation method thereof. The SONOS memory based on the ultrathin ITO film comprises a substrate which is a Si sheet with a SiO2 layer, a groove is formed in the SiO2 layer as a gate region, a gate is formed in the gate region, a blocking layer / charge trapping layer laminated structure covers the gate, a tunneling layer is formed on the charge trapping layer, an ultrathin ITO film is formed on the tunneling layer as a channel, and a source and a drain are formed on both sides of the ITO film.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a SONOS memory based on an ultrathin ITO thin film and its fabrication method. Background Technology

[0002] Existing SONOS memories primarily use silicon as the channel, with electrons supplied by silicon during storage. As CMOS technology nodes continue to advance to below 5nm, the scaling of silicon devices becomes inherently limited, leading to reduced mobility and severe second-order effects such as short-channel effects.

[0003] Indium tin oxide (ITO) has long been used as a transparent electrode due to its high electron concentration and good conductivity. However, when ITO becomes ultrathin (below 10 nm), it exhibits semiconductor characteristics. The electron concentration varies in ultrathin ITO of different thicknesses; the thinner the ITO, the lower the electron concentration. Therefore, ultrathin ITO of different thicknesses can achieve both enhancement and depletion modes. Because of its high electron concentration, when the channel length decreases, the bulk charge density controlled by the gate voltage does not drop to the point where the drain space charge region extends into the channel, thus making it immune to short-channel effects. ITO also has a relatively high trap density, enabling a large storage window. Summary of the Invention

[0004] This invention discloses a SONOS memory based on an ultrathin ITO thin film, comprising: a substrate, which is a Si wafer having a SiO2 layer, wherein a groove is formed in the SiO2 layer as a gate region; a gate, formed in the gate region; a barrier layer / charge trapping layer stacked structure covering the gate; a tunneling layer formed on the charge trapping layer; an ultrathin ITO thin film formed on the tunneling layer as a channel; and a source and a drain formed on both sides of the ITO thin film.

[0005] In the SONOS memory based on ultrathin ITO film of the present invention, preferably, the thickness of the ultrathin ITO film is 0.7nm to 10nm.

[0006] In the SONOS memory based on ultrathin ITO thin film of the present invention, the barrier layer is preferably Al2O3, HfO2, ZrO2, or Ta2O5.

[0007] In the SONOS memory based on ultrathin ITO thin film of the present invention, preferably, the thickness of the barrier layer is 6nm to 20nm and the thickness of the charge trapping layer is 4nm to 10nm.

[0008] In the SONOS memory based on ultrathin ITO thin film of the present invention, preferably, the thickness of the tunneling layer is 3nm to 10nm.

[0009] This invention also discloses a method for fabricating a SONOS memory based on an ultrathin ITO thin film, comprising the following steps: preparing a substrate, which is a Si wafer having a SiO2 layer; forming a groove in the SiO2 layer as a gate region; forming a gate in the gate region; forming a barrier layer / charge trapping layer stacked structure on the above structure to cover the gate; forming a tunneling layer on the charge trapping layer; forming an ultrathin ITO thin film on the tunneling layer as a channel; and forming a source and a drain on both sides of the ultrathin ITO thin film.

[0010] In the SONOS memory fabrication method based on ultrathin ITO thin film of the present invention, preferably, the thickness of the ultrathin ITO thin film is 0.7 nm to 10 nm.

[0011] In the method for fabricating SONOS memory based on ultrathin ITO thin film of the present invention, the barrier layer is preferably Al2O3, HfO2, ZrO2, or Ta2O5.

[0012] In the SONOS memory fabrication method based on ultrathin ITO thin film of the present invention, preferably, the thickness of the barrier layer is 6nm to 20nm and the thickness of the charge trapping layer is 4nm to 10nm.

[0013] In the SONOS memory fabrication method based on ultrathin ITO thin film of the present invention, preferably, the thickness of the tunneling layer is 3nm to 10nm. Attached Figure Description

[0014] Figure 1 This is a flowchart of the SONOS memory fabrication method based on ultrathin ITO thin film.

[0015] Figures 2-7 This is a schematic diagram of the structure of each stage of the SONOS memory fabrication method based on ultrathin ITO thin film. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0017] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0019] Figure 1 This is a flowchart of a SONOS memory fabrication method based on an ultrathin ITO thin film. (Example:) Figure 1 As shown, the method for fabricating a SONOS memory based on an ultrathin ITO thin film includes the following steps:

[0020] Step S1: Prepare a Si substrate 100 with a SiO2 layer 101 (thickness greater than 100 nm), clean the surface with alcohol and deionized water, and then dry it with nitrogen gas.

[0021] Step S2: A 50nm thick layer of polyvinyl alcohol (PVA) and a 50nm thick layer of polymethyl methacrylate (PMMA) are spin-coated sequentially onto the SiO2 layer 101, followed by mask exposure and development. The gate pattern is etched using CCl4 gas to form a 40nm deep trench as the gate region. Then, a 70nm thick metal, such as Pt, is physically vapor-deposited using a lift-off method to form the gate 102. Figure 2 As shown. The gate can also be a metal such as Ag or Ni.

[0022] Step S3: An Al2O3 thin film with a thickness of 6 nm to 20 nm is grown using atomic layer deposition (ALD) as a barrier layer 103 to cover the gate 102. Preferably, the reaction temperature is 200°C and the deposition rate is 0.1 nm / cycle. Figure 3As shown. The barrier layer can also be made of high-k dielectric materials such as HfO2, ZrO2, and Ta2O5. The function of the Al2O3 barrier layer is to prevent charge leakage to the gate. If the Al2O3 film is too thin, it cannot effectively function as a barrier layer, resulting in reduced storage performance. If the Al2O3 film is too thick, it will divert most of the gate voltage drop, reducing gate control capability and degrading memory performance. Therefore, this application sets the barrier layer thickness between 6nm and 20nm.

[0023] Step S4: A Si3N4 thin film with a thickness of 4 nm to 10 nm is deposited on the barrier layer 103 using chemical vapor deposition as a charge trapping layer 104. Figure 4 As shown. The charge trapping layer can also be made of high-k dielectric materials such as Al₂O₃ and HfO₂, or some oxide semiconductor materials such as hafnium zirconium oxide and ZnO, as long as they possess high trapping density and deep trap energy levels. However, it is important to note that the charge trapping layer, tunneling layer, and barrier layer are different dielectric materials.

[0024] Step S5: An Al2O3 thin film with a thickness of 3 nm to 10 nm is grown on the charge trapping layer 104 using atomic layer deposition (ALD) as the tunneling layer 105. Figure 5 As shown. The reaction temperature is 200℃, and the growth rate is 0.1 nm / cycle. When a voltage is applied to the gate, electrons tunnel through the tunneling layer. If the tunneling layer is too thick, the electron tunneling efficiency will decrease, and the number of electrons that can be trapped by the charge trapping layer will also decrease, resulting in a lower threshold voltage offset of the device, a smaller storage window, and reduced memory performance. If the tunneling layer is too thin, the overall breakdown voltage performance of the device will decrease, and the retention and durability performance of the memory will also decrease. Therefore, in this application, the suitable thickness of the Al2O3 tunneling layer is selected to be 3 nm to 10 nm. The tunneling layer can also be HfO2, ZrO2, Ta2O5, etc. In this embodiment, the charge trapping layer and the tunneling layer are each one layer, but the present invention is not limited to this and can also be a multi-layered structure, that is, multiple layers of charge trapping layers and tunneling layers are alternately stacked.

[0025] Step S6: An ultrathin ITO film 106 is deposited on the tunneling layer 105 as a channel using physical vapor deposition, such as... Figure 6 As shown. Preferably, the growth temperature does not exceed 300℃ to ensure compatibility with subsequent processes. The ITO film should not be too thick, otherwise the electron concentration will be too high, making it unsuitable for use as a channel. The thinner the ITO, the wider its bandgap and the more pronounced its semiconductor characteristics. After repeated optimization tests, the thickness of the ITO film was set between 0.7nm and 10nm.

[0026] Step S7: A 70 nm thick Pt metal is physically vapor-deposited on the ultrathin ITO film 106 using a peel-and-strip method as the source 107 and drain 108, as shown below. Figure 7 As shown. The source and drain can also be metals such as Ag and Ni.

[0027] like Figure 7 As shown, the SONOS memory based on an ultrathin ITO thin film includes: a substrate, which is a Si wafer 100 having a SiO2 layer 101, in which a groove is formed as a gate region; a gate 102 formed in the gate region; a barrier layer 103 / charge trapping layer 104 stacked structure covering the gate 102; a tunneling layer 105 formed on the charge trapping layer 104; an ultrathin ITO thin film 106 formed on the tunneling layer 105 as a channel; and a source 107 and a drain 108 formed on both sides of the ultrathin ITO thin film 106.

[0028] By applying a forward voltage to the gate, electrons tunnel through the Al2O3 tunneling layer to the Si3N4 charge trapping layer. These electrons are trapped in the Si3N4 layer, causing a forward shift in the device's threshold voltage, thus enabling the write operation. When a reverse voltage is applied to the gate, electrons in the Si3N4 charge trapping layer return to the ultrathin ITO film, causing a reverse shift in the threshold voltage, thus enabling the erase operation. This application's SONOS memory based on an ultrathin ITO film, which provides electrons through a channel ultrathin ITO film, effectively reduces the tunneling barrier and optimizes device performance compared to traditional SONOS-type memories.

[0029] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A SONOS memory based on an ultra-thin ITO film, characterized in that it comprises: a substrate, which is a Si sheet having a SiO2 layer in which a groove is formed as a gate region; a gate formed in the gate region; a blocking layer / charge trapping layer laminated structure covering the gate; a tunneling layer formed on the charge trapping layer; an ultra-thin ITO film formed on the tunneling layer as a channel; a source and a drain formed on both sides of the ultra-thin ITO film, and the thickness of the ultra-thin ITO film is 0.7 nm to 10 nm.

2. The SONOS memory based on an ultra-thin ITO film according to claim 1, characterized in that the blocking layer is Al2O3, HfO2, ZrO2, Ta2O5.

3. The SONOS memory based on an ultra-thin ITO film according to claim 1, characterized in that the thickness of the blocking layer is 6 nm to 20 nm and the thickness of the charge trapping layer is 4 nm to 10 nm.

4. The SONOS memory based on an ultra-thin ITO film according to claim 1, characterized in that the thickness of the tunneling layer is 3 nm to 10 nm.

5. A method for manufacturing a SONOS memory based on an ultra-thin ITO film, characterized in that it comprises the following steps: preparing a Si sheet having a SiO2 layer as a substrate; forming a groove in the SiO2 layer as a gate region; forming a gate in the gate region; forming a blocking layer / charge trapping layer laminated structure covering the gate; forming a tunneling layer on the charge trapping layer; forming an ultra-thin ITO film on the tunneling layer as a channel; forming a source and a drain on both sides of the ultra-thin ITO film, and the thickness of the ultra-thin ITO film is 0.7 nm to 10 nm.

6. The method for manufacturing a SONOS memory based on an ultra-thin ITO film according to claim 5, characterized in that the blocking layer is Al2O3, HfO2, ZrO2, Ta2O5.

7. The method for manufacturing a SONOS memory based on an ultra-thin ITO film according to claim 5, characterized in that the thickness of the blocking layer is 6 nm to 20 nm and the thickness of the charge trapping layer is 4 nm to 10 nm.

8. The method for manufacturing a SONOS memory based on an ultra-thin ITO film according to claim 5, characterized in that the thickness of the tunneling layer is 3 nm to 10 nm. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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