Deep trench isolated bipolar transistor and method of manufacturing the same

Abstract

This invention provides a deep trench isolated bipolar transistor and its manufacturing method. By setting a heavily doped region of a first impurity type within a substrate of a first impurity type, a high recombination rate region is introduced along the transport path of excess carriers to the collector-substrate PN junction. This reduces the number of excess carriers collected by the collector region, effectively reducing the amplitude and duration of the instantaneous photocurrent, thereby significantly improving the resistance to transient dose rate effects of the deep trench isolated bipolar transistor. The heavily doped region of the first impurity type is located within the substrate, without altering the intrinsic structure and process flow of the device, and without affecting the conventional electrical parameters of the device. The formation method of the heavily doped region of the first impurity type is simple, requiring only one additional ion implantation process compared to conventional devices, and without the need for a separate metal contact, which helps reduce process complexity and manufacturing costs. Simultaneously, while improving the resistance to transient dose rate effects, it also improves the resistance to single-event effects.

Description

Technical Field

[0001] This invention relates to the field of radiation-hardened semiconductor device technology, and in particular to a deep trench isolated bipolar transistor and its manufacturing method. Background Technology

[0002] Semiconductor devices used in weaponry, nuclear facilities, and high-energy physics experimental setups are at risk of exposure to transient high-dose-rate gamma-ray and X-ray radiation. When gamma rays or X-rays enter a semiconductor device, they interact with the outer electrons of the semiconductor material's atoms, generating a large number of electron-hole pairs. When these excess carriers move to the vicinity of the PN junction in the semiconductor device, they are rapidly collected under the influence of the depletion region's electric field. Electrons are swept towards the N-type region, while holes are swept towards the P-type region. The large number of collected excess carriers leads to the generation of transient photocurrents, severely interfering with the normal operation of the device and potentially causing circuit and system malfunctions.

[0003] Meanwhile, vertical bipolar devices employing deep trench isolation structures can effectively isolate substrate coupling noise and leakage current between adjacent device components, thereby ensuring the signal quality of analog and RF modules, and thus have wide applications in mixed-signal circuits. However, such devices typically have a large-area collector-substrate (CS) PN junction, fabricated on a lightly doped substrate. On the one hand, the large-area CS PN junction significantly increases the collection area for excess carriers generated by instantaneous dose rate irradiation; on the other hand, the lightly doped substrate significantly increases the recombination lifetime of excess carriers, allowing excess carriers located far from the CS PN junction in the substrate to reach its vicinity and be collected through long-term diffusion, ultimately making such devices highly sensitive to instantaneous dose rate effects.

[0004] Therefore, appropriate reinforcement measures must be taken for bipolar transistors with deep trench isolation structures to improve their resistance to transient dose rate effects. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a deep trench isolated longitudinal bipolar transistor technology with a transient dose rate effect-hardened structure, so as to improve the transient dose rate radiation resistance performance of the deep trench isolated longitudinal bipolar transistor.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] A deep trench isolated bipolar transistor, comprising:

[0008] First impurity type substrate;

[0009] A heavily doped region of the first impurity type is disposed within a substrate of the first impurity type.

[0010] The second impurity type collector region is disposed on the first impurity type substrate and located above the first impurity type heavily doped region;

[0011] A deep trench isolation medium is arranged around the second impurity type collector region;

[0012] The first isolation medium is embedded in the second impurity type collector region and is disposed around the window area of ​​the second impurity type collector region;

[0013] The first impurity type base region is disposed on the second impurity type collector region and the first isolation medium, and is in contact with the window region of the second impurity type collector region;

[0014] The second isolation medium surrounds the window region of the first impurity type base region, and the bottom of the window region of the first impurity type base region is exposed.

[0015] The second impurity type emission region is disposed on the second isolation medium and contacts the window region of the first impurity type base region through the second isolation medium.

[0016] Optionally, the doping concentration of the heavily doped region of the first impurity type is higher than the doping concentration of the substrate of the first impurity type.

[0017] Optionally, the peak doping concentration of the heavily doped region of the first impurity type is 2 × 10⁻⁶. 19 cm -3 .

[0018] Optionally, a deep trench isolation medium surrounds and contacts the heavily doped region of the first impurity type.

[0019] Optionally, the heavily doped region of the first impurity type is positioned close to the PN junction formed by the substrate of the first impurity type and the collector region of the second impurity type.

[0020] Optionally, the first impurity type heavily doped region includes either a single-layer structure or a multilayer structure.

[0021] Optionally, when the first impurity type is acceptor type, the second impurity type is donor type; when the first impurity type is donor type, the second impurity type is acceptor type.

[0022] A method for manufacturing a deep trench isolated bipolar transistor, comprising:

[0023] Provide a substrate of the first impurity type;

[0024] A first impurity type heavily doped region is formed, and the first impurity type heavily doped region is disposed in a first impurity type substrate;

[0025] A second impurity type collector region is formed, which is disposed on the first impurity type substrate and located above the first impurity type heavily doped region;

[0026] A deep trench isolation medium is formed, which surrounds the heavily doped region of the first impurity type and the collector region of the second impurity type.

[0027] A first isolation medium is formed, which is embedded in the second impurity type collector region and is disposed around the window region of the second impurity type collector region;

[0028] A first impurity type base region is formed, which is disposed on the second impurity type collector region and the first isolation medium, and is in contact with the window region of the second impurity type collector region;

[0029] A second isolation medium is formed, which surrounds the window region of the first impurity type base region and exposes the window region of the first impurity type base region at its bottom;

[0030] A second impurity type emission region is formed, which is disposed on the second isolation medium and contacts the window region of the first impurity type base region through the second isolation medium.

[0031] Optionally, an ion implantation process and an annealing process are used to form a first impurity type heavily doped region, and an ion implantation process, an annealing process, and an epitaxial process are used to form a second impurity type collector region.

[0032] Alternatively, etching, oxidation, and deposition processes can be used to form the deep trench isolation medium.

[0033] As described above, the deep trench isolated bipolar transistor and its manufacturing method provided by the present invention have at least the following beneficial effects:

[0034] By setting a heavily doped region of the first impurity type within the substrate of the first impurity type, a high recombination rate region is introduced along the transport path of excess carriers to the collector-substrate PN junction, reducing the number of excess carriers collected by the collector region. This effectively reduces the amplitude and duration of the instantaneous photocurrent, thereby significantly improving the resistance to transient dose rate effects of the deep trench isolated bipolar transistor. The heavily doped region of the first impurity type is located within the substrate, without altering the intrinsic structure and process flow of the device, and does not affect the conventional electrical parameters of the device. The formation method of the heavily doped region of the first impurity type is simple, requiring only one additional ion implantation process compared to conventional devices, and without the need for a separate metal contact, which helps reduce process complexity and manufacturing costs. Simultaneously, while improving the resistance to transient dose rate effects, it also improves the resistance to single-event effects. Attached Figure Description

[0035] Figure 1The diagram shown is a schematic representation of a deep trench isolated bipolar transistor according to an embodiment of the present invention.

[0036] Figure 2 Displayed as Figure 1 A schematic diagram comparing the instantaneous collector photocurrent obtained from an instantaneous dose rate effect experiment of a medium-deep trench isolated bipolar transistor and a conventional deep trench isolated bipolar transistor.

[0037] Figure 3 The diagram shown is a structural schematic of a deep trench isolated bipolar transistor according to another embodiment of the present invention.

[0038] Figure 4 Displayed as Figure 3 A schematic diagram comparing the instantaneous collector photocurrent obtained from an instantaneous dose rate effect experiment of a medium-deep trench isolated bipolar transistor and a conventional deep trench isolated bipolar transistor.

[0039] Figure 5 The diagram shows the steps of the manufacturing method of the deep trench isolated bipolar transistor in this invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0042] like Figure 1 As shown, the present invention provides a deep trench isolated bipolar transistor, which includes:

[0043] First impurity type substrate 10;

[0044] A first impurity type heavily doped region 11 is disposed within a first impurity type substrate 10;

[0045] The second impurity type collector region 20 is disposed on the first impurity type substrate 10 and located above the first impurity type heavily doped region 11;

[0046] A deep trench isolation medium 30 is arranged around the second impurity type collector region 20;

[0047] The first isolation medium 31 is embedded in the second impurity type collector region 20 and is disposed around the window area of ​​the second impurity type collector region 20.

[0048] The first impurity type base region 12 is disposed on the second impurity type collector region 20 and the first isolation medium 31, and is in contact with the window region of the second impurity type collector region 20.

[0049] The second isolation medium 32 surrounds the window region of the first impurity type base region 12, and the bottom of the window region of the first impurity type base region 12 is exposed.

[0050] The second impurity type emission region 21 is disposed on the second isolation medium 32 and passes through the second isolation medium 32 to contact the window region of the first impurity type base region 12.

[0051] In detail, such as Figure 1 As shown, the doping concentration of the heavily doped region 11 of the first impurity type is higher than that of the substrate 10 of the first impurity type. In an optional embodiment of the present invention, the peak doping concentration of the heavily doped region 11 of the first impurity type is 2 × 10⁻⁶. 19 cm -3 .

[0052] In detail, such as Figure 1 As shown, the deep trench isolation medium 30 also surrounds and contacts the first impurity type heavily doped region 11; the first impurity type heavily doped region 11 is located close to the PN junction formed by the first impurity type substrate 10 and the second impurity type collector region 20.

[0053] In detail, such as Figure 1 As shown, the first impurity type heavily doped region 11 is a single-layer structure, that is, the first impurity type heavily doped region 11 has only one layer structure.

[0054] Wherein, when the first impurity type is acceptor type, the second impurity type is donor type; when the first impurity type is donor type, the second impurity type is acceptor type. Acceptor type impurities are P-type impurities, and donor type impurities are N-type impurities.

[0055] In an optional embodiment of the present invention, such as Figure 1As shown, the deep trench isolated bipolar transistor is a deep trench isolated vertical NPN type germanium-silicon bipolar transistor. The first impurity type substrate 10 is a P-type silicon substrate, the first impurity type heavily doped region 11 is a P-type heavily doped region, the second impurity type collector region 20 is an N-type collector region, the first impurity type base region 12 is a P-type germanium-silicon base region, and the second impurity type emitter region 21 is an N-type emitter region. The deep trench isolation dielectric 30, the first isolation dielectric 31, and the second isolation dielectric 32 are all dielectric layers (such as silicon oxide).

[0056] It should be noted that the above embodiments are illustrated using a P-type substrate as an example, but the substrate of the present invention can also be an N-type substrate, and the corresponding deep trench isolated bipolar transistor is a deep trench isolated vertical PNP type bipolar transistor, whose structure is similar and will not be described again here.

[0057] More in detail, such as Figure 1 As shown, by setting a first impurity type heavily doped region 11 in the first impurity type substrate 10, a high recombination rate region is introduced on the excess carrier transport path of the PN junction formed by the second impurity type collector region 20 and the first impurity type substrate 10. The first impurity type heavily doped region 11 with high recombination rate constitutes a radiation-hardened structure, which reduces the number of excess carriers collected by the second impurity type collector region 20, effectively reduces the amplitude of instantaneous photocurrent and shortens its duration, thereby significantly improving the resistance to instantaneous dose rate effects of the deep trench isolated bipolar transistor.

[0058] In detail, regarding such Figure 1 The deep trench isolated bipolar transistor shown here, with its radiation-hardened structure featuring a heavily doped region 11 of the first impurity type, will be demonstrated using, as shown below, as a demonstration of its technical effectiveness. Figure 1 A comparative experiment on the instantaneous dose rate effect was conducted between the hardened device with a heavily doped region 11 of the first impurity type and a conventional unhardened device without a heavily doped region 11 of the first impurity type. The results showed that at a dose rate of 1×10⁻⁶, the two devices achieved the same effect. 12 rad(Si)·s -1 The instantaneous photocurrent induced by a transient gamma ray irradiation lasting 500 ns is as follows: Figure 2 As shown. By Figure 2 It can be seen that the device with the radiation-hardened structure of the first impurity type heavily doped region 11 has a transient peak photocurrent that decreases by about 57% and a duration (10% peak current) that is shortened by about 25%, and its resistance to transient dose rate effects is significantly improved.

[0059] In another optional embodiment of the present invention, in order to further enhance the radiation-hardened structure of the first impurity type heavily doped region 11 against transient dose rate effects, such as... Figure 3As shown, the first impurity type heavily doped region 11 is a vertical double-layer structure, that is, the first impurity type heavily doped region 11 is a two-layer structure with vertical spacing.

[0060] In detail, regarding such Figure 3 The deep trench isolated bipolar transistor shown here, to demonstrate its technical effectiveness, will be as follows: Figure 3 A comparative experiment on the instantaneous dose rate effect was conducted between the hardened device with a heavily doped region 11 of the first impurity type and a conventional unhardened device without a heavily doped region 11 of the first impurity type. The results showed that at a dose rate of 1×10⁻⁶, the two devices achieved the same effect. 12 rad(Si)·s -1 The instantaneous photocurrent induced by a transient gamma ray irradiation lasting 500 ns is as follows: Figure 4 As shown. By Figure 4 It can be seen that the device with the radiation-hardened structure of the first impurity type heavily doped region 11 has a transient peak photocurrent that decreases by about 89% and a duration (10% peak current) that is shortened by about 25%, and its resistance to transient dose rate effects is further improved.

[0061] It is understood that the first impurity type heavily doped region 11 can also be a vertical three-layer structure, a four-layer structure, or other composite structures to further enhance the resistance of the first impurity type heavily doped region 11 to transient dose rate effects, and no limitation is made here.

[0062] Furthermore, the present invention also provides a method for manufacturing a deep trench isolated bipolar transistor, such as... Figure 5 As shown, it includes the following steps:

[0063] S1, Provide a substrate of the first impurity type;

[0064] S2. Form a first impurity type heavily doped region, wherein the first impurity type heavily doped region is disposed within a first impurity type substrate;

[0065] S3. A second impurity type collector region is formed, which is disposed on the first impurity type substrate and located above the first impurity type heavily doped region.

[0066] S4. A deep trench isolation medium is formed, which surrounds the first impurity type heavily doped region and the second impurity type collector region.

[0067] S5. A first isolation medium is formed, which is embedded in the second impurity type collector region and is disposed around the window region of the second impurity type collector region.

[0068] S6. A first impurity type base region is formed, which is disposed on the second impurity type collector region and the first isolation medium, and is in contact with the window region of the second impurity type collector region.

[0069] S7. A second isolation medium is formed, the second isolation medium is disposed around the window region of the first impurity type base region, and the bottom of the second isolation medium exposes the window region of the first impurity type base region;

[0070] S8. A second impurity type emission region is formed. The second impurity type emission region is disposed on the second isolation medium and contacts the window region of the first impurity type base region through the second isolation medium.

[0071] Specifically, in step S2, a first impurity type heavily doped region is formed by sequentially employing photolithography, ion implantation, and annealing processes; in step S3, a second impurity type collector region is formed by sequentially employing ion implantation, annealing, and epitaxial processes; in step S4, a deep trench isolation medium is formed by sequentially employing photolithography, etching, oxidation, deposition, oxidation, and etching processes; in step S5, a first isolation medium is formed by sequentially employing deposition, photolithography, etching, and oxidation processes, or by sequentially employing deposition, photolithography, etching, deposition, and chemical mechanical planarization processes; in step S6, a first impurity type base region is formed by sequentially employing epitaxial processes, photolithography, etching, deposition, and ion implantation processes; in step S7, a second isolation medium is formed by sequentially employing deposition, photolithography, and etching processes, or by sequentially employing deposition, photolithography, and etching processes; and in step S8, a second impurity type emitter region is formed by sequentially employing deposition, photolithography, and etching processes.

[0072] The above-mentioned processes are conventional processes and can be referred to in existing technologies, so they will not be described in detail here. At the same time, it should be noted that the order and combination of the steps of the above series of processes can be slightly modified according to the actual situation, and there are many other different ways to manufacture deep trench isolated bipolar transistors, not limited to this. The present invention wants to emphasize that the first impurity type heavily doped region is formed in the first impurity type substrate, and other aspects are not limited.

[0073] In summary, the deep trench isolated bipolar transistor and its manufacturing method provided by this invention introduce a high recombination rate region on the excess carrier transport path of the collector-substrate PN junction by setting a first impurity type heavily doped region within a first impurity type substrate. This reduces the number of excess carriers collected by the collector region, effectively reducing the amplitude and duration of the instantaneous photocurrent, thereby significantly improving the resistance to transient dose rate effects of the deep trench isolated bipolar transistor. The first impurity type heavily doped region is located in the substrate, without changing the intrinsic region structure and process flow of the device, and without affecting the conventional electrical parameters of the device. The formation method of the first impurity type heavily doped region is simple, requiring only one additional ion implantation process compared to conventional devices, and without the need for a separate metal contact, which helps to reduce process complexity and manufacturing costs. At the same time, while improving the resistance to transient dose rate effects, it also improves the resistance to single-event effects.

[0074] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A deep trench isolated bipolar transistor, characterized by, include: First impurity type substrate; A heavily doped region of the first impurity type is disposed within a substrate of the first impurity type. The second impurity type collector region is disposed on the first impurity type substrate and located above the first impurity type heavily doped region; A deep trench isolation medium is arranged around the second impurity type collector region; The first isolation medium is embedded in the second impurity type collector region and is disposed around the window area of ​​the second impurity type collector region; The first impurity type base region is disposed on the second impurity type collector region and the first isolation medium, and is in contact with the window region of the second impurity type collector region; The second isolation medium surrounds the window region of the first impurity type base region, and the bottom of the window region of the first impurity type base region is exposed. The second impurity type emission region is disposed on the second isolation medium and contacts the window region of the first impurity type base region through the second isolation medium; The first impurity type heavily doped region is located close to the PN junction formed by the first impurity type substrate and the second impurity type collector region.

2. The STI bipolar transistor of claim 1, wherein, The doping concentration of the heavily doped region of the first impurity type is higher than that of the substrate of the first impurity type.

3. The STI bipolar transistor of claim 2, wherein, The peak doping concentration of the first impurity type heavily doped region is 2 x 1019cm-3. 19 cm -3 .

4. The STI bipolar transistor of claim 1, wherein, The deep trench isolation medium surrounds and contacts the heavily doped region of the first impurity type.

5. The STI bipolar transistor of claim 1, wherein, The first type of impurity heavily doped region includes one of the single-layer structure and the multilayer structure.

6. The STI bipolar transistor according to any one of claims 1 to 5, wherein When the first impurity type is acceptor type, the second impurity type is donor type; when the first impurity type is donor type, the second impurity type is acceptor type.

7. A method of manufacturing a deep trench isolated bipolar transistor, characterized by, include: Provide a substrate of the first impurity type; A first impurity type heavily doped region is formed, and the first impurity type heavily doped region is disposed in a first impurity type substrate; A second impurity type collector region is formed, which is disposed on the first impurity type substrate and located above the first impurity type heavily doped region; A deep trench isolation medium is formed, which surrounds the heavily doped region of the first impurity type and the collector region of the second impurity type. A first isolation medium is formed, which is embedded in the second impurity type collector region and is disposed around the window region of the second impurity type collector region; A first impurity type base region is formed, which is disposed on the second impurity type collector region and the first isolation medium, and is in contact with the window region of the second impurity type collector region; A second isolation medium is formed, which surrounds the window region of the first impurity type base region and exposes the window region of the first impurity type base region at its bottom; A second impurity type emission region is formed, which is disposed on the second isolation medium and contacts the window region of the first impurity type base region through the second isolation medium.

8. The method of manufacturing a deep-trench-isolated bipolar transistor according to claim 7, wherein The first type of heavily doped region is formed by ion implantation and annealing, and the second type of collector region is formed by ion implantation, annealing and epitaxy.

9. The method of manufacturing a deep-trench-isolated bipolar transistor according to claim 8, wherein Deep trench isolation media are formed by etching, oxidation and deposition processes.

Images