Semiconductor devices and electronic devices

Abstract

The present application provides a semiconductor device and an electronic device, wherein the semiconductor device includes an insulating substrate and a thin film transistor layer located on the insulating substrate, the thin film transistor layer includes a first active layer arranged on the insulating substrate and a first insulating layer located on the first active layer, and the first insulating layer forms a boss; wherein the present application further includes a second active layer and a third active layer arranged on both side walls and the upper surface of the boss by providing the thin film transistor layer, one end of the first active layer is connected to the second active layer, and the other end of the first active layer is connected to the third active layer, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, and reducing the power consumption; and further reducing the area of the thin film transistor, thereby improving the integration of the electronic device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device and an electronic device. Background Art

[0002] At present, flat-panel display devices such as liquid crystal semiconductor devices (LCD) and organic light-emitting diodes (OLED) mobile terminals are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc. due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices.

[0003] In the prior art, it is known that integrating IC (Integrated Circuit) circuits such as pixels, drivers, multiplexing, control, and logic on a glass substrate (system on glass, SOG) can improve the integration of semiconductor devices and reduce dependence on IC chips. In order to achieve SOG, it is necessary to improve the integration, maximum operating frequency, and current density of existing thin-film transistors (TFTs). Since the electrical performance of a thin-film transistor when turned on is related to the portion of the active layer corresponding to the source and drain electrodes (i.e., the channel length of the active layer), in order to achieve the above effects, the thin-film transistor needs to have a shorter channel length and a smaller volume. However, in the manufacturing process of traditional thin-film transistors, when an "I"-type active layer is produced on a substrate using existing exposure equipment, the minimum size of the mask pattern is generally greater than 2μm. Therefore, in the prior art, it is difficult to achieve a short channel of the thin-film transistor. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor device and an electronic device to alleviate the deficiencies in the related art.

[0005] To achieve the above functions, the technical solutions provided in the embodiments of the present application are as follows:

[0006] An embodiment of the present application provides a semiconductor device, including:

[0007] Insulation substrate;

[0008] A thin film transistor layer is provided on the insulating substrate, and the thin film transistor layer includes:

[0009] A first active layer is provided on the insulating substrate;

[0010] a first insulating layer disposed on the first active layer, wherein the first insulating layer is formed with a boss;

[0011] The thin film transistor layer further includes a second active layer and a third active layer arranged on both side walls and the upper surface of the boss, one end of the first active layer is connected to the second active layer, and the other end of the first active layer is connected to the third active layer.

[0012] In the semiconductor device provided in the embodiment of the present application, the second active layer includes a first conductor portion located on the upper surface of the boss, and the third active layer includes a second conductor portion located on the upper surface of the boss, wherein the first conductor portion and the second conductor portion are arranged at intervals.

[0013] In the semiconductor device provided in an embodiment of the present application, in a direction perpendicular to the insulating substrate, the orthographic projection of the first conductor portion is located within the orthographic projection of the first active layer, the orthographic projection of the second conductor portion is located within the orthographic projection of the first active layer, and the orthographic projection of the first conductor portion and the orthographic projection of the second conductor portion do not overlap with each other.

[0014] In the semiconductor device provided in the embodiment of the present application, the thin film transistor layer comprises a first metal layer located on the upper surface of the boss, and the first metal layer includes a source connected to the first conductor portion and a drain connected to the second conductor portion.

[0015] In the semiconductor device provided in an embodiment of the present application, the source includes a first sub-portion and a second sub-portion, an orthographic projection of the first sub-portion on the insulating substrate overlaps with an orthographic projection of the first conductor portion on the insulating substrate, and an orthographic projection of the second sub-portion on the insulating substrate does not overlap with an orthographic projection of the first conductor portion on the insulating substrate;

[0016] The drain includes a third sub-portion and a fourth sub-portion, the orthographic projection of the third sub-portion on the insulating base overlaps with the orthographic projection of the second conductor portion on the insulating base, and the orthographic projection of the fourth sub-portion on the insulating base does not overlap with the orthographic projection of the second conductor portion on the insulating base.

[0017] In the semiconductor device provided in the embodiment of the present application, the semiconductor device includes an electrode layer located on a side of the thin film transistor layer away from the insulating substrate, and the electrode layer is connected to the second sub-section, or the electrode layer is connected to the fourth sub-section.

[0018] In the semiconductor device provided in the embodiment of the present application, the source is located between the first conductor portion and the boss, and the drain is located between the second conductor portion and the boss.

[0019] In the semiconductor device provided in the embodiment of the present application, the thin film transistor layer includes a channel located between the first active layer and the first conductor portion, and the length of the channel and the thickness of the boss satisfy the following relationship:

[0020]

[0021] Wherein, L represents the length of the channel, H represents the height of the boss, and α represents the angle between the side wall and the lower surface of the boss.

[0022] In the semiconductor device provided in the embodiment of the present application, the angle α between the sidewall and the lower surface of the boss is greater than or equal to 45 degrees and less than 90 degrees.

[0023] In the semiconductor device provided in the embodiment of the present application, in the direction perpendicular to the insulating substrate, the length of the channel is greater than or equal to 100 angstroms and less than or equal to 10,000 angstroms, and the width of the channel is greater than or equal to 300 angstroms and less than or equal to 100,000 angstroms.

[0024] In the semiconductor device provided in an embodiment of the present application, the thin film transistor layer includes a second metal layer located on the side of the first insulating layer away from the insulating substrate, and in a direction perpendicular to the insulating substrate, the second metal layer covers the first active layer, the second active layer and the third active layer.

[0025] In the semiconductor device provided in an embodiment of the present application, the thin film transistor layer includes a second insulating layer located between the second metal layer and the first insulating layer, and in a direction perpendicular to the insulating substrate, the second insulating layer covers the first active layer, the second active layer, and the third active layer;

[0026] Wherein, on the upper surface of the boss, the second insulating layer includes a groove located between the second active layer and the third active layer, and the second metal layer fills the groove.

[0027] In the semiconductor device provided in the embodiment of the present application, the thin film transistor layer includes a plurality of thin film transistors, the first insulating layer includes a plurality of bosses, one thin film transistor is arranged corresponding to one boss, or a plurality of thin film transistors are arranged corresponding to one boss.

[0028] In the semiconductor device provided in the embodiment of the present application, the cross section of the sidewall of the boss in a direction perpendicular to the insulating base is a straight line or an arc.

[0029] In the semiconductor device provided in the embodiment of the present application, the semiconductor device includes a light-shielding layer located between the insulating substrate and the first active layer, the second active layer includes a first active segment located on the side wall, and the third active layer includes a second active segment located on the side wall, wherein the orthographic projection of the light-shielding layer on the insulating substrate covers the orthographic projection of the first active segment on the substrate, and the orthographic projection of the light-shielding layer on the insulating substrate covers the orthographic projection of the second active segment on the substrate.

[0030] An embodiment of the present application provides an electronic device, which includes any of the semiconductor devices described above.

[0031] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a semiconductor device and an electronic device, wherein the semiconductor device includes an insulating substrate and a thin film transistor layer arranged on the insulating substrate, the thin film transistor layer includes a first active layer arranged on the insulating substrate, and a first insulating layer located on the first active layer, and the first insulating layer forms a boss; wherein, the embodiments of the present application further include a second active layer and a third active layer arranged on the two side walls and the upper surface of the boss by setting the thin film transistor layer, one end of the first active layer is connected to the second active layer, and the other end of the first active layer is connected to the third active layer, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, and reducing the power consumption; and further reducing the area of the thin film transistor, thereby improving the integration of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a top cross-sectional view of a conventional display panel;

[0034] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the AA′ direction;

[0035] Figure 3 for Figure 1 Schematic diagram of the cross-sectional structure along the BB′ direction;

[0036] Figure 4 A top cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0037] Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the AA′ direction;

[0038] Figure 6 for Figure 4 Schematic diagram of the first cross-sectional structure along the BB′ direction;

[0039] Figure 7 for Figure 4 Schematic diagram of the second cross-sectional structure along the BB′ direction;

[0040] Figure 8 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0041] Figures 9A to 9L for Figure 8 Structural process flow chart for semiconductor device manufacturing. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0043] The embodiments of the present application provide a semiconductor device and an electronic device. These are described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0044] See also Figures 4 to 9L , embodiments of the present application provide a semiconductor device and an electronic device, wherein the semiconductor device includes:

[0045] Insulation substrate;

[0046] A thin film transistor layer is provided on the insulating substrate, and the thin film transistor layer includes:

[0047] A first active layer is provided on the insulating substrate;

[0048] a first insulating layer, disposed on the first active layer;

[0049] The thin film transistor layer further includes a second active layer and a third active layer arranged on both side walls and the upper surface of the boss, one end of the first active layer is connected to the second active layer, and the other end of the first active layer is connected to the third active layer.

[0050] See also Figure 1 、 Figure 2 and Figure 3 ;in, Figure 1 is a top cross-sectional view of a conventional display panel; Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the AA′ direction; Figure 3 for Figure 1 It should be noted that this embodiment does not impose any specific restrictions on the structure of the existing display panel. The following description will only take the existing display panel as a liquid crystal display (LCD) panel as an example.

[0051] The existing display panel includes a first substrate 100 and a second substrate (not shown in the figure) arranged relatively to each other, and a liquid crystal layer (not shown in the figure) arranged between the first substrate 100 and the second substrate. The first substrate 100 includes an insulating base 10, a light-shielding layer 20, a buffer layer 30, a thin-film transistor layer 40, a flat layer 60, a common electrode 71, a passivation layer 80 and a pixel electrode 72 arranged in a stacked manner. The thin-film transistor layer 40 includes an active layer 41, a first insulating layer 44, a gate 47A, an interlayer insulating layer 50, a source 45A and a drain 45B stacked in sequence on the insulating base 10; wherein the thin-film transistor layer 40 includes a plurality of thin-film transistors 40A arranged in a matrix, and one thin-film transistor 40A is correspondingly located in a sub-pixel area.

[0052] At present, it is known that integrating IC (Integrated Circuit) circuits such as pixels, driving, multiplexing, control, and logic on a glass substrate (system on glass, SOG) can improve the integration of display panels and reduce dependence on IC chips; and in order to achieve SOG, it is necessary to improve the integration, maximum operating frequency, and current density of existing thin film transistors (TFTs). Among them, since the electrical performance of the thin film transistor when it is turned on is related to the part of the active layer corresponding to the source and the drain (that is, the channel length of the active layer), in order to achieve the above effect, the thin film transistor needs to have a shorter channel length and a smaller volume; however, in the manufacturing process of traditional thin film transistors, when the "I" type active layer is manufactured on the substrate through existing exposure equipment, the minimum size of its mask pattern is generally greater than 2μm. Therefore, in the existing technology, it is difficult to achieve short channel of the thin film transistor 40A.

[0053] It can be understood that the embodiment of the present application, by setting the thin film transistor layer, also includes a second active layer and a third active layer arranged on the two side walls and the upper surface of the boss, one end of the first active layer is connected to the second active layer, and the other end of the first active layer is connected to the third active layer, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, reducing power consumption, and further reducing the area of the thin film transistor, thereby improving the integration of the electrode device.

[0054] The technical solution of this application is now described in conjunction with specific embodiments.

[0055] In one embodiment, please combine Figure 4 、 Figure 5 and Figure 6 ;in, Figure 4 A top cross-sectional view of a semiconductor device provided in an embodiment of the present application; Figure 5 for Figure 4 Schematic diagram of the cross-sectional structure along the AA′ direction;

[0056] Figure 6 for Figure 4 Schematic diagram of the first cross-sectional structure along the BB′ direction.

[0057] In this embodiment, the semiconductor device 1 includes an insulating substrate 10 and a thin film transistor layer 40 disposed on the insulating substrate 10. The insulating substrate 10 may include a rigid substrate or a flexible substrate. This embodiment does not impose any specific restrictions on the material of the insulating substrate 10.

[0058] The thin film transistor layer 40 includes a first active layer 41A arranged on the insulating substrate 10, and a first insulating layer 44 arranged on the first active layer 41A, and the first insulating layer 44 is formed with a boss 44A; wherein, the thin film transistor layer 40 also includes a second active layer 42A and a third active layer 43A arranged on the two side walls 441B and the upper surface 441A of the boss 44A, one end of the first active layer 41A is connected to the second active layer 42A, and the other end of the first active layer 41A is connected to the third active layer 43A.

[0059] Furthermore, the second active layer 42A includes a first conductor portion 422A located on the upper surface 441A of the boss 44A, and the third active layer 43A includes a second conductor portion 432A located on the upper surface 441A of the boss 44A, wherein the first conductor portion 422A and the second conductor portion 432A are arranged at intervals; specifically, in a direction perpendicular to the insulating substrate 10, the orthographic projection of the first conductor portion 422A is located within the orthographic projection of the first active layer 41A, and the orthographic projection of the second conductor portion 432A is located within the orthographic projection of the first active layer 41A, and the orthographic projection of the first conductor portion 422A and the orthographic projection of the second conductor portion 432A do not overlap with each other, thereby avoiding contact between the first conductor portion 422A and the second conductor portion 432A.

[0060] In this embodiment, the second active layer 42A includes a first active segment 421A located on the sidewall 441B and the first conductor portion 422A located on the upper surface 441A of the boss 44A. One end of the first active segment 421A is connected to the first active layer 41A, and the other end of the first active segment 421A is connected to the first conductor portion 422A. The third active layer 43A includes a second active segment 431A located on the sidewall 441B and the second conductor portion 432A located on the upper surface 441A of the boss 44A. One end of the second active segment 431A is connected to the first active layer 41A, and the other end of the second active segment 431A is connected to the second conductor portion 432A. In a direction perpendicular to the insulating substrate 10, the first active segment 421A and the second active segment 431A have the same projection pattern, and the first conductor portion 422A and the second conductor portion 432A have the same projection pattern.

[0061] It should be noted that the materials of the first active layer 41A, the first active section 421A and the second active section 431A include but are not limited to amorphous silicon, polycrystalline silicon, or oxide semiconductor materials. The first conductor portion 422A and the second conductor portion 432A can be made of silicide or polycrystalline silicon doped with n-type impurities at a high concentration. The first insulating layer 44 includes but is not limited to a liner layer. The materials of the first insulating layer 44 include but are not limited to a single layer of silicon nitride (Si3N4), a single layer of silicon dioxide (SiO2), a single layer of silicon oxynitride (SiON) x ), or a double-layer structure of the above film layers, which is not specifically limited in this embodiment.

[0062] In this embodiment, the thin film transistor layer 40 includes a first metal layer 45 located on the upper surface 441A of the boss 44A, and the first metal layer 45 includes a source 45A connected to the first conductor portion 422A and a drain 45B connected to the second conductor portion 432A. Specifically, in this embodiment, the first metal layer 45 is stacked with the first conductor portion 422A and the second conductor portion 432A, but this embodiment does not impose specific restrictions on the positional relationship between the first metal layer 45 and the first conductor portion 422A and the second conductor portion 432A; preferably, in this embodiment, the source 45A is located between the first conductor portion 422A and the boss 44A, and the drain 45B is located between the second conductor portion 432A and the boss 44A.

[0063] Furthermore, the source electrode 45A includes a first sub-portion 451A and a second sub-portion 452A, the orthographic projection of the first sub-portion 451A on the insulating substrate 10 overlaps with the orthographic projection of the first conductor portion 422A on the insulating substrate 10, and the orthographic projection of the second sub-portion 452A on the insulating substrate 10 does not overlap with the orthographic projection of the first conductor portion 422A on the insulating substrate 10; the drain electrode 45B includes a third sub-portion 451B and a fourth sub-portion 452B, the orthographic projection of the third sub-portion 451B on the insulating substrate 10 overlaps with the orthographic projection of the first conductor portion 422A on the insulating substrate 10. The orthographic projection of the second conductor portion 432A on the insulating base 10 overlaps, and the orthographic projection of the fourth sub-portion 452B on the insulating base 10 does not overlap with the orthographic projection of the second conductor portion 432A on the insulating base 10; that is, in this embodiment, the orthographic projection of the first conductor portion 422A on the insulating base 10 is located within the orthographic projection of the source 45A on the insulating base 10, and the orthographic projection of the second conductor portion 432A on the insulating base 10 is located within the orthographic projection of the drain 45B on the insulating base 10.

[0064] It can be understood that, in this embodiment, the orthographic projection of the first sub-portion 451A on the insulating substrate 10 is overlapped with the orthographic projection of the first conductor portion 422A on the insulating substrate 10, and the orthographic projection of the third sub-portion 451B on the insulating substrate 10 is overlapped with the orthographic projection of the second conductor portion 432A on the insulating substrate 10. Compared with the technical solution in the prior art in which the source 45A and the drain 45B contact the active layer through a via, the contact area between the source 45A and the second active layer 42A, and the contact area between the drain 45B and the third active layer 43A is increased, thereby reducing the contact resistance and improving the stability of signal transmission.

[0065] In this embodiment, the thin film transistor layer 40 includes a second metal layer 47 located on the side of the first insulating layer 44 away from the insulating substrate 10, and in a direction perpendicular to the insulating substrate 10, the second metal layer 47 covers the first active layer 41A, the second active layer 42A and the third active layer 43A; preferably, the second metal layer 47 includes a gate 47A, and the first active layer 41A, the first insulating layer 44, the source 45A, the drain 45B, the second active layer 42A, the third active layer 43A and the gate 47A are stacked in sequence on the insulating substrate 10.

[0066] Furthermore, the thin film transistor layer 40 includes a second insulating layer 46 located between the second metal layer 47 and the first insulating layer 44, and in a direction perpendicular to the insulating substrate 10, the second insulating layer 46 covers the first active layer 41A, the second active layer 42A and the third active layer 43A; wherein, on the upper surface 441A of the boss 44A, the second insulating layer 46 includes a groove 461 located between the second active layer 42A and the third active layer 43A, and the second metal layer 47 fills the groove 461; it can be understood that in this embodiment, by being arranged on the upper surface 441A of the boss 44A, the second insulating layer 46 includes a groove 461 located between the second active layer 42A and the third active layer 43A, and the second metal layer 47 fills the groove 461, thereby avoiding the gate 47A, the source 45A and the drain 45B from contacting on the upper surface 441A of the boss 44A, thereby affecting the electrical characteristics of the thin film transistor layer 40.

[0067] Furthermore, in this embodiment, the second insulating layer 46 covers the first active layer 41A, the second active layer 42A and the third active layer 43A, thereby blocking water and oxygen and insulating the first active layer 41A, the second active layer 42A and the third active layer 43A; this embodiment takes the second insulating layer 46 as the gate 47A insulating layer as an example to illustrate the technical solution of the present application.

[0068] In this embodiment, the thin film transistor layer 40 includes at least one thin film transistor 40A, and the thin film transistor 40A includes the first active layer 41A, the first insulating layer 44, and the second active layer 42A and the third active layer 43A arranged on the two side walls 441B and the upper surface 441A of the boss 44A; it can be understood that in this embodiment, the second active layer 42A includes the first active section 421A and the first conductor portion 422A, and the third active layer 43A includes the second active section 431A and the second conductor portion 432A. The first active section 421A connects the first active layer 41A and the first conductor portion 422A, the second active section 431A connects the first active layer 41A and the second conductor portion 432A, the first conductor portion 422A is connected to the source 45A, and the second conductor portion 432A is connected to the drain 45B, thereby forming the thin film transistor 40A.

[0069] It should be noted that the first active layer 41A, the first insulating layer 44, the first metal layer 45, the second active layer 42A, the third active layer 43A and the second metal layer 47 are stacked in sequence on the insulating substrate 10, that is, in this embodiment, the thin film transistor 40A is a top-gate thin film transistor 40A. It is only used for illustration. This embodiment does not impose any specific restrictions on the type of the thin film transistor 40A. It can be understood that this embodiment arranges the first active layer 41A, the first insulating layer 44, the first metal layer 45, the second active layer 42A, the third active layer 43A and the second metal layer 47 into a stacked structure perpendicular to the direction of the insulating substrate 10. Compared with the prior art, this reduces the area occupied by the thin film transistor 40A and improves the aperture ratio.

[0070] Furthermore, in this embodiment, the thin film transistor layer 40 includes a plurality of thin film transistors 40A arranged in a matrix, the first insulating layer 44 includes a plurality of the bosses 44A, one thin film transistor 40A is set corresponding to one boss 44A, or multiple thin film transistors 40A are set corresponding to one boss 44A; preferably, this embodiment uses the setting of one thin film transistor 40A corresponding to one boss 44A as an example to illustrate the technical solution of the present application.

[0071] In this embodiment, the thin film transistor layer 40 includes a channel between the first active layer 41A and the first conductor portion 422A. The length of the channel and the thickness of the boss 44A satisfy the following relationship:

[0072]

[0073] Wherein, L represents the length of the channel, H represents the height of the boss 44A, and α represents the angle between the side wall 441B and the lower surface 441C of the boss 44A.

[0074] Furthermore, the cross-section of the side wall 441B of the boss 44A in the direction perpendicular to the insulating base 10 is a straight line or an arc; preferably, in this embodiment, the cross-section of the side wall 441B of the boss 44A in the direction perpendicular to the insulating base 10 is a straight line, and the cross-section of the boss 44A is trapezoidal. The boss 44A includes an upper surface 441A connecting the two side walls 441B and away from the insulating base 10, and a lower surface 441C connecting the two side walls 441B and close to the insulating base 10. The angle α between the side wall 441B and the lower surface 441C of the boss 44A is greater than or equal to 45 degrees and less than 90 degrees.

[0075] Specifically, in this embodiment, the direction in which the first conductor portion 422A points to the second conductor portion 432A is a first direction X, and the extension direction of the boss 44A is a second direction Y. The first direction X and the second direction Y form a predetermined angle, and a plane defined by the first direction X and the second direction Y is parallel to the substrate. In the second direction Y, the thickness of the boss 44A ranges from 100 angstroms to 10,000 angstroms, the length of the channel is greater than or equal to 100 angstroms and less than or equal to 10,000 angstroms, and the width of the channel is greater than or equal to 300 angstroms and less than or equal to 100,000 angstroms.

[0076] It should be noted that, in this embodiment, there is no restriction on the range of the preset angle, and the directions of the first direction X and the second direction Y. However, for the convenience of description, this embodiment is illustrated by taking the preset angle as 90°, the first direction as direction X, and the second direction as direction Y as an example.

[0077] It can be understood that in this embodiment, the channel between the source 45A and the drain 45B is composed of the first active section 421A and the second active section 431A located on the two side walls 441B of the boss 44A, that is, the length of the channel is determined by the length of the two side walls 441B of the boss 44A and the angle α between the side walls 441B and the lower surface 441C of the boss 44A, and the width of the channel is determined by the sum of the width of the orthographic projection of the first active section 421A on the boss 44A and the width of the orthographic projection of the second active section 431A on the boss 44A. Therefore, despite the limitations of the exposure equipment, since the length of the two side walls 441B of the boss 44A and the angle α between the side walls 441B and the lower surface 441C of the boss 44A can be controlled, the length of the channel can be controlled independently of the exposure equipment, that is, the short channel of the thin film transistor 40A is achieved.

[0078] Continuing from the above, in this embodiment, the second active layer 42A includes a first conductor portion 422A located on the upper surface 441A of the boss 44A, and the third active layer 43A includes a second conductor portion 432A located on the upper surface 441A of the boss 44A, wherein the first conductor portion 422A and the second conductor portion 432A are arranged at intervals; specifically, in a direction perpendicular to the insulating substrate 10, the orthographic projection of the first conductor portion 422A is located within the orthographic projection of the first active layer 41A, and the orthographic projection of the second conductor portion 432A is located within the orthographic projection of the first active layer 41A, and the orthographic projection of the first conductor portion 422A and the orthographic projection of the second conductor portion 432A do not overlap with each other, thereby reducing the channel length; and, under the condition that the width of the channel is constant, shortening the channel length can enable the thin film transistor 40A to have a larger aspect ratio, thereby having a larger on-state current, and reducing the power consumption of the thin film transistor 40A.

[0079] It should be noted that the trapezoidal cross-sectional shape of the boss 44A is only used for illustration. For example, in another embodiment, the cross-sectional shape of the side wall 441B of the boss 44A in the direction perpendicular to the insulating base 10 is an arc, and the cross-sectional shape of the boss 44A is at least one of a circle or an ellipse.

[0080] In this embodiment, the semiconductor device 1 includes an electrode layer 70 located on the side of the thin film transistor layer 40 away from the insulating substrate 10, and the electrode layer 70 is connected to the second sub-section 452A, or the electrode layer 70 is connected to the fourth sub-section 452B; preferably, in this embodiment, the electrode layer 70 is connected to the fourth sub-section 452B.

[0081] Furthermore, in this embodiment, the semiconductor device 1 also includes a third insulating layer 2 on the side of the thin film transistor layer 40 away from the insulating substrate 10, and the electrode layer 70 is located on the side of the third insulating layer 2 away from the thin film transistor layer 40; specifically, the third insulating layer 2 includes an interlayer insulating layer 50 located on the side of the thin film transistor layer 40 away from the insulating substrate 10, a flat layer 60 located on the side of the interlayer insulating layer 50 away from the thin film transistor layer 40, and a passivation layer 80 located on the side of the flat layer 60 away from the interlayer insulating layer 50, and the electrode layer 70 includes a first electrode 71 and a second electrode 72, the first electrode 71 is located between the flat layer 60 and the passivation layer 80, and the second electrode 72 is located on the side of the passivation layer 80 away from the flat layer 60; preferably, the first electrode 71 is a common electrode, and the second electrode 72 is a pixel electrode.

[0082] A first via hole 51 passing through the second insulating layer 46 and the third insulating layer 2 is provided in the semiconductor device 1. The first via hole 51 is located above the drain 45B. Specifically, the first via hole 51 passes through the second insulating layer 46, the interlayer insulating layer 50 and the flat layer 60. The passivation layer 80 is provided with a second via hole 81 exposing a portion of the drain 45B. The second electrode 72 is connected to the drain 45B through the first via hole 51 and the second via hole 81. In the direction perpendicular to the insulating substrate 10, the aperture of the second via hole 81 is smaller than the aperture of the first via hole 51. In the first via hole 51, the passivation layer 80 covers the inner wall of the flat layer 60, thereby blocking water and oxygen and insulating the flat layer 60.

[0083] It can be understood that, in this embodiment, the orthographic projection of the fourth sub-section 452B on the insulating substrate 10 and the orthographic projection of the second conductor section 432A on the insulating substrate 10 do not overlap with each other, that is, in this embodiment, along the AA′ direction, the length of the second conductor section 432A is greater than the length of the second semiconductor section, wherein the first via 51 and the second via 81 are located on the fourth sub-section 452B, thereby facilitating the connection between the drain 45B and the electrode layer 70.

[0084] It should be noted that, in this embodiment, the third insulating layer 2 includes the interlayer insulating layer 50 , the planarizing layer 60 and the passivation layer 80 for illustration only. This embodiment does not impose any specific limitation on the film structure of the third insulating layer 2 .

[0085] In this embodiment, the thin film transistor layer 40 also includes a control circuit (not shown in the figure), and the control circuit includes a plurality of thin film transistors 40A, wherein the control circuit includes but is not limited to IC circuits such as pixels, driving, multiplexing and logic. It can be understood that the embodiment of the present application arranges the thin film transistor layer 40 to include a second active layer 42A and a third active layer 43A arranged on the two side walls 441B and the upper surface 441A of the boss 44A, one end of the first active layer 41A is connected to the second active layer 42A, and the other end of the first active layer 41A is connected to the third active layer 43A, thereby reducing the channel length, reducing the short channel effect, increasing the on-state current, reducing power consumption, and thus improving the integration of the thin film transistor 40A.

[0086] In this embodiment, the semiconductor device 1 further includes a light-shielding layer 20 and a buffer layer 30 stacked on the insulating substrate 10, wherein the orthographic projection of the light-shielding layer 20 on the insulating substrate 10 covers the orthographic projection of the first active segment 421A on the substrate, and the orthographic projection of the light-shielding layer 20 on the insulating substrate 10 covers the orthographic projection of the second active segment 431A on the substrate. It can be understood that the light-shielding layer 20 can block the light directed to the first active layer 41A and the second active layer 42A, thereby reducing the conduction of photogenerated carriers generated by light irradiating the first active layer 41A and the second active layer 42A. The leakage current increases, thereby maintaining the stability of the semiconductor device 1 during operation; further, the light-shielding layer 20 includes a first light-shielding sub-layer 21 and a second light-shielding sub-layer 22 arranged at intervals, the first light-shielding sub-layer 21 is arranged corresponding to the first active segment 421A, and the orthographic projection of the first light-shielding sub-layer 21 on the insulating substrate 10 covers the orthographic projection of the first active segment 421A on the insulating substrate 10, and the second light-shielding sub-layer 22 is arranged corresponding to the second active segment 431A, and the orthographic projection of the second light-shielding sub-layer 22 on the insulating substrate 10 covers the orthographic projection of the second active segment 431A on the insulating substrate 10.

[0087] In another embodiment, please combine Figure 4 、 Figure 5 and Figure 7 ;in, Figure 7 for Figure 4 Schematic diagram of the second cross-sectional structure along the BB′ direction.

[0088] In this embodiment, the structure of the semiconductor device is similar to / identical to that of the semiconductor device provided in the above embodiment. For details, please refer to the description of the semiconductor device in the above embodiment, which will not be repeated here. The only difference between the two is:

[0089] In this embodiment, the semiconductor device 1 also includes a bridging layer 91 located between the flat layer 60 and the passivation layer 80, a light-emitting device layer (not marked in the figure) located on the side of the passivation layer 80 away from the flat layer 60, and an encapsulation layer (not drawn in the figure) located on the side of the light-emitting device layer away from the passivation layer 80, the light-emitting device layer includes an anode 73, a light-emitting layer 93 and a cathode 94 stacked on the passivation layer 80, wherein the electrode layer 70 includes the anode 73.

[0090] Furthermore, the third insulating layer 2 includes an interlayer insulating layer 50 located on the side of the thin film transistor 40A4 away from the insulating substrate 10, a planar layer 60 located on the side of the interlayer insulating layer 50 away from the thin film transistor layer 40, and a pixel definition layer 92 located on the side of the planar layer 60 away from the interlayer insulating layer 50, a first opening (not marked in the figure) is opened on the pixel definition layer 92 to expose the anode 73, the light-emitting layer 93 is located in the opening, the light-emitting layer 93 is connected to the anode 73 through the opening, and the cathode 94 is connected to the light-emitting layer 93 through the opening.

[0091] A third via 52 is provided in the semiconductor device 1, passing through the second insulating layer 46 and the interlayer insulating layer 50. The bridging layer 91 is connected to the drain 45B through the third via 52. A second opening (not marked in the figure) is provided on the flat layer 60 to expose a portion of the bridging layer 91. The anode 73 is connected to the bridging layer 91 through the second opening, and the anode 73 is connected to the drain 45B through the bridging layer 91.

[0092] It can be understood that in this embodiment, the passivation layer 80, the bridging layer 91, the planar layer 60, the anode 73, the light-emitting layer 93, the cathode 94 and the encapsulation layer are conventional film layers in the prior art, and this embodiment will not go into details about them.

[0093] The present application also provides a method for manufacturing a semiconductor device 1. Figure 4 、 Figure 8 and 9A to 9H ;in, Figure 8 A flowchart of a method for manufacturing a semiconductor device 1 according to an embodiment of the present application; 9A to 9I for Figure 8 Structural process flow chart for semiconductor device manufacturing.

[0094] In this embodiment, the method for manufacturing the semiconductor device 1 includes the following steps:

[0095] Step S100: providing an insulating substrate 10, and a light shielding layer 20 and a buffer layer 30 sequentially formed on the insulating substrate 10, such as Figure 9A shown.

[0096] Among them, when the insulating substrate 10 is a rigid substrate, the material can be metal or glass. When the insulating substrate 10 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, silicone resin, polyimide resin, and polyamide resin.

[0097] The material of the light shielding layer 20 includes but is not limited to metal materials, and the metal materials include but are not limited to one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the material of the buffer layer 30 includes but is not limited to single-layer silicon nitride (Si3N4), single-layer silicon dioxide (SiO2), single-layer silicon oxynitride (SiON x ), or a double-layer structure of the above film layers.

[0098] Step S200: forming a thin film transistor layer 40 on the insulating substrate 10, wherein the thin film transistor layer 40 includes a first active layer 41A arranged on the insulating substrate 10, and a first insulating layer 44 arranged on the first active layer 41A, wherein the first insulating layer 44 is formed with a boss 44A; wherein the thin film transistor layer 40 also includes a second active layer 42A and a third active layer 43A arranged on the two side walls 441B and the upper surface 441A of the boss 44A, one end of the first active layer 41A is connected to the second active layer 42A, and the other end of the first active layer 41A is connected to the third active layer 43A.

[0099] Specifically, in this embodiment, step S200 includes the following steps:

[0100] Step S201: forming a first active layer 41A on an insulating substrate 10, such as Figure 9B shown.

[0101] Step S202: forming a first insulating layer 44 on the first active layer 41A, wherein the first insulating layer 44 includes a boss 44A located on the first active layer 41A. Figure 9C As shown; wherein the material of the first insulating layer 44 is not limited to a single layer of silicon nitride (Si3N4), a single layer of silicon dioxide (SiO2), a single layer of silicon oxynitride (SiON x ), or a double-layer structure of the above film layers, the orthographic projection of the boss 44A on the insulating substrate 10 is located within the orthographic projection of the first active layer 41A on the insulating substrate 10.

[0102] Step S203: A first metal layer 45 is formed on the upper surface 441A of the boss 44A. The material of the first metal layer 45 includes but is not limited to at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W).

[0103] Step S204: Patterning the first metal layer 45 to form a source electrode 45A and a drain electrode 45B located on the upper surface 441A of the boss 44A and spaced apart from each other. Figure 9D shown.

[0104] Step S205: forming a second active layer 42A on the source electrode 45A, and forming a third active layer 43A on the drain electrode 45B, wherein the second active layer 42A includes a first active segment 421A located on the side wall 441B of the boss 44A, and a first conductor portion 422A located on the upper surface 441A of the boss 44A, one end of the first active segment 421A is connected to the first source electrode 45A, and the other end of the first active segment 421A is connected to the first conductor portion 422A, and the third active layer 43A includes a second active segment 431A located on the side wall 441B of the boss 44A, and a second conductor portion 432A located on the upper surface 441A of the boss 44A, one end of the second active segment 431A is connected to the first source electrode 45A, and the other end of the second active segment 431A is connected to the second conductor portion 432A, wherein the first conductor portion 422A and the second conductor portion 432A are arranged alternately, as shown in FIG. Figure 9E shown.

[0105] It should be noted that, in this embodiment, the material of the first active layer 41A, the material of the first active segment 421A, and the material of the second active segment 431A include but are not limited to amorphous silicon, polycrystalline silicon, or oxide semiconductor materials, and the first conductor portion 422A and the second conductor portion 432A can both be made of silicide and polycrystalline silicon doped with n-type impurities at a high concentration. This embodiment does not impose specific restrictions on this.

[0106] In this embodiment, the method for manufacturing the semiconductor device 1 further includes the following steps:

[0107] Step S300: Forming a second insulating layer 46 on the second active layer 42A and the third active layer 43A, wherein the second insulating layer 46 covers the first active layer 41A, the second active layer 42A and the third active layer 43A in a direction perpendicular to the insulating substrate 10, wherein the second insulating layer 46 includes a groove 461 located between the second active layer 42A and the third active layer 43A on the upper surface 441A of the boss 44A.

[0108] Step S400: forming a second metal layer 47 on the second insulating layer 46 in a direction away from the insulating substrate 10. In a direction perpendicular to the insulating substrate 10, the second metal layer 47 covers the first active layer 41A, the second active layer 42A and the third active layer 43A. The second metal layer 47 fills the groove 461. Figure 9F As shown, preferably, the second metal layer 47 includes but is not limited to a gate 47A.

[0109] It can be understood that, in this embodiment, the channel of the thin film transistor layer 40 is located between the first active layer 41A and the first conductor portion 422A, and between the first active layer 41A and the second conductor portion 432A, that is, the channel between the source 45A and the drain 45B is composed of the first active segment 421A and the second active segment 431A located on the two side walls 441B of the boss 44A, and the length of the channel is determined by the length of the two side walls 441B of the boss 44A and the distance between the side walls 441B and the lower surface of the boss 44A. The angle α between the two side walls 441B of the boss 44A and the angle α between the side walls 441B and the lower surface 441C of the boss 44A are commonly determined, and the width of the channel is determined by the sum of the width of the orthographic projection of the first active segment 421A on the boss 44A and the width of the orthographic projection of the second active segment 431A on the boss 44A. Therefore, despite the limitations of the exposure equipment, since the length of the two side walls 441B of the boss 44A and the angle α between the side walls 441B and the lower surface 441C of the boss 44A can be controlled, the length of the channel can be controlled independently of the exposure equipment, that is, the short channel of the thin film transistor 40A is achieved.

[0110] It should be noted that, in this embodiment, the light-shielding layer 20 includes a first light-shielding sub-layer 21 and a second light-shielding sub-layer 22 arranged at intervals. The first light-shielding sub-layer 21 is arranged corresponding to the first active segment 421A, and the orthographic projection of the first light-shielding sub-layer 21 on the insulating substrate 10 covers the orthographic projection of the first active segment 421A on the insulating substrate 10. The second light-shielding sub-layer 22 is arranged corresponding to the second active segment 431A, and the orthographic projection of the second light-shielding sub-layer 22 on the insulating substrate 10 covers the orthographic projection of the second active segment 431A on the insulating substrate 10, thereby reducing the increase in leakage current caused by photogenerated carriers generated by light irradiating the first active layer 41A and the second active layer 42A, thereby maintaining the stability of the semiconductor device 1 during operation.

[0111] Step S500: forming an interlayer insulating layer 50 and a planarizing layer 60 in sequence on a side of the gate 47A away from the second insulating layer 46, as shown in FIG. Figure 9G shown.

[0112] Step S600: forming a first electrode 71 on a side of the planar layer 60 away from the interlayer insulating layer 50, as shown in FIG. Figure 9H shown.

[0113] Step S700: A first via hole 51 exposing a portion of the drain electrode 45B is formed on the planar layer 60, the interlayer insulating layer 50 and the second insulating layer 46 by a photomask process. Figure 9I shown.

[0114] Step S800: forming a passivation layer 80 on a side of the first electrode 71 away from the planar layer 60, such as Figure 9J As shown; further, the passivation layer 80 fills the first via hole 51, and the passivation layer 80 covers the upper surface 441A of the flat layer 60 and the inner wall of the first via hole 51, thereby playing a role in blocking water and oxygen and insulating the flat layer 60, as shown Figure 9K shown.

[0115] Step S900: A second via hole 81 exposing a portion of the drain electrode 45B is formed on the passivation layer 80 through a photomask process. The aperture of the second via hole 81 is smaller than that of the first via hole 51. Figure 9L shown.

[0116] Step S1000: forming a second electrode 72 on a side of the passivation layer 80 away from the first electrode 71, such as Figure 5 As shown; further, the second electrode 72 is connected to the drain 45B through the second via 81, as shown Figure 6 shown.

[0117] The material of the first electrode 71 and the material of the second electrode 72 both include metal oxide materials, including but not limited to indium gallium zinc oxide (IGZO). Preferably, the first electrode 71 is a common electrode, and the second electrode 72 is a pixel electrode.

[0118] It should be noted that, please combine Figure 4 In this embodiment, the Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D 、 Figure 9E 、 Figure 9F 、 Figure 9G 、 Figure 9H and the Figure 9J For the Figure 4 A schematic cross-sectional view along the first direction X, wherein Figure 9I 、 Figure 9K and the Figure 9L For the Figure 4 A schematic cross-sectional view along the second direction Y in FIG.

[0119] This embodiment provides an electronic device, which includes the semiconductor device described in any one of the above embodiments.

[0120] It can be understood that the semiconductor device has been described in detail in the above embodiments and will not be repeated here.

[0121] In specific applications, the electronic device can be a display screen of a smartphone, tablet computer, laptop computer, smart bracelet, smart watch, smart glasses, smart helmet, desktop computer, smart TV or digital camera, and can even be used on electronic devices with flexible display screens.

[0122] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] The above is a detailed introduction to a semiconductor device and an electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: Insulation substrate; A thin film transistor layer is provided on the insulating substrate, and the thin film transistor layer includes: A first active layer is provided on the insulating substrate; a first insulating layer disposed on the first active layer, wherein the first insulating layer is formed with a boss; A first metal layer is located on the upper surface of the boss, and the first metal layer includes a source electrode and a drain electrode; In which, the thin film transistor layer also includes a second active layer and a third active layer arranged on the two side walls and the upper surface of the boss, one end of the first active layer is connected to the second active layer, and the other end of the first active layer is connected to the third active layer; the source is located between the second active layer and the boss, and the drain is located between the third active layer and the boss, the source is connected to the second active layer, and the drain is connected to the third active layer.

2. The semiconductor device according to claim 1, wherein The second active layer includes a first conductor portion located on an upper surface of the boss, and the third active layer includes a second conductor portion located on an upper surface of the boss, wherein the first conductor portion and the second conductor portion are spaced apart.

3. The semiconductor device according to claim 2, wherein In a direction perpendicular to the insulating substrate, the orthographic projection of the first conductor portion is located within the orthographic projection of the first active layer, the orthographic projection of the second conductor portion is located within the orthographic projection of the first active layer, and the orthographic projection of the first conductor portion and the orthographic projection of the second conductor portion do not overlap with each other.

4. The semiconductor device according to claim 2, wherein The source is connected to the first conductor portion, and the drain is connected to the second conductor portion.

5. The semiconductor device according to claim 4, wherein The source electrode includes a first sub-portion and a second sub-portion, wherein the orthographic projection of the first sub-portion on the insulating base overlaps with the orthographic projection of the first conductor portion on the insulating base, and the orthographic projection of the second sub-portion on the insulating base does not overlap with the orthographic projection of the first conductor portion on the insulating base; The drain includes a third sub-portion and a fourth sub-portion, the orthographic projection of the third sub-portion on the insulating base overlaps with the orthographic projection of the second conductor portion on the insulating base, and the orthographic projection of the fourth sub-portion on the insulating base does not overlap with the orthographic projection of the second conductor portion on the insulating base.

6. The semiconductor device according to claim 5, wherein The semiconductor device includes an electrode layer located on a side of the thin film transistor layer away from the insulating substrate, and the electrode layer is connected to the second sub-section, or the electrode layer is connected to the fourth sub-section.

7. The semiconductor device according to claim 4, wherein: The source electrode is located between the first conductor portion and the boss, and the drain electrode is located between the second conductor portion and the boss.

8. The semiconductor device according to claim 2, wherein: The thin film transistor layer includes a channel located between the first active layer and the first conductor portion, and the length of the channel and the thickness of the boss satisfy the following relationship: Wherein, L represents the length of the channel, H represents the height of the boss, and α represents the angle between the side wall and the lower surface of the boss.

9. The semiconductor device according to claim 8, wherein An included angle α between the side wall and the lower surface of the boss is greater than or equal to 45 degrees and less than 90 degrees.

10. The semiconductor device according to claim 8, wherein In a direction perpendicular to the insulating substrate, the length of the channel is greater than or equal to 100 angstroms and less than or equal to 10,000 angstroms, and the width of the channel is greater than or equal to 300 angstroms and less than or equal to 100,000 angstroms.

11. The semiconductor device according to claim 1, wherein The thin film transistor layer includes a second metal layer located on a side of the first insulating layer away from the insulating substrate. In a direction perpendicular to the insulating substrate, the second metal layer covers the first active layer, the second active layer and the third active layer.

12. The semiconductor device according to claim 11, wherein The thin film transistor layer includes a second insulating layer located between the second metal layer and the first insulating layer, and in a direction perpendicular to the insulating substrate, the second insulating layer covers the first active layer, the second active layer and the third active layer; Wherein, on the upper surface of the boss, the second insulating layer includes a groove located between the second active layer and the third active layer, and the second metal layer fills the groove.

13. The semiconductor device according to claim 1, wherein The thin film transistor layer includes a plurality of thin film transistors, the first insulating layer includes a plurality of bosses, and one thin film transistor is arranged corresponding to one boss, or a plurality of thin film transistors are arranged corresponding to one boss.

14. The semiconductor device according to claim 1, wherein The cross section of the side wall of the boss in a direction perpendicular to the insulating base is a straight line or an arc.

15. The semiconductor device according to claim 1, wherein The semiconductor device includes a light-shielding layer located between the insulating substrate and the first active layer, the second active layer includes a first active segment located on the side wall, and the third active layer includes a second active segment located on the side wall, wherein the orthographic projection of the light-shielding layer on the insulating substrate covers the orthographic projection of the first active segment on the substrate, and the orthographic projection of the light-shielding layer on the insulating substrate covers the orthographic projection of the second active segment on the substrate.

16. An electronic device, characterized in that: The electronic device comprises the semiconductor device according to any one of claims 1 to 15.

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