A schottky diode and a method of manufacturing the same

Abstract

A Schottky diode and a manufacturing method thereof, the Schottky diode comprising a first metal layer, a passivation layer, a semiconductor layer and a second metal layer; the first metal layer is formed on a substrate; the passivation layer is at least partially formed on the first metal layer, the passivation layer formed on the first metal layer has a shaped slope connected with the first metal layer; the semiconductor layer is at least partially formed on the shaped slope, the semiconductor layer has a sidewall higher than the top of the shaped slope, the sidewall is above the first metal layer, the passivation layer separates the sidewall from the first metal layer; a Schottky contact is formed between the semiconductor layer and the first metal layer; an ohmic contact is formed between the second metal layer and the semiconductor layer. By forming the semiconductor layer on the shaped slope of the passivation layer, the part of the semiconductor layer in contact with the first metal layer is not formed by etching, the sidewall formed by etching is separated from the first metal layer by the passivation layer, thereby eliminating the leakage problem caused by the sidewall.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of Schottky diode, in particular to a Schottky diode and a manufacturing method thereof. BACKGROUND

[0002] The existing Schottky diode can realize close ideal factor and high Schottky barrier, but has serious leakage when reverse voltage is applied, and the off-state current rises rapidly with the increase of reverse voltage, which also makes the device easy to be broken down. SUMMARY

[0003] The present application mainly solves the technical problem of reverse voltage leakage and breakdown of the existing Schottky diode.

[0004] According to the first aspect, a Schottky diode is provided in an embodiment, comprising: a first metal layer, a passivation layer, a semiconductor layer and a second metal layer;

[0005] The first metal layer is formed on a substrate, and the first metal layer is a high work function metal;

[0006] The passivation layer is at least partially formed on the first metal layer, and the passivation layer formed on the first metal layer has a shaped slope connected with the first metal layer;

[0007] The semiconductor layer is at least partially formed on the shaped slope, and the semiconductor layer has a sidewall higher than the top of the shaped slope, the sidewall is above the first metal layer, and the passivation layer isolates the sidewall from the first metal layer; the Schottky contact is formed between the semiconductor layer and the first metal layer;

[0008] The second metal layer forms an ohmic contact with the semiconductor layer, and the second metal layer is a low work function metal.

[0009] According to the second aspect, a manufacturing method of a Schottky diode is provided in an embodiment, comprising:

[0010] Forming a first metal layer on a substrate, the first metal layer being a high work function metal;

[0011] Forming a passivation layer on the first metal layer, and patterning the passivation layer to form a shaped slope connected with the first metal layer;

[0012] Forming a semiconductor layer on at least the first metal layer, the semiconductor layer being at least partially formed on the shaped slope, and the semiconductor layer having a sidewall higher than the top of the shaped slope, the sidewall being above the first metal layer, and the passivation layer isolating the sidewall from the first metal layer; the Schottky contact is formed between the semiconductor layer and the first metal layer;

[0013] A second metal layer is formed on the semiconductor layer, the second metal layer is in contact with the semiconductor layer and forms an ohmic contact, and the second metal layer is a low work function metal.

[0014] According to the Schottky diode and the manufacturing method thereof, by forming the semiconductor layer on the formed inclined surface of the passivation layer, the part where the semiconductor layer is in contact with the first metal layer is not formed by etching, and the sidewall formed by etching is separated from the first metal layer by the passivation layer, so as to eliminate the leakage problem caused by the sidewall. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 Fig. 1 is a schematic diagram of the structure of a prior Schottky diode;

[0016] Figure 2 Fig. 2 is a schematic diagram of the electrical characteristic curves of the prior Schottky diode under different defect states;

[0017] Figure 3 Fig. 3 is a schematic diagram of the structure of a Schottky diode according to an embodiment;

[0018] Figure 4 Fig. 4 is a schematic diagram of the structure of another Schottky diode according to an embodiment;

[0019] Figure 5 Fig. 5 is a schematic diagram of the electrical characteristic curves of the Schottky diode shown in Fig. 3; Figure 1 Fig. 6 is a schematic diagram of the electrical characteristic curves of the Schottky diode shown in Fig. 4; Figure 3 Fig. 7 is a schematic diagram of the electrical characteristic curves of the Schottky diode shown in Fig. 3 and Fig. 4;

[0020] Figure 6 Fig. 8 is a flow chart of a manufacturing method of the Schottky diode according to an embodiment;

[0021] Figure 7 Fig. 9 is a schematic diagram of the process of the manufacturing method of the Schottky diode according to an embodiment (1);

[0022] Figure 8 Fig. 10 is a schematic diagram of the process of the manufacturing method of the Schottky diode according to an embodiment (2);

[0023] Figure 9 Fig. 11 is a schematic diagram of the process of the manufacturing method of the Schottky diode according to an embodiment (3);

[0024] Figure 10 Fig. 12 is a schematic diagram of the process of the manufacturing method of the Schottky diode according to an embodiment (4);

[0025] Figure 11 Fig. 13 is a schematic diagram of the process of the manufacturing method of the Schottky diode according to an embodiment (5).

[0026] Reference numerals: 1 - substrate; 2 - first metal layer; 3 - semiconductor layer; 31 - side wall; 4 - passivation layer; 40 - forming groove; 41 - forming slope; 5 - second metal layer. DETAILED DESCRIPTION

[0027] The application will be further described below in connection with specific embodiments with reference to the attached drawings. Like numbers in different figures refer to elements with the same function. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details given. In other instances, well-known methods have not been described in detail in order not to obscure the present application. It will be apparent to one skilled in the art that, in different situations, some features of the application can be omitted, or replaced by other elements, materials, methods, etc. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core of the present application being obscured by too many details, and it is not necessary for one skilled in the art to describe these related operations in detail, based on the description in the specification and the general technical knowledge in the art.

[0028] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various embodiments. Meanwhile, the steps or actions in the method description can also be sequentially adjusted or changed in a manner that is obvious to one skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment, and do not mean that the sequence is necessary, unless otherwise stated that a certain sequence must be followed.

[0029] The serial numbers of components in this document, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any sequence or technical meaning. The "connection" and "coupling" in the present application include direct and indirect connection (coupling) unless otherwise specified.

[0030] As Figure 1As shown, the existing vertical structure Schottky diode can achieve an ideal factor close to 1 and a higher Schottky barrier, but when reverse voltage is applied, the Schottky diode will have a large leakage current, and even be broken down. Some existing Schottky diodes can appropriately reduce the leakage by increasing the guard ring or field plate structure. On the one hand, the material selection of the guard ring or field plate is difficult, and polycrystalline silicon is generally used. On the other hand, the process complexity is increased and the carrier transport mechanism becomes complex, and the process temperature is generally relatively high. When the semiconductor layer 3 is an N-type semiconductor, the field plate can use nickel oxide or P-type polycrystalline silicon, wherein the nickel oxide is unstable, and the P-type polycrystalline silicon is generally used. The forming temperature of the P-type polycrystalline silicon is high, greater than 350 degrees, which does not belong to the low-temperature process in the semiconductor field, and the polycrystalline silicon also needs to be doped to form a guard ring, which requires an additional process. The field plate needs to be arranged on the top of the passivation layer 4 and needs to have a certain width along the left-right direction shown in the figure, which will increase the lateral size of the device, and the field plate generally needs to be used with a field limiting ring to obtain a better electric field modulation effect. The field limiting ring needs to be formed by an additional process (ion implantation), which will also increase the volume of the device. It should be noted that the additional process refers to a process that is not involved in the conventional Schottky diode, such as deposition and doping of polycrystalline silicon. The specific process type can also include different process parameters of the same type of process if necessary.

[0031] The present application analyzes the forming process of the Schottky diode, as shown in Figure 1 As shown, the conventional Schottky diode is formed on the substrate 1 in sequence of the first metal layer 2, the semiconductor layer 3, the passivation layer 4 and the second metal layer 5. The present application believes that the semiconductor layer 3 needs to be patterned after being formed by using dry etching or wet etching. The side wall 31 of the semiconductor layer 3 is formed under the condition of corrosion or ion bombardment, and therefore, the semiconductor layer 3 has a large number of defect states. The present application believes that it is these defect states that cause the device to have a leakage current. Through further analysis, the present application believes that a large number of electrons will tunnel into the semiconductor layer 3 through the defect states under the action of the electric field provided by the negative bias, causing serious leakage at the edge of the semiconductor layer 3 (corresponding to the position of the side wall 31).

[0032] As shown in Figure 2 The present application first uses TCAD simulation to simulate different degrees of defect states. It can be seen that the larger the edge defect state density (DOS) of the semiconductor layer 3, the larger the leakage current under negative voltage, and the more obvious the upwarping.

[0033] In the embodiment of the present application, by changing the forming process of the Schottky diode, the passivation layer 4 is formed first, and then the semiconductor layer 3 is formed. The semiconductor layer 3 is formed on the forming slope 41 of the passivation layer 4, so that the part of the semiconductor layer 3 in contact with the first metal layer 2 is not etched and does not have a defect state, and the sidewall 31 formed by etching is isolated by the passivation layer 4, and the sidewall 31 is isolated from the first metal layer 2, thereby completely eliminating the problem of electric leakage of the sidewall 31.

[0034] Embodiment one:

[0035] Please refer to Figure 3 and Figure 4 , the embodiment provides a Schottky diode, which can include: a first metal layer 2, a passivation layer 4, a semiconductor layer 3 and a second metal layer 5. The Schottky diode provided by the present application can be a vertical structure Schottky diode as shown in Figure 3 , or a horizontal structure Schottky diode as shown in Figure 4 .

[0036] The first metal layer 2 is formed on the substrate 1, and the first metal layer 2 is a high work function metal. The substrate 1 can be a hard material such as silicon, silicon dioxide, etc.; or a flexible substrate such as plastic, paper, etc. Common high work function metals include platinum, palladium, gold or silver oxide. Common semiconductor layers 3, such as metal oxides, carbon nanotubes, perovskites, amorphous silicon or single crystal silicon, can all use the above metals. The thickness of the first metal layer 2 can be half the thickness of the semiconductor layer 3.

[0037] The passivation layer 4 is at least partially formed on the first metal layer 2, and the passivation layer 4 formed on the first metal layer 2 has a forming slope 41 connected with the first metal layer 2; the passivation layer 4 can use at least one insulating layer material, such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, etc.

[0038] The semiconductor layer 3 is at least partially formed on the forming slope 41, and the semiconductor layer 3 has a sidewall 31 higher than the top of the forming slope 41. The sidewall 31 is either in direct contact with the top surface of the passivation layer 4 (corresponding to the vertical structure of Figure 3 , or the sidewall 31 is located above the first metal layer 2, and the passivation layer 4 isolates the sidewall 31 from the first metal layer 2; the Schottky contact is formed between the semiconductor layer 3 and the first metal layer 2. The semiconductor layer 3 can include at least one layer of semiconductor material layer arranged in a stack; the material of the semiconductor layer 3 can be metal oxide (such as gallium nitride, gallium arsenide, generally amorphous), single crystal silicon or amorphous silicon. In the present application, the thickness of the semiconductor layer 3 is not limited, and generally can be greater than or equal to the thickness of the first metal layer 2, for example, the thickness of the first metal layer 2 is 60 nm, and the thickness of the semiconductor layer 3 is 100 nm.

[0039] For example, asFigure 3 and Figure 8 As shown, the Schottky diode is a vertically oriented Schottky diode; the passivation layer 4 has a forming groove 40 extending to the first metal layer 2, the forming groove 40 being centrally located on the first metal layer 2, and the forming groove 40 having two symmetrical forming ramps 41. The semiconductor layer 3 is formed in the forming groove 40, and the top surface of the semiconductor layer 3 is higher than the top of the forming groove 40. The two sides of the portion of the semiconductor layer 3 that is higher than the forming groove 40 have sidewalls 31, which are formed by etching.

[0040] For example, such as Figure 4 As shown, the Schottky diode is a horizontally structured Schottky diode; the forming slope 41 of the passivation layer 4 and the first metal layer 2 are located on one side of the substrate 1, and the second metal layer 5 is located on the other side; the semiconductor layer 3 is partially formed on the first metal layer 2 and partially formed on the substrate 1, and the semiconductor layer 3 is at least partially formed on the forming slope 41; the second metal layer 5 is disposed on the side of the semiconductor layer 3 away from the first metal layer 2. In a horizontally structured Schottky diode, after forming the semiconductor layer 3, a passivation layer 4 needs to be re-covered on the top surface of the semiconductor layer 3. At this time, as... Figure 4 As shown, the passivation layer 4 formed on the first metal layer 2 refers to the portion from the bottom end of the sidewall 31 to the top surface of the first metal layer 2, and this thickness corresponds to the vertical height of the forming slope 41. This can be combined with... Figure 3 passivation layer 4, and Figure 4 The overlapping portion is used to determine this.

[0041] An ohmic contact is formed between the second metal layer 5 and the semiconductor layer 3, and the second metal layer 5 is a low work function metal. For example, Figure 3 As shown, the second metal layer 5 is centrally disposed on the semiconductor layer 3, and the second metal layer 5 covers the sidewall 31 of the semiconductor layer 3. Alternatively, the second metal layer 5 may be disposed on the side of the semiconductor layer 3 away from the first metal layer 2, and in another aspect, the sidewall 31 of the first metal layer 2 of the semiconductor layer 3 may be covered by the second metal layer 5. The thickness of the second metal layer 5 can be half the thickness of the semiconductor layer 3.

[0042] In this embodiment, by changing the deposition order of the passivation layer 4 and the semiconductor layer 3, the passivation layer 4 is formed first, followed by the semiconductor layer 3. This allows the sidewalls 31 of the semiconductor layer 3, etched by wet etching, to be located away from the first metal layer 2, preventing the formation of poor Schottky contacts on the sidewalls 31 of the semiconductor layer 3. Furthermore, the semiconductor layer 3 is completely encapsulated by the second metal layer 5, making it easier for the sidewalls 31 to form ohmic contacts with the second metal layer 5, preventing leakage current and thus completely eliminating leakage current from the sidewalls 31.

[0043] like Figure 5 As shown, with Figure 3 Taking the Schottky diode shown as an example, with Figure 1The Schottky diode shown (corresponding to) Figure 2 Experimental tests were conducted to compare the electrical characteristic curves of the two structures (using an extremely low DOS structure). It can be seen that the current density versus voltage relationship of the two structures, at a reverse voltage of 1.5V, is different from that of the existing structure. Figure 1 The structure shown, even at extremely low DOS, has a leakage current density of approximately 10. -6 A / cm 2 And this application, as Figure 3 The structure shown has a leakage current density of approximately 10. -7 A / cm 2 The leakage current decreased by nearly an order of magnitude. Furthermore, at a forward voltage of 1.5V, the leakage current decreased significantly, unlike in this application. Figure 3 The structure shown has a higher current density, better device performance, and its on-state current is more consistent with the theoretical formula for thermionic emission.

[0044] In one embodiment, with Figure 3 Taking the structure shown as an example, the angle between the forming slope 41 and the first metal layer 2 can be 60°-70°. Since the passivation layer 4 is formed before the semiconductor layer 3, the slope of the forming slope 41 of the passivation layer 4 can be adjusted. In this application, the forming slope 41 of the passivation layer 4 is formed by dry etching or wet etching. Based on the fact that dry etching can better control the lateral etching ratio, the slope of the contact surface between the passivation layer 4 and the semiconductor layer 3 can be changed by adjusting the lateral etching ratio of the dry etching. As the angle changes from 90° to 0°, the electric field at the contact surface decreases rapidly and then increases slowly due to the vector superposition characteristic. Therefore, etching to form a suitable slope can also significantly improve the breakdown voltage. When the forming slope 41 is set perpendicular to the top surface of the first metal layer 2 (with an angle of 90°), it will cause the electric field to concentrate. The current is large at the point of electric field concentration, which can easily lead to leakage and breakdown. Therefore, the forming slope 41 needs to have a slope. This application achieves this by adjusting the lateral etching ratio of the dry etching process, so that the forming slope 41 and the top surface of the first metal layer 2 have an angle.

[0045] For example, in one embodiment, the included angle can be 60°-70°. In this case, the passivation layer 4 can improve the breakdown voltage of the device, and the lateral etching ratio of dry etching is easy to adjust and implement.

[0046] In one embodiment, the thickness of the passivation layer 4 formed on the first metal layer 2 is 20nm-200nm, and the thickness of the first metal layer 2 is greater than or equal to 60nm. In this application, the thickness of the passivation layer 4 can be changed to weaken the edge electric field. The thinner the passivation layer 4, the weaker the edge electric field. However, at the same time, the leakage current through the passivation layer 4 will also increase. Therefore, it is necessary to comprehensively adjust both the edge electric field and leakage current effects to select the most suitable passivation layer 4 thickness, so as to weaken the edge electric field without increasing the leakage current, and ultimately improve the breakdown voltage.

[0047] For example, when the thickness of the first metal layer 2 is equal to 60 nm, the thickness of the passivation layer 4 can be 60 nm, and the thickness of the semiconductor layer 3 can be 100 nm. At this time, the passivation layer 4 can weaken the edge electric field of the semiconductor layer 3 and can also limit the leakage current itself.

[0048] Embodiment II

[0049] For example, the substrate 11 can be a hard substrate or a flexible substrate. The hard substrate can be a conventional single crystal silicon or silicon dioxide or SOI, etc. The flexible substrate can be plastic or paper. In this embodiment, the substrate 11 is taken as plastic as an example for illustration, for example, PET or PI substrate. Figure 6 The embodiment provides a manufacturing method of a Schottky diode. The Schottky diode manufactured by the manufacturing method can be compatible with low-temperature process. The method can include the following steps.

[0050] Step 1: as shown in the figure, a first metal layer 2 is formed on a substrate 1. The first metal layer 2 is a high work function metal. Figure 7 For example, the substrate 11 can be a hard substrate or a flexible substrate. The hard substrate can be a conventional single crystal silicon or silicon dioxide or SOI, etc. The flexible substrate can be plastic or paper. In this embodiment, the substrate 11 is taken as plastic as an example for illustration, for example, PET or PI substrate.

[0051] For example, the first metal layer 2 is palladium, which is formed by a sputtering process. The process temperature is normal temperature, and the thickness is 60 nm.

[0052] Step 2: as shown in the figure, a passivation layer 4 is formed on the first metal layer 2. The passivation layer 4 is patterned to form a shaped slope 41 connected with the first metal layer 2. The material of the passivation layer 4 can be a commonly used insulating material such as silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, etc. The passivation layer 4 can be a single layer structure or a laminated structure. In this application, the passivation layer 4 can be silicon dioxide or silicon nitride, for example, silicon dioxide, which is formed by a plasma enhanced chemical vapor deposition process. The process temperature is below 300°C.

[0053] Figure 8 Step 3: as shown in the figure, a semiconductor layer 3 is formed on at least the first metal layer 2. The semiconductor layer 3 is formed at least partially on the shaped slope 41. The semiconductor layer 3 has a side wall 31 higher than the top of the shaped slope 41. The side wall 31 is located above the first metal layer 2, and the passivation layer 4 isolates the side wall 31 from the first metal layer 2. The semiconductor layer 3 forms a Schottky contact with the first metal layer 2. In this embodiment, the semiconductor layer 3 is taken as a single layer of amorphous metal oxide as an example for illustration. The amorphous metal oxide is mainly used to meet the requirement of low process temperature and compatibility with low-temperature process. If there is no low-temperature requirement, single crystal silicon can also be used.

[0054] Step 3: as shown in the figure, a semiconductor layer 3 is formed on at least the first metal layer 2. The semiconductor layer 3 is formed at least partially on the shaped slope 41. The semiconductor layer 3 has a side wall 31 higher than the top of the shaped slope 41. The side wall 31 is located above the first metal layer 2, and the passivation layer 4 isolates the side wall 31 from the first metal layer 2. The semiconductor layer 3 forms a Schottky contact with the first metal layer 2. In this embodiment, the semiconductor layer 3 is taken as a single layer of amorphous metal oxide as an example for illustration. The amorphous metal oxide is mainly used to meet the requirement of low process temperature and compatibility with low-temperature process. If there is no low-temperature requirement, single crystal silicon can also be used. Figure 10 Step 3: as shown in the figure, a semiconductor layer 3 is formed on at least the first metal layer 2. The semiconductor layer 3 is formed at least partially on the shaped slope 41. The semiconductor layer 3 has a side wall 31 higher than the top of the shaped slope 41. The side wall 31 is located above the first metal layer 2, and the passivation layer 4 isolates the side wall 31 from the first metal layer 2. The semiconductor layer 3 forms a Schottky contact with the first metal layer 2. In this embodiment, the semiconductor layer 3 is taken as a single layer of amorphous metal oxide as an example for illustration. The amorphous metal oxide is mainly used to meet the requirement of low process temperature and compatibility with low-temperature process. If there is no low-temperature requirement, single crystal silicon can also be used.

[0055] ​In this embodiment, a Schottky diode with a vertical structure is used as an example for illustration. Step 2 above may include:

[0056] Step 201: As Figure 7 As shown, a passivation layer 4 is deposited on the first metal layer 2. For example, the passivation layer 4 can be silicon dioxide, which can be formed by plasma-enhanced chemical vapor deposition at a process temperature below 300°C.

[0057] Step 202: The passivation layer 4 is patterned to form a forming groove 40 that extends to the first metal layer 2 on the passivation layer 4. The forming groove 40 has two symmetrical forming slopes 41.

[0058] For example, a forming groove 40 can be formed on the passivation layer 4 using dry etching; wherein, by adjusting the lateral etching ratio of the dry etching, the forming slope 41 of the forming groove 40 is adjusted to a preset angle. The preset angle is used to represent the angle between the forming slope 41 and the upper surface of the first metal layer 2.

[0059] Step 3 above may include:

[0060] Step 301: Form a semiconductor layer 3 on the molding tank 40 and the first metal layer 2, wherein the top surface of the semiconductor layer 3 is higher than the top of the molding tank 40. For example, a sputtering process can be used to obtain a semiconductor layer 3 with a thickness of 100 nm, where the thickness refers to the thickness from the top surface to the bottom surface of the semiconductor layer 3.

[0061] Step 302: Pattern the semiconductor layer 3 so that the two sides of the portion of the semiconductor layer 3 that protrudes above the molding groove 40 have sidewalls 31. For example, the semiconductor layer 3 is etched by wet etching to obtain two sidewalls 31.

[0062] Step 4: As Figure 11 As shown, a second metal layer 5 is formed on the semiconductor layer 3. The second metal layer 5 contacts the semiconductor layer 3 and forms an ohmic contact. The second metal layer 5 is a low work function metal. For example, the second metal layer 5 is molybdenum, titanium, and indium tin oxide, formed by room temperature sputtering or low temperature evaporation (below 350°C), with a thickness of 60 nm.

[0063] Step 4 above may include:

[0064] A second metal layer 5 is formed to cover the semiconductor layer 3. The second metal layer 5 is patterned and retained on the sidewalls 31 and the top surface of the semiconductor layer 3. The second metal layer 5 completely covers the top surface and sidewalls 31 of the semiconductor layer 3. The second metal layer 5 contacts the semiconductor layer 3 and forms an ohmic contact to prevent leakage.

[0065] The above manufacturing method can be used to manufacture products such as...Figure 3 With Figure 11 The vertical structure Schottky diode shown in FIG. 1, if needed to manufacture Figure 4 The horizontal structure Schottky diode shown in FIG. 2, only needs to adjust the mask plate, adjust the patterning shape of each structure layer, and the specific forming process and process temperature can refer to the corresponding process in each step above.

[0066] It can be seen that each process temperature above belongs to a low-temperature process (not more than 350 DEG C), which can be compatible with flexible technology, for example, a flexible diode manufactured on a flexible substrate, which can be applied to flexible screens such as curved screens and folding screens. The existing technical solutions using guard rings and field plates all need high-temperature processes (more than 350 DEG C), which are not compatible with flexible technology.

[0067] In summary, the Schottky diode provided by the present application can greatly reduce the on-state current, completely shield the edge leakage, improve the breakdown voltage, and the reduction of the on-state current also improves the application potential of the Schottky diode in the photoelectric direction. At the same time, the on-state current also conforms to the theoretical formula of thermionic emission, and the ideal factor and barrier height of the on-state are closer to the theoretical value. And the electrical stress test and environmental stability are also improved, and no additional photolithography steps are added, the cost is reduced, and other structures such as field plates can be further reduced.

[0068] The above uses specific examples to describe the present application, which is only used to help understand the present application and does not limit the present application. For those skilled in the art to which the present application belongs, according to the idea of the present application, several simple deductions, deformations or substitutions can be made.

Claims

1. A Schottky diode, characterized in that, include: The first metal layer (2), passivation layer (4), semiconductor layer (3), and second metal layer (5); The first metal layer (2) is formed on the substrate (1), and the first metal layer (2) is a high work function metal; The passivation layer (4) is at least partially formed on the first metal layer (2), and the passivation layer (4) formed on the first metal layer (2) has a shaped bevel (41) connected to the first metal layer (2); The semiconductor layer (3) is at least partially formed on the molding ramp (41), the semiconductor layer (3) has a sidewall (31) that extends above the top of the molding ramp (41), the sidewall (31) is located above the first metal layer (2), and the passivation layer (4) isolates the sidewall (31) from the first metal layer (2); a Schottky contact is formed between the semiconductor layer (3) and the first metal layer (2); An ohmic contact is formed between the second metal layer (5) and the semiconductor layer (3), and the second metal layer (5) is a low work function metal; The Schottky diode is a horizontally structured Schottky diode; The semiconductor layer (3) is partially formed on the first metal layer (2) and partially formed on the substrate (1), and the semiconductor layer (3) is at least partially formed on the molding slope (41); The second metal layer (5) is disposed on the side of the semiconductor layer (3) away from the first metal layer (2).

2. The Schottky diode as described in claim 1, characterized in that, The Schottky diode is a vertically oriented Schottky diode; The passivation layer (4) has a forming groove (40) extending through the first metal layer (2), and the forming groove (40) has two symmetrical forming slopes (41). The semiconductor layer (3) is formed in the molding groove (40), and the top surface of the semiconductor layer (3) is higher than the top of the molding groove (40). The two sides of the portion of the semiconductor layer (3) that is higher than the molding groove (40) have the sidewalls (31).

3. The Schottky diode as described in claim 2, characterized in that, The second metal layer (5) is centrally disposed on the semiconductor layer (3), and the second metal layer (5) wraps around the sidewall (31) of the semiconductor layer (3).

4. The Schottky diode as described in claim 1, characterized in that, The angle between the forming inclined surface (41) and the first metal layer (2) is 60°-70°; and / or the thickness of the passivation layer (4) formed on the first metal layer (2) is 20nm-200nm, and the thickness of the first metal layer (2) is greater than or equal to 60nm.

5. The Schottky diode as described in any one of claims 1 to 4, characterized in that, The semiconductor layer (3) includes at least one stacked semiconductor material layer; And / or, the material of the semiconductor layer (3) is metal oxide, single crystal silicon or amorphous silicon; And / or, the substrate (1) is a flexible substrate.

6. A method for manufacturing a Schottky diode, characterized in that, include: A first metal layer (2) is formed on a substrate (1), wherein the first metal layer (2) is a high work function metal; A passivation layer (4) is formed on the first metal layer (2), and the passivation layer (4) is patterned to form a shaped inclined surface (41) connected to the first metal layer (2); A semiconductor layer (3) is formed at least on the first metal layer (2), the semiconductor layer (3) being at least partially formed on the forming ramp (41), the semiconductor layer (3) having a sidewall (31) extending above the top of the forming ramp (41), the sidewall (31) being located above the first metal layer (2), and the passivation layer (4) isolating the sidewall (31) from the first metal layer (2); a Schottky contact is formed between the semiconductor layer (3) and the first metal layer (2); A second metal layer (5) is formed on the semiconductor layer (3), the second metal layer (5) is in contact with the semiconductor layer (3) and forms an ohmic contact, and the second metal layer (5) is a low work function metal; The Schottky diode is a horizontally structured Schottky diode; The semiconductor layer (3) is partially formed on the first metal layer (2) and partially formed on the substrate (1), and the semiconductor layer (3) is at least partially formed on the molding slope (41); The second metal layer (5) is disposed on the side of the semiconductor layer (3) away from the first metal layer (2).

7. The manufacturing method as described in claim 6, characterized in that, The passivation layer (4) is patterned to form a shaped bevel (41) connected to the first metal layer (2), including: The passivation layer (4) is patterned to form a forming groove (40) that extends to the first metal layer (2) on the passivation layer (4). The forming groove (40) has two symmetrical forming slopes (41). A semiconductor layer (3) is formed on at least the first metal layer (2), including: The semiconductor layer (3) is formed on the molding groove (40) and the first metal layer (2). The top surface of the semiconductor layer (3) is higher than the top of the molding groove (40), and the two sides of the portion of the semiconductor layer (3) that is higher than the molding groove (40) have the sidewalls (31).

8. The manufacturing method as described in claim 6, characterized in that, A second metal layer (5) is formed on the semiconductor layer (3), comprising: A second metal layer (5) is formed covering the semiconductor layer (3), and the second metal layer (5) is patterned, retaining the second metal layer (5) on the sidewall (31) of the semiconductor layer (3) and on the top surface of the semiconductor layer (3).

9. The manufacturing method as described in claim 7, characterized in that, A forming groove (40) extending to the first metal layer (2) is formed on the passivation layer (4), including: The forming groove (40) is formed on the passivation layer (4) by dry etching; wherein, the lateral etching ratio of the dry etching is adjusted, and the forming slope (41) of the forming groove (40) is adjusted to a preset angle.

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