A fabrication process for a front-side locally passivated contact battery, and the resulting battery, module, and system.

Abstract

This invention relates to a fabrication process and a battery for a front-side locally passivated contact battery. The fabrication process includes: fabricating a front-side dielectric layer on the front side of a silicon substrate; selectively doping the surface of the front-side dielectric layer using boron-doped silicon slurry; performing boron doping on the front side of the silicon substrate to obtain p+ emitters spaced apart on the front side of the silicon substrate, a front-side dielectric layer located between two adjacent p+ emitters and locally arranged on the front side of the silicon substrate, and a heavily doped p+ polycrystalline silicon layer stacked on the surface of the front-side dielectric layer; etching and cleaning the back side of the silicon substrate; then sequentially fabricating a back-side dielectric layer and an n+ polycrystalline silicon layer on the back side of the silicon substrate; passivation treatment to prepare back-side and front-side passivation layers; and metallization treatment to prepare back-side and front-side metal electrodes. This fabrication process further simplifies the fabrication process of the local passivated contact structure on the front side of the battery, resulting in low production cost, high production efficiency, and suitability for large-scale mass production.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a fabrication process for a front-side locally passivated contact cell, as well as the cell, module, and system thereof. Background Technology

[0002] With the development of solar cell technology, the requirements for battery efficiency are becoming increasingly stringent. Passivation contact technology, due to its superior surface passivation and contact performance, enables batteries to achieve higher open-circuit voltage and lower contact resistance, thereby improving photoelectric conversion efficiency. Passivation contact technology primarily combines an ultrathin tunneling oxide layer with a heavily doped polycrystalline silicon layer. This ultrathin tunneling oxide layer (such as silicon oxide) reduces the interface state density between the silicon substrate and polycrystalline silicon (Poly-Si) through chemical passivation, allowing majority carriers to be transported via tunneling. Minority carriers, however, are difficult to tunnel through the tunneling oxide layer due to the higher potential barrier and the presence of the Poly-Si field effect.

[0003] However, the current mainstream approach is to apply passivation contact technology to the entire back of the battery to provide better surface passivation and contact performance as a back field, while the front of the battery only has a traditional emitter. For example, the method for fabricating a P-type back-side tunneling oxide passivation contact solar cell disclosed in application number CN201910475066.9 still exhibits high interfacial recombination and contact resistance in the metal electrode contact area on the front of such batteries, thus limiting the improvement of battery efficiency. Of course, a small number of battery structures have also appeared on the market that apply passivation contact technology to the entire front of the battery, such as a P-type PERC battery with front passivation contacts disclosed in application number CN201721093521.1. However, due to the high absorption coefficient of the doped polycrystalline silicon layer, applying the passivation contact structure to the entire front of the battery will cause severe optical loss, thereby affecting the light utilization rate and battery efficiency on the front side. In addition, local passivation contact structures and their preparation methods for the front side of batteries have also emerged. For example, a method for preparing a local passivation contact structure is disclosed in application number CN201910873413.3. Although this preparation method can prepare a local passivation contact structure for the front side of batteries, it is necessary to deposit an intrinsic amorphous silicon layer on the tunneling oxide layer before printing the doping paste. After forming the heavily doped polycrystalline silicon layer, the polycrystalline silicon layer in the unprinted doping paste area needs to be etched with an alkaline solution to remove it. Then, it needs to be immersed in HF solution again to remove the oxide layer in the remaining printed doping paste area. It can be seen that although no additional masking step is required, the preparation process of this local passivation contact structure is still relatively complicated, which affects the application and promotion of this local passivation contact structure on the front side of batteries. Summary of the Invention

[0004] One of the objectives of this invention is to overcome the aforementioned deficiencies of the prior art and provide a fabrication process for a front-side locally passivated contact battery. This fabrication process further simplifies the fabrication process of the locally passivated contact structure, especially the fabrication process of the locally passivated contact structure on the front side of the battery. It has low production cost, high production efficiency, and is suitable for large-scale mass production.

[0005] The second objective of this invention is to provide a battery prepared using the aforementioned process for a front-side locally passivated contact battery. This battery has the passivated contact structure locally disposed on the front side of the battery, which effectively reduces metal contact recombination and contact resistance on the front side of the battery, and effectively avoids optical losses on the front side of the battery caused by polycrystalline silicon, thereby improving the photoelectric conversion efficiency of the battery.

[0006] The third objective of this invention is to provide a solar cell module.

[0007] The fourth objective of this invention is to provide a solar cell system.

[0008] Based on this, the present invention discloses a fabrication process for a front-side locally passivated contact battery, comprising the following fabrication steps:

[0009] Step 1: Prepare a front dielectric layer on the front side of the silicon substrate;

[0010] Step 2: Then, the boron-doped silicon paste is selectively doped onto the surface of the front dielectric layer by screen printing or inkjet printing.

[0011] Step 3: After selective doping, the front side of the silicon substrate is boron-doped by high-temperature boron diffusion to obtain p+ emitters spaced apart on the front side of the silicon substrate, a front dielectric layer located between two adjacent p+ emitters and locally arranged on the front side of the silicon substrate, and a heavily doped p+ polycrystalline silicon layer stacked on the surface of the front dielectric layer.

[0012] Step 4: Then, the back side of the silicon substrate is etched and cleaned to remove the p+ layer deposited around the back side of the silicon substrate, resulting in a clean back side of the silicon substrate.

[0013] Step 5: Sequentially prepare a back dielectric layer and an n+ polysilicon layer on the back side of the cleaned silicon substrate;

[0014] Step 6, then, passivation treatment is performed to form a back passivation layer on the surface of the n+ polysilicon layer and a front passivation layer on the surface of the heavily doped p+ polysilicon layer and the p+ emitter.

[0015] Step 7: Then, metallization is performed to prepare a back metal electrode with one end in contact with the n+ polysilicon layer and the other end extending to the outside of the back passivation layer, and a front metal electrode with one end in contact with the heavily doped p+ polysilicon layer and the other end extending to the outside of the front passivation layer is prepared, thus obtaining a battery with local passivation contact on the front side.

[0016] Preferably, before step 1, the silicon substrate is further pretreated to form a pyramid-shaped light-trapping structure on the front side of the silicon substrate and a planar structure on the back side of the silicon substrate.

[0017] Preferably, in step 2, the selective doping treatment method is screen printing.

[0018] Preferably, in step 3, the diffusion temperature of the high-temperature boron diffusion method is 700-1100℃, the time is 40-240min, and the sheet resistance is 60-200Ω / sqr; during the high-temperature boron diffusion process, the boron-doped silicon slurry crystallizes to form the heavily doped p+ polycrystalline silicon layer, and other high-temperature boron diffusion regions on the front side of the silicon substrate form the p+ emitter, while a borosilicate glass layer is formed on the surface of the p+ emitter.

[0019] More preferably, after step 5, a chemical cleaning process using an acid solution is further included to remove the borosilicate glass layer.

[0020] Preferably, step 5, preparing the n+ polycrystalline silicon layer specifically includes the following steps:

[0021] Step 51: An amorphous silicon layer is prepared on the surface of the back dielectric layer;

[0022] Step 52: Phosphorus doping treatment is performed on the surface of the amorphous silicon layer by ion implantation, followed by heat treatment to prepare a heavily phosphorus-doped n+ polycrystalline silicon layer.

[0023] The present invention also discloses a battery, which is fabricated using the above-described front-side localized passivation contact battery fabrication process, comprising a silicon substrate, wherein a back dielectric layer, an n+ polysilicon layer and a back passivation layer are sequentially disposed on the back side of the silicon substrate, the n+ polysilicon layer is in contact with a back metal electrode extending beyond the back passivation layer, and p+ emitters are arranged at intervals on the front side of the silicon substrate, wherein a front dielectric layer and a heavily doped p+ polysilicon layer are disposed locally on the front side of the silicon substrate and stacked on the surface of the front dielectric layer are disposed between two adjacent p+ emitters, and a front passivation layer is disposed on the surface of both the heavily doped p+ polysilicon layer and the p+ emitter, and the heavily doped p+ polysilicon layer is in contact with a front metal electrode extending beyond the front passivation layer.

[0024] Preferably, the heavily doped p+ polysilicon layer and the p+ emitter have the same doping polarity, and the doping concentration of the heavily doped p+ polysilicon layer is greater than the doping concentration of the p+ emitter.

[0025] Preferably, both the back dielectric layer and the front dielectric layer are silicon oxide with a thickness of 1-2 nm.

[0026] Preferably, the silicon substrate is an N-type crystalline silicon substrate.

[0027] The present invention also discloses a solar cell module, comprising, from top to bottom, a front material layer, a front encapsulation layer, a cell, a back encapsulation layer, and a back material layer, wherein the cell is a cell prepared by the aforementioned front local passivation contact cell preparation process.

[0028] The present invention also discloses a solar cell system, comprising one or more solar cell modules, wherein the solar cell module is one of the aforementioned solar cell modules.

[0029] Compared with the prior art, the present invention has at least the following beneficial effects:

[0030] 1. In the fabrication process of the front-side localized passivation contact cell of the present invention, screen printing is used to selectively print boron-doped silicon paste onto a specific area of ​​the front-side dielectric layer. This eliminates the need for photolithography and multi-step masking. After high-temperature treatment by high-temperature boron diffusion, p+ emitters spaced apart on the front side of the silicon substrate, a front-side dielectric layer located between two adjacent p+ emitters and locally arranged on the front side of the silicon substrate, and a heavily doped p+ polycrystalline silicon layer stacked on the surface of the front-side dielectric layer can be fabricated simultaneously in one step. This greatly simplifies the process flow of the front-side localized passivation contact cell and improves production efficiency. Moreover, screen printing can accurately dope boron-doped silicon paste onto a specific area of ​​the surface of the front-side dielectric layer to avoid contaminating the p+ emitters, thereby ensuring the light utilization rate and cell efficiency of the front side of the cell.

[0031] 2. In the fabrication process of the front-side localized passivated contact battery of the present invention, after the preparation of the front dielectric layer, selective doping treatment using boron-doped silicon slurry, and boron doping treatment, a localized passivated contact structure can be obtained on the front side of the battery. In this fabrication process, there is no need to add an additional masking step, nor is there a need for the deposition of an intrinsic amorphous silicon layer, removal of the polycrystalline silicon layer, and secondary removal of the oxide layer. This further simplifies the fabrication process of the localized passivated contact structure, especially the localized passivated contact structure on the front side of the battery. As a result, the present invention provides a fabrication process for a front-side localized passivated contact battery that is low in production cost, high in production efficiency, and suitable for large-scale mass production.

[0032] 3. Step 3 employs a high-temperature boron diffusion method. Firstly, it can quickly and efficiently complete the boron doping process to obtain the p+ emitter. Secondly, after step 2, the high-temperature boron diffusion method can simultaneously prepare the p+ emitter, the front dielectric layer locally arranged on the front side of the silicon substrate, and the heavily doped p+ polycrystalline silicon layer. It also eliminates the need for conventional annealing or heat treatment steps, simplifies the process flow, and avoids the reduction in battery efficiency caused by the doping atoms in steps 2 and 3 damaging the silicon substrate due to multiple heat treatments.

[0033] 4. The battery prepared by this invention has a locally passivated contact structure formed by a front dielectric layer and a heavily doped p+ polycrystalline silicon layer in a localized area on the front side of the silicon substrate. This allows the heavily doped p+ polycrystalline silicon layer to contact the front metal electrode, effectively reducing metal contact recombination and contact resistance on the front side of the battery, thereby increasing its open-circuit voltage and short-circuit current, and thus improving the photoelectric conversion efficiency of the battery. Moreover, since the silicon substrate has a locally passivated contact structure on the front side, there will be no optical loss on the front side of the battery due to light reflection from the heavily doped p+ polycrystalline silicon layer in the p+ emitter region. Therefore, while reducing metal contact recombination and contact resistance, the light utilization rate on the front side of the battery can also be ensured, thereby improving the battery efficiency. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the silicon substrate after pretreatment in the fabrication process of a front-side localized passivated contact battery according to this embodiment.

[0035] Figure 2 This is a schematic diagram of the structure after the front dielectric layer is prepared in the fabrication process of a front-side localized passivated contact battery according to this embodiment.

[0036] Figure 3 This is a schematic diagram of the structure after local printing of boron-doped silicon paste in the fabrication process of a front-side local passivated contact battery according to this embodiment.

[0037] Figure 4 This is a schematic diagram of the structure after boron doping treatment in the fabrication process of a front-side localized passivated contact battery according to this embodiment.

[0038] Figure 5 This is a schematic diagram of the structure after the back dielectric layer is prepared in the fabrication process of a front-side localized passivated contact battery according to this embodiment.

[0039] Figure 6 This is a schematic diagram of the structure after the amorphous silicon layer is prepared in the fabrication process of a front-side localized passivated contact battery according to this embodiment.

[0040] Figure 7 This is a schematic diagram of the structure after the n+ polycrystalline silicon layer is prepared in the fabrication process of a front-side localized passivated contact cell in this embodiment.

[0041] Figure 8 This is a schematic diagram of the structure after metallization treatment in the fabrication process of a front-side localized passivated contact battery according to this embodiment.

[0042] Explanation of reference numerals: 1. Silicon substrate; 2. Front dielectric layer; 3. Boron-doped silicon paste; 4. p+ emitter; 5. Heavily doped p+ polycrystalline silicon layer; 6. Borosilicate glass layer; 7. Front passivation layer; 8. Front metal electrode; 9. Back dielectric layer; 10. Amorphous silicon layer; 11. n+ polycrystalline silicon layer; 12. Back passivation layer; 13. Back metal electrode. Detailed Implementation

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Example

[0045] This embodiment describes a fabrication process for a front-side locally passivated contact battery, see [link to documentation]. Figure 1-8 The process includes the following steps:

[0046] Step S1: Select a suitable silicon substrate 1, preferably an N-type crystalline silicon substrate, and then pre-treat the silicon substrate 1 to form a pyramid-shaped light-trapping structure on the front side and a planar structure on the back side. The pre-treatment method is preferably alkaline treatment or acid treatment, but is not limited to these two methods.

[0047] In one example of this embodiment, additives may be added during the alkaline treatment to promote the pretreatment process. The structure of the pretreated silicon substrate 1 is as follows. Figure 1 As shown.

[0048] Step S2: Prepare a front dielectric layer 2 on the front side of the pretreated silicon substrate 1. In one example of this embodiment, when the material of the front dielectric layer 2 is silicon oxide, the preparation method of the front dielectric layer 2 is nitric acid oxidation, high-temperature thermal oxidation, or ozone oxidation, but is not limited to the above preparation methods of the front dielectric layer 2.

[0049] Specifically, the steps for preparing silicon oxide using the nitric acid oxidation method are as follows: A pretreated silicon substrate 1 is placed in a 45-80% nitric acid solution and reacted for 4-8 minutes at a temperature of 90-100°C. After the reaction, the silicon substrate 1 is rapidly dried using a nitrogen gun, thus obtaining a silicon oxide layer with a thickness of 1-2 nm on the front side of the silicon substrate 1. Preferably, the thickness of this silicon oxide is 1.5 nm. Its structure is as follows: Figure 2 As shown.

[0050] In step S3, the boron-doped silicon paste 3 is selectively doped onto the surface of the front dielectric layer 2 using screen printing or inkjet printing. Screen printing is preferred as the method for selective doping.

[0051] In one example of this embodiment, the selective doping process using screen printing involves: locally printing boron-doped silicon paste 3 onto the surface of the front dielectric layer 2; after printing, drying at 100-400°C for 5-30 minutes. After selective doping, the structure is as follows: Figure 3 As shown.

[0052] Step S4: After selective doping, the front side of the silicon substrate 1 is boron-doped by high-temperature boron diffusion to obtain p+ emitters 4 spaced apart on the front side of the silicon substrate 1, a front dielectric layer 2 located between two adjacent p+ emitters 4 and locally arranged on the front side of the silicon substrate 1, and a heavily doped p+ polycrystalline silicon layer 5 stacked on the surface of the front dielectric layer 2.

[0053] In one example of this embodiment, the steps for preparing the p+ emitter 4 using the high-temperature boron diffusion method are as follows: In an atmospheric pressure tube, boron tribromide is used as the boron source to perform high-temperature boron source diffusion on the front side of the silicon substrate 1. The diffusion temperature is 700-1100℃, the time is 40-240 min, and the sheet resistance is 60-200 Ω / sqr; preferably, the diffusion temperature is 900℃, the time is 150 min, and the sheet resistance is 150 Ω / sqr. During the high-temperature boron diffusion process, the boron-doped silicon paste 3 crystallizes to form a heavily doped p+ polycrystalline silicon layer 5, thus forming a localized passivation contact structure on the front side of the silicon substrate 1. Simultaneously, other high-temperature boron diffusion regions on the front side of the silicon substrate 1 form lightly doped p+ emitters 4 to form a pn junction with the N-type crystalline silicon substrate. A borosilicate glass layer 6 is also oxidized on the surface of the p+ emitter 4. Specifically, during the high-temperature boron diffusion process, the wafers are inserted back-to-back, i.e., the diffusion surface faces outwards and the non-diffusion surface faces inwards. After the boron doping treatment is completed, its structure is as follows: Figure 4 As shown.

[0054] It should be noted that in step S4, the front dielectric layer 2 covered by the other non-selective doped areas on the front side of the silicon substrate 1 can act as a buffer layer in the high-temperature boron diffusion process, so as to effectively reduce the damage to the surface of the silicon substrate 1 caused by the high-temperature boron diffusion process.

[0055] Step S5: Then, the non-diffusive surface (i.e., the back side) of the silicon substrate 1 is placed in an etching and cleaning machine for etching and cleaning to remove the p+ layer deposited around the non-diffusive surface, obtaining an undoped and clean back side morphology. Specifically, a mixed solution of HF / HNO3 / H2SO4 is used to etch and clean the non-diffusive surface of the silicon substrate 1.

[0056] In step S6, referring to step S2, a back dielectric layer 9 is fabricated on the back side of the silicon substrate 1, with the structure as follows: Figure 5 As shown.

[0057] Step S7: An undoped amorphous silicon layer 10 is prepared on the surface of the back dielectric layer 9. The preparation method is physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), or atmospheric pressure chemical vapor deposition (APCVD). Correspondingly, the equipment used to deposit the amorphous silicon layer 10 is a PVD equipment, an LPCVD equipment, a PECVD equipment, or an APCVD equipment.

[0058] In one example of this embodiment, the process of preparing the amorphous silicon layer 10 by LPCVD is as follows: under a vacuum below 7 × 10⁻⁶ - 3 Under conditions of Torr and temperature of 550-700℃, SiH4 is introduced, followed by a deposition reaction of 10-40 min. Then, a vacuum is drawn to ensure the hazardous SiH4 gas is completely removed. Nitrogen gas is then introduced to atmospheric pressure, and after cooling, the layer is removed, thus fabricating an amorphous silicon layer 10 on the surface of the back dielectric layer 9. Its structure is as follows: Figure 6 As shown.

[0059] Step S8: Phosphorus doping is performed on the amorphous silicon surface using ion implantation, with a pulling voltage of 10-15 keV and a dose of 4.5 × 10⁻⁶. 15 -7.0×10 15 cm -2 Then, through heat treatment, the doped phosphorus atoms are activated to form a heavily phosphorus-doped n+ polycrystalline silicon layer 11, the structure of which is as follows: Figure 7 As shown.

[0060] Specifically, the heat treatment in step S8 is annealing, and the specific steps are as follows: first, the annealing furnace is evacuated, and then nitrogen is filled as a protective gas. During the annealing process, the vacuum degree of the annealing furnace is 450-1050 mbar, the annealing temperature is 700-900℃, and the annealing time is 25-120 min.

[0061] Step S9, after annealing, involves chemical cleaning with an acid solution to remove the borosilicate glass layer 6 and other impurities from the preparation process. This chemical cleaning process is crucial.

[0062] Step S10, then, passivation treatment is performed to form a back passivation layer 12 on the surface of the n+ polysilicon layer 11, and a front passivation layer 7 on the surface of the heavily doped p+ polysilicon layer 5 and the p+ emitter 4.

[0063] In step S11, after passivation, a metallization process is performed to prepare a back metal electrode 13 with one end contacting the n+ polysilicon layer 11 and the other end extending beyond the back passivation layer 12, and a front metal electrode 8 with one end contacting the heavily doped p+ polysilicon layer 5 and the other end extending beyond the front passivation layer 7. Specifically, the back metal electrode 13 is formed by printing silver paste and then sintering; the front metal electrode 8 is formed by printing silver-aluminum paste and then sintering.

[0064] Thus, a battery of this embodiment has been prepared. See below. Figure 8 The device includes a silicon substrate 1. On the back side of the silicon substrate 1, a back dielectric layer 9, a heavily phosphorus-doped n+ polysilicon layer 11, and a back passivation layer 12 are sequentially disposed. The n+ polysilicon layer 11 is in contact with a back metal electrode 13 extending beyond the back passivation layer 12. On the front side of the silicon substrate 1, p+ emitters 4 are arranged at intervals. Between two adjacent p+ emitters 4, a front dielectric layer 2 is disposed locally on the front side of the silicon substrate 1, and a heavily doped p+ polysilicon layer 5 is stacked on the surface of the front dielectric layer. The surfaces of the heavily doped p+ polysilicon layer 5 and the p+ emitters 4 are both provided with a front passivation layer 7, and the heavily doped p+ polysilicon layer 5 is in contact with a front metal electrode 8 extending beyond the front passivation layer 7.

[0065] The heavily doped p+ polysilicon layer 5 is made from boron-doped silicon slurry. The heavily doped p+ polysilicon layer 5 and the p+ emitter 4 have the same doping polarity, and the doping concentration of the heavily doped p+ polysilicon layer 5 is greater than that of the p+ emitter 4.

[0066] In this embodiment, a battery features a locally passivated contact structure formed by a front dielectric layer 2 and a heavily doped p+ polysilicon layer 5, which is located on the front side of a silicon substrate 1 and makes the heavily doped p+ polysilicon layer 5 contact the front metal electrode 8. This effectively reduces metal contact recombination and contact resistance on the front side of the battery, thereby increasing the open-circuit voltage and short-circuit current, and thus improving the photoelectric conversion efficiency of the battery. Furthermore, since the locally passivated contact structure is located on the front side of the silicon substrate 1, the heavily doped p+ polysilicon layer 5 is not present in the p+ emitter 4 region. Therefore, the p+ emitter 4 region effectively avoids optical loss on the front side of the battery due to light reflection from the heavily doped p+ polysilicon layer 5. Thus, the battery reduces metal contact recombination and contact resistance while ensuring light utilization, thereby improving battery efficiency. Moreover, the heavily phosphorus-doped n+ polysilicon layer 11 in this battery contacts the back metal electrode 13, further reducing metal contact recombination and contact resistance on the back side of the battery, and further improving the photoelectric conversion efficiency of the battery.

[0067] In addition, in the fabrication process of a front-side local passivation contact cell in this embodiment, (1) step S3 uses screen printing to selectively print boron-doped silicon paste 3 onto a specific area of ​​the front-side dielectric layer 2. No photolithography and multi-step masking are required. After the high-temperature treatment by the high-temperature boron diffusion method in step S4, the p+ emitter 4, the front-side dielectric layer 2 locally arranged on the front side of the silicon substrate 1, and the heavily doped p+ polycrystalline silicon layer 5 can be fabricated simultaneously in one step. This greatly simplifies the process flow of the front-side local passivation contact cell and improves production efficiency. Moreover, screen printing can accurately dope the boron-doped silicon paste 3 onto a specific area on the surface of the front-side dielectric layer 2 to avoid contaminating the p+ emitter 4, thereby ensuring the light utilization rate and cell efficiency of the front side of the cell. (2) After steps S1-S4, a local passivation contact structure can be obtained on the front side of the battery. In this preparation process, no additional masking step is required, nor is it necessary to deposit an intrinsic amorphous silicon layer, remove the polycrystalline silicon layer, and perform secondary oxide layer removal. This further simplifies the preparation process of the local passivation contact structure, especially the local passivation contact structure on the front side of the battery. As a result, a preparation process of a front-side local passivation contact battery with low production cost, high production efficiency, and suitable for large-scale mass production can be obtained. (3) Step S4 using the high-temperature boron diffusion method has the following advantages: First, it can quickly and efficiently complete the boron doping treatment to obtain the p+ emitter 4. Second, after step S3, the high-temperature boron diffusion method can simultaneously prepare the p+ emitter 4, the front dielectric layer 2 locally arranged on the front side of the silicon substrate 1, and the heavily doped p+ polycrystalline silicon layer 5. It can also eliminate the conventional annealing or heat treatment steps, simplify the process flow, and avoid the reduction in battery efficiency caused by the doping atoms in steps S3 and S4 damaging the silicon substrate 1 due to multiple heat treatments.

[0068] This embodiment also provides a solar cell module, including a front material layer, a front encapsulation layer, a cell, a back encapsulation layer, and a back material layer arranged sequentially from top to bottom, wherein the cell is one of the aforementioned types of cells.

[0069] This embodiment also provides a solar cell system, including one or more solar cell modules, wherein the solar cell module is one of the solar cell modules described above.

[0070] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0071] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A fabrication process for a front-side locally passivated contact battery, characterized in that, The preparation steps include the following: Step 1: Prepare a front dielectric layer on the front side of the silicon substrate; Step 2: Then, the boron-doped silicon paste is selectively doped onto the surface of the front dielectric layer by screen printing or inkjet printing. Step 3: After selective doping, the front side of the silicon substrate is boron-doped by high-temperature boron diffusion to obtain p+ emitters spaced apart on the front side of the silicon substrate, a front dielectric layer located between two adjacent p+ emitters and locally arranged on the front side of the silicon substrate, and a heavily doped p+ polycrystalline silicon layer stacked on the surface of the front dielectric layer. Step 4: Then, the back side of the silicon substrate is etched and cleaned to remove the p+ layer deposited around the back side of the silicon substrate, resulting in a clean back side of the silicon substrate. Step 5: Sequentially prepare a back dielectric layer and an n+ polysilicon layer on the back side of the cleaned silicon substrate; Step 6, then, passivation treatment is performed to form a back passivation layer on the surface of the n+ polysilicon layer and a front passivation layer on the surface of the heavily doped p+ polysilicon layer and the p+ emitter. Step 7: Then, metallization is performed to prepare a back metal electrode with one end in contact with the n+ polysilicon layer and the other end extending to the outside of the back passivation layer, and a front metal electrode with one end in contact with the heavily doped p+ polysilicon layer and the other end extending to the outside of the front passivation layer is prepared, thus obtaining a battery with front local passivation contact. In step 3, the diffusion temperature of the high-temperature boron diffusion method is 700-1100℃; during the high-temperature boron diffusion process, the boron-doped silicon slurry crystallizes to form the heavily doped p+ polycrystalline silicon layer, and other high-temperature boron diffusion regions on the front side of the silicon substrate form the p+ emitter, while a borosilicate glass layer is formed on the surface of the p+ emitter. The heavily doped p+ polysilicon layer and the p+ emitter have the same doping polarity, and the doping concentration of the heavily doped p+ polysilicon layer is greater than that of the p+ emitter.

2. The fabrication process of a front-side locally passivated contact battery according to claim 1, characterized in that, In step 2, the selective doping process is performed using screen printing.

3. The fabrication process of a front-side locally passivated contact battery according to claim 1 or 2, characterized in that, In step 3, the diffusion time of the high-temperature boron diffusion method is 40-240 min and the sheet resistance is 60-200 Ω / sqr.

4. The fabrication process of a front-side locally passivated contact battery according to claim 3, characterized in that, Following step 5, a chemical cleaning process using an acid solution is also included to remove the borosilicate glass layer.

5. The fabrication process of a front-side locally passivated contact battery according to claim 1, characterized in that, Step 5, the preparation of the n+ polycrystalline silicon layer specifically includes the following steps: Step 51: An amorphous silicon layer is prepared on the surface of the back dielectric layer; Step 52: Phosphorus doping treatment is performed on the surface of the amorphous silicon layer by ion implantation, followed by heat treatment to prepare a heavily phosphorus-doped n+ polycrystalline silicon layer.

6. The fabrication process of a front-side locally passivated contact battery according to claim 1, characterized in that, Before step 1, the process further includes a step of pre-treating the silicon substrate to form a pyramid-shaped light-trapping structure on the front side of the silicon substrate and a planar structure on the back side of the silicon substrate.

7. A battery, characterized in that, It is fabricated using the fabrication process of a front-side localized passivated contact cell as described in any one of claims 1-6, comprising a silicon substrate, wherein a back dielectric layer, an n+ polysilicon layer and a back passivation layer are sequentially disposed on the back side of the silicon substrate, the n+ polysilicon layer is in contact with a back metal electrode extending beyond the back passivation layer, p+ emitters are arranged at intervals on the front side of the silicon substrate, and a front dielectric layer locally disposed on the front side of the silicon substrate and a heavily doped p+ polysilicon layer stacked on the surface of the front dielectric layer are disposed between two adjacent p+ emitters, both the heavily doped p+ polysilicon layer and the p+ emitter are provided with a front passivation layer, and the heavily doped p+ polysilicon layer is in contact with a front metal electrode extending beyond the front passivation layer.

8. A battery according to claim 7, characterized in that, Both the back dielectric layer and the front dielectric layer are made of silicon oxide with a thickness of 1-2 nm.

9. A battery according to claim 7, characterized in that, The silicon substrate is an N-type crystalline silicon substrate.

10. A solar cell module, comprising, from top to bottom, a front material layer, a front encapsulation layer, a cell, a back encapsulation layer, and a back material layer, characterized in that: The battery is a battery prepared by the preparation process of a front-side localized passivated contact battery as described in any one of claims 1-6.

11. A solar cell system comprising one or more solar cell modules, characterized in that: The solar cell module is the solar cell module according to claim 10.

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