Epitaxial wafer of light-emitting diode with improved luminous efficiency and preparation method thereof

Abstract

The present disclosure provides an epitaxial wafer of a light-emitting diode (LED) with improved luminous efficiency and a preparation method thereof, belonging to the field of optoelectronic manufacturing technology. The epitaxial wafer includes a substrate and an n-type layer, a light-emitting layer, and a p-type layer sequentially formed on the substrate; the light-emitting layer includes multiple InGaN quantum well layers, multiple n-type GaN quantum barrier layers, and a composite quantum barrier layer, multiple InGaN quantum well layers and multiple n-type GaN quantum barrier layers are alternately stacked, the composite quantum barrier layer is located on the InGaN quantum well layer closest to the p-type layer, and the composite quantum barrier layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence, the first sublayer and the fifth sublayer are both GaN layers, the second sublayer is an AlN layer, and the third sublayer is an AlN layer. x Ga 1‑x N layer, 0.02≤x≤0.08, the fourth sublayer is an InN layer. The disclosed embodiment can improve the electron-hole recombination efficiency and enhance the luminous efficiency of the light-emitting diode.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to an epitaxial wafer of a light-emitting diode (LED) with improved luminous efficiency and a preparation method thereof. Background Art

[0002] Light-emitting diodes (LEDs), a highly influential new product in the optoelectronics industry, boast small size, long lifespan, rich colors, and low energy consumption. They are widely used in lighting, display screens, signal lights, backlights, toys, and other fields. The core structure of LEDs is the epitaxial wafer, and its fabrication significantly influences the optoelectronic properties of LEDs.

[0003] Epitaxial wafers typically consist of a substrate, an n-type layer, a light-emitting layer, and a p-type layer, stacked sequentially on the substrate. Electrons in the n-type layer migrate toward the light-emitting layer, while holes in the p-type layer migrate toward the light-emitting layer. The holes and electrons recombine in the light-emitting layer, generating light. Therefore, enabling more holes and electrons to recombine in the light-emitting layer is crucial for improving the efficiency of LEDs. Summary of the Invention

[0004] The embodiments of the present disclosure provide an epitaxial wafer of a light-emitting diode with improved luminous efficiency and a method for preparing the same, which can improve the efficiency of electron-hole recombination and thus improve the luminous efficiency of the light-emitting diode. The technical solution is as follows:

[0005] On the one hand, an embodiment of the present disclosure provides an epitaxial wafer of a light-emitting diode with improved luminous efficiency, the epitaxial wafer comprising a substrate and an n-type layer, a light-emitting layer, and a p-type layer sequentially formed on the substrate; the light-emitting layer comprises a plurality of InGaN quantum well layers, a plurality of n-type GaN quantum barrier layers, and a composite quantum barrier layer, the plurality of InGaN quantum well layers and the plurality of n-type GaN quantum barrier layers being alternately stacked, the composite quantum barrier layer being located on the InGaN quantum well layer closest to the p-type layer, the composite quantum barrier layer comprising a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked sequentially, the first sublayer and the fifth sublayer being both GaN layers, the second sublayer being an AlN layer, and the third sublayer being an AlN layer. x Ga 1-x N layer, 0.02≤x≤0.08, and the fourth sublayer is an InN layer.

[0006] Optionally, the thickness of the composite quantum barrier layer is no more than 15 nm.

[0007] Optionally, the thickness of the first sublayer is 1nm to 5nm, the thickness of the second sublayer is 0.5nm to 1.5nm, the thickness of the third sublayer is 1nm to 2nm, the thickness of the fourth sublayer is 0.5nm to 1.5nm, and the thickness of the fifth sublayer is 1nm to 5nm.

[0008] Optionally, the thickness of the InGaN quantum well layer is 2 nm to 5 nm.

[0009] Optionally, the thickness of the n-type GaN quantum barrier layer is 5 nm to 15 nm.

[0010] Optionally, the number of layers of the InGaN quantum well layer is 7 to 15 layers.

[0011] On the other hand, the present disclosure also provides a method for preparing an epitaxial wafer of a light-emitting diode with improved luminous efficiency, the method comprising:

[0012] providing a substrate;

[0013] An n-type layer, a light-emitting layer, and a p-type layer are sequentially grown on the substrate; the light-emitting layer comprises a plurality of InGaN quantum well layers, a plurality of n-type GaN quantum barrier layers, and a composite quantum barrier layer; the plurality of InGaN quantum well layers and the plurality of n-type GaN quantum barrier layers are alternately stacked; the composite quantum barrier layer is located on the InGaN quantum well layer closest to the p-type layer; the composite quantum barrier layer comprises a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence; the first sublayer and the fifth sublayer are both GaN layers, the second sublayer is an AlN layer, and the third sublayer is an AlN layer. x Ga 1-x N layer, 0.02≤x≤0.08, and the fourth sublayer is an InN layer.

[0014] Optionally, when growing the n-type GaN quantum barrier layer and the composite quantum barrier layer, the growth temperature is 850° C. to 950° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0015] Optionally, when growing the InGaN quantum well layer, the growth temperature is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

[0016] Optionally, the sum of the thicknesses of the first sublayer, the second sublayer, the third sublayer, the fourth sublayer and the fifth sublayer is not greater than 15 nm, the thickness of the first sublayer is 1 nm to 5 nm, the thickness of the second sublayer is 0.5 nm to 1.5 nm, the thickness of the third sublayer is 1 nm to 2 nm, the thickness of the fourth sublayer is 0.5 nm to 1.5 nm, and the thickness of the fifth sublayer is 1 nm to 5 nm.

[0017] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0018] In the light-emitting layer of the epitaxial wafer of the embodiment of the present disclosure, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer and a fifth sublayer stacked in sequence.

[0019] Among them, the first sublayer is a GaN layer, which can prevent In in the InGaN quantum well layer from diffusing into the P region, and can also prevent Al from diffusing into the InGaN quantum well layer, forming a non-radiative energy level and causing carrier overflow.

[0020] The second sublayer is an AlN layer, and the third sublayer is an AlGaN layer. AlN / AlGaN, as a wide bandgap semiconductor, can increase the potential barrier, reduce the carrier escape velocity, and improve the luminous efficiency of the last InGaN quantum well layer.

[0021] The fourth sublayer is the InN layer. The bandgap width of the InN layer is relatively narrow, which can effectively increase the carrier injection efficiency. The gradient decrease in the bandgap width from the second sublayer, the third sublayer to the fourth sublayer can effectively increase the hole injection efficiency and improve the quantum efficiency.

[0022] The fifth sublayer is the GaN layer. The last GaN layer prevents In in the InN layer from entering the p-type layer to form non-radiative recombination centers, causing the loss of carriers and thus affecting the luminous efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 1 is a schematic structural diagram of an epitaxial wafer of a light-emitting diode provided by an embodiment of the present disclosure;

[0025] Figure 2 This is a flow chart of a method for preparing an epitaxial wafer of a light-emitting diode provided in an embodiment of the present disclosure.

[0026] The descriptions of the marks in the figure are as follows:

[0027] 10. Substrate;

[0028] 20. n-type layer;

[0029] 30. Light-emitting layer; 31. InGaN quantum well layer; 32. n-type GaN quantum barrier layer; 320. Composite quantum barrier layer; 321. First sublayer; 322. Second sublayer; 323. Third sublayer; 324. Fourth sublayer; 325. Fifth sublayer;

[0030] 40. p-type layer; 41. low-temperature p-type GaN layer; 42. p-type AlGaN layer; 43. high-temperature p-type GaN layer; 44. p-type ohmic contact layer;

[0031] 51. Buffer layer; 52. Undoped GaN layer;

[0032] 60. Shallow well layer; 61. In x Ga 1-x N potential well layer; 62. GaN barrier layer. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0034] Figure 1 Schematic diagram of the structure of an epitaxial wafer of a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the epitaxial wafer includes a substrate 10 and an n-type layer 20 , a light-emitting layer 30 and a p-type layer 40 sequentially formed on the substrate 10 .

[0035] like Figure 1 As shown, the light-emitting layer 30 includes multiple InGaN quantum well layers 31, multiple n-type GaN quantum barrier layers 32 and a composite quantum barrier layer 320. The multiple InGaN quantum well layers 31 and the multiple n-type GaN quantum barrier layers 32 are alternately stacked. The composite quantum barrier layer 320 is located on the InGaN quantum well layer 31 closest to the p-type layer 40. The composite quantum barrier layer 320 includes a first sublayer 321, a second sublayer 322, a third sublayer 323, a fourth sublayer 324 and a fifth sublayer 325 stacked in sequence. The first sublayer 321 and the fifth sublayer 325 are both GaN layers, the second sublayer 322 is an AlN layer, and the third sublayer 323 is an AlN layer. x Ga 1-x N layer, 0.02≤x≤0.08, the fourth sublayer 324 is an InN layer.

[0036] In the light emitting layer 30 of the epitaxial wafer of the embodiment of the present disclosure, the composite quantum barrier layer 320 closest to the p-type layer 40 includes a first sublayer 321 , a second sublayer 322 , a third sublayer 323 , a fourth sublayer 324 and a fifth sublayer 325 stacked in sequence.

[0037] The first sublayer 321 is a GaN layer, which can prevent In in the InGaN quantum well layer 31 from diffusing into the P region and also prevent Al from diffusing into the InGaN quantum well layer 31 to form a non-radiative energy level and cause carrier overflow.

[0038] The second sublayer 322 is an AlN layer, and the third sublayer 323 is an AlGaN layer. AlN / AlGaN as wide bandgap semiconductors can increase the potential barrier, reduce the carrier escape velocity, and improve the luminous efficiency of the last InGaN quantum well layer 31 .

[0039] The fourth sublayer 324 is an InN layer. The bandgap width of the InN layer is relatively narrow, which can effectively increase the carrier injection efficiency. The gradient decrease in the bandgap width from the second sublayer 322, the third sublayer 323 to the fourth sublayer 324 can effectively increase the hole injection efficiency and improve the quantum efficiency.

[0040] The fifth sublayer 325 is a GaN layer. The last GaN layer is used to prevent In in the InN layer from entering the p-type layer 40 to form non-radiative recombination centers, causing carrier loss and thus affecting luminous efficiency.

[0041] Optionally, the substrate 10 is a sapphire substrate 10, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 10 can be a flat substrate 10 or a patterned substrate 10.

[0042] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a commonly used substrate 10 with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a sapphire flat sheet substrate 10.

[0043] Optionally, the n-type layer 20 may be an n-type GaN layer, and the thickness of the n-type layer 20 is 1.5 μm to 3.5 μm. The dopant of the n-type layer 20 is silane.

[0044] Optionally, the thickness of the p-type layer 40 is 30 nm to 120 nm, wherein the dopant of the p-type layer 40 is bis(cyclopentadienyl)magnesium.

[0045] The p-type layer 40 may include a low-temperature p-type GaN layer 41 , a p-type AlGaN layer 42 , a high-temperature p-type GaN layer 43 and a p-type ohmic contact layer 44 sequentially stacked on the light emitting layer 30 .

[0046] For example, the low-temperature p-type GaN layer 41 may be a GaN layer grown at a temperature of 700° C. to 800° C., and the high-temperature p-type GaN layer 43 may be a GaN layer grown at a temperature of 900° C. to 1050° C. Both the low-temperature p-type GaN layer 41 and the high-temperature p-type GaN layer 43 are doped with Mg.

[0047] The thickness of the low-temperature p-type GaN layer 41 may be 50 nm to 150 nm. For example, the thickness of the low-temperature p-type GaN layer 41 may be 100 nm.

[0048] The high temperature p-type GaN layer 43 may have a thickness of 50 nm to 150 nm. For example, the low temperature p-type GaN layer 43 may have a thickness of 100 nm.

[0049] In the embodiment of the present disclosure, the p-type AlGaN layer 42 serves as an electron blocking layer for blocking electrons from entering the p-type layer 40. Both the p-type AlGaN layer 42 and the p-type ohmic contact layer 44 are doped with Mg.

[0050] Optionally, the thickness of the p-type AlGaN layer 42 may be 5 nm to 15 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type AlGaN layer 42 is 10 nm.

[0051] If the thickness of the p-type AlGaN layer 42 is too thin, the electron blocking effect will be reduced. If the thickness of the p-type AlGaN layer 42 is too thick, the p-type AlGaN layer 42 will increase its absorption of light, thereby reducing the luminous efficiency of the LED.

[0052] Optionally, the thickness of the p-type ohmic contact layer 44 may be 3 nm to 10 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type ohmic contact layer 44 is 8 nm.

[0053] If the p-type ohmic contact layer 44 is too thin, it will affect the current contact between the epitaxial layer and the electrode. If the p-type ohmic contact layer 44 is too thick, it will increase the absorption of light by the p-type ohmic contact layer 44, thereby reducing the luminous efficiency of the LED.

[0054] Optionally, the sum of the thicknesses of the composite quantum barrier layers 320 is no greater than 15 nm.

[0055] Exemplarily, the thickness of the first sub-layer 321 is 1 nm to 5 nm. For example, the thickness of the first sub-layer 321 is 3 nm.

[0056] Exemplarily, the thickness of the second sub-layer 322 is 0.5 nm to 1.5 nm. For example, the thickness of the second sub-layer 322 is 1 nm.

[0057] Exemplarily, the thickness of the third sub-layer 323 is 1 nm to 2 nm. For example, the thickness of the third sub-layer 323 is 1.5 nm.

[0058] Exemplarily, the thickness of the fourth sub-layer 324 is 0.5 nm to 1.5 nm. For example, the thickness of the fourth sub-layer 324 is 1 nm.

[0059] Exemplarily, the thickness of the fifth sublayer 325 is 1 nm to 5 nm. For example, the thickness of the fifth sublayer 325 is 3 nm.

[0060] In the above implementation, the sum of the thicknesses of the first sublayer 321 , the second sublayer 322 , the third sublayer 323 , the fourth sublayer 324 and the fifth sublayer 325 is 3 nm + 1 nm + 1.5 nm + 1 nm + 3 nm = 9.5 nm.

[0061] By controlling the thickness of the five sublayers within the above range, it is possible to avoid setting the thickness of the five sublayers too thin, thereby failing to improve the electron-hole recombination efficiency and thus enhance the luminous efficiency of the light-emitting diode; it is also possible to avoid setting the thickness of the five sublayers too thick, thereby increasing the production cost.

[0062] In the embodiment of the present disclosure, the thickness of the InGaN quantum well layer 31 in the light emitting layer 30 is 2 nm to 5 nm.

[0063] By controlling the thickness of the InGaN quantum well layer 31 within the above range, it is possible to avoid setting the thickness of the InGaN quantum well layer 31 too thin to achieve the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the InGaN quantum well layer 31 too thick to increase the production cost.

[0064] Exemplarily, the thickness of the InGaN quantum well layer 31 may be 3 nm.

[0065] Optionally, the thickness of the n-type GaN quantum barrier layer 32 is 5 nm to 15 nm.

[0066] By controlling the thickness of the n-type GaN quantum barrier layer 32 within the above range, it is possible to avoid setting the thickness of the n-type GaN quantum barrier layer 32 too thin to achieve the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the n-type GaN quantum barrier layer 32 too thick to increase the production cost.

[0067] Exemplarily, the thickness of the n-type GaN quantum barrier layer 32 is 10 nm.

[0068] Optionally, the number of the InGaN quantum well layer 31 is 7 to 15 layers.

[0069] By controlling the number of InGaN quantum well layers 31 and n-type GaN quantum barrier layers 32 within the above range, it is possible to avoid setting the number of InGaN quantum well layers 31 and n-type GaN quantum barrier layers 32 too small, which would result in the thickness of the light-emitting layer 30 being too small and failing to meet the purpose of electron-hole recombination; it is also possible to avoid setting the thickness of the light-emitting layer 30 too thick, which would increase the production cost.

[0070] For example, the number of InGaN quantum well layers 31 may be 10, the number of n-type GaN quantum barrier layers 32 may be 9, plus a composite quantum barrier layer 320, so that the total number of quantum barrier layers is the same as the number of InGaN quantum well layers.

[0071] It should be noted that Figure 1 Only a part of the structure of the light emitting layer 30 is shown in the figure, and it is not intended to limit the number of cycles of the alternating stacking of the InGaN quantum well layer 31 and the quantum barrier layer.

[0072] Alternatively, as Figure 1 As shown, a buffer layer 51 and a non-doped GaN layer 52 are further included between the substrate 10 and the p-type layer 40 . The buffer layer 51 and the non-doped GaN layer 52 are sequentially stacked on the substrate 10 .

[0073] In the embodiment of the present disclosure, the buffer layer 51 may be a low-temperature GaN layer, which is a GaN layer grown at a temperature between 500° C. and 650° C.

[0074] The thickness of the buffer layer 51 may be 10 nm to 15 nm. For example, the thickness of the buffer layer 51 may be 12 nm.

[0075] By setting the thickness of the buffer layer 51 within the above range, it is possible to avoid the buffer layer 51 being too thin, which would reduce the crystal quality of the epitaxial layer grown on the thinner buffer layer 51; it is also possible to avoid the buffer layer 51 being too thick, which would increase the buffer layer 51's absorption of light, thereby reducing the luminous efficiency of the epitaxial wafer.

[0076] In the embodiment of the present disclosure, an undoped GaN layer 52 is also grown between the buffer layer 51 and the n-type layer 20. Compared with the substrate 10, since the crystal structure of the undoped GaN layer 52 is similar to that of the n-type layer 20, by providing the undoped GaN layer 52 as a transition layer, the crystal quality of the subsequent epitaxial layer can be improved.

[0077] The thickness of the non-doped GaN layer 52 is 1.5 μm to 3.5 μm. For example, the thickness of the non-doped GaN layer 52 is 2 μm.

[0078] By setting the thickness of the undoped GaN layer 52 within the above range, it is possible to avoid the thickness of the undoped GaN layer 52 being too thin, which fails to play a transitional role and reduces the crystal quality of the grown epitaxial layer. It is also possible to avoid the thickness of the undoped GaN layer 52 being too thick, which increases the light absorption of the undoped GaN layer 52 and thus reduces the light emission efficiency of the epitaxial wafer.

[0079] Optionally, as Figure 1 shown, a shallow well layer 60 is further included between the n-type layer 20 and the light-emitting layer 30.

[0080] Among them, the shallow well layer 60 may include 5 to 20 sequentially overlapping In x Ga 1-x N(0 < x < 0.1) well layers 61 and GaN barrier layers 62.

[0081] Exemplarily, the thickness of the In x Ga 1-x N well layer 61 is 1 nm to 4 nm. For example, the thickness of the In x Ga 1-x N well layer 61 is 3 nm.

[0082] Exemplarily, the thickness of the GaN barrier layer 62 is 10 nm to 30 nm. For example, the thickness of the GaN barrier layer 62 is 20 nm.

[0083] In the above implementation, the shallow well layer 60 adopts a superlattice structure formed by sequentially alternatingly stacking multiple In x Ga 1-x N well layers 61 and GaN barrier layers 62. The superlattice structure can be used to relieve the lattice mismatch between heterogeneous materials, which is beneficial to improving the overall crystal quality of the epitaxial wafer and ultimately enhancing the light emission efficiency of the LED.

[0084] The light emission effect of this epitaxial wafer is illustrated by the following several examples:

[0085] In the first example, the quantum barrier layer closest to the p-type layer includes 3 sub-layers stacked in sequence. The first sub-layer is a GaN layer with a thickness of 1 nm to 5 nm; the second sub-layer is an Al x Ga 1-x N layer (0.02 ≤ X ≤ 0.08) with a thickness of 1 nm to 2 nm; the third sub-layer is a GaN layer with a thickness of nm to 5 nm, and the total thickness of the quantum barrier layer does not exceed 15 nm.

[0086] In a second embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked sequentially. The first sublayer has a thickness of 1 nm to 5 nm; the second sublayer has a thickness of 0.5 nm; the third sublayer has a thickness of 1 nm to 2 nm; the fourth sublayer has a thickness of 0.5 nm; and the fifth sublayer has a thickness of 1 nm to 5 nm. The total thickness of the five sublayers does not exceed 15 nm.

[0087] In a third embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence. The first sublayer has a thickness of 1 nm to 5 nm; the second sublayer has a thickness of 0.5 nm; the third sublayer has a thickness of 1 nm to 2 nm; the fourth sublayer has a thickness of 0.8 nm; and the fifth sublayer has a thickness of 1 nm to 5 nm. The total thickness of the five sublayers does not exceed 15 nm.

[0088] In a fourth embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence. The first sublayer has a thickness of 1nm to 5nm; the second sublayer has a thickness of 0.5nm; the third sublayer has a thickness of 1nm to 2nm; the fourth sublayer has a thickness of 1.2nm; and the fifth sublayer has a thickness of 1nm to 5nm. The total thickness of the five sublayers does not exceed 15nm.

[0089] In a fifth embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence. The first sublayer has a thickness of 1 nm to 5 nm; the second sublayer has a thickness of 0.5 nm; the third sublayer has a thickness of 1 nm to 2 nm; the fourth sublayer has a thickness of 1.5 nm; and the fifth sublayer has a thickness of 1 nm to 5 nm. The total thickness of the five sublayers does not exceed 15 nm.

[0090] In a sixth embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked sequentially. The first sublayer has a thickness of 1 nm to 5 nm; the second sublayer has a thickness of 0.8 nm; the third sublayer has a thickness of 1 nm to 2 nm; the fourth sublayer has a thickness of 0.8 nm; and the fifth sublayer has a thickness of 1 nm to 5 nm. The total thickness of the five sublayers does not exceed 15 nm.

[0091] In the seventh embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence. The first sublayer has a thickness of 1nm to 5nm; the second sublayer has a thickness of 1.2nm; the third sublayer has a thickness of 1nm to 2nm; the fourth sublayer has a thickness of 0.8nm; and the fifth sublayer has a thickness of 1nm to 5nm. The total thickness of the five sublayers does not exceed 15nm.

[0092] In an eighth embodiment, the composite quantum barrier layer closest to the p-type layer includes a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence. The first sublayer has a thickness of 1 nm to 5 nm; the second sublayer has a thickness of 1.5 nm; the third sublayer has a thickness of 1 nm to 2 nm; the fourth sublayer has a thickness of 0.8 nm; and the fifth sublayer has a thickness of 1 nm to 5 nm. The total thickness of the five sublayers does not exceed 15 nm.

[0093] The epitaxial wafers were fabricated into single 22×40 mil LED chips through semiconductor processes including cleaning, deposition, photolithography, and etching. Testing of the LED chips revealed that, compared to the first example, with a fixed AlN layer thickness of 0.5 nm, the second example achieved a 0.7% improvement in luminous efficiency, the third example achieved a nearly 1.2% improvement, the fourth example achieved an approximately 0.5% improvement, and the fifth example showed no improvement. When the InN layer thickness was fixed at 0.8 nm, compared to the third example, the sixth and eighth examples showed no improvement, while the seventh example showed a 0.3% improvement. The seventh example, the optimal example, achieved a 1.5% improvement in luminous efficiency compared to the first.

[0094] Figure 2 This is a flow chart of a method for preparing an epitaxial wafer of a light-emitting diode provided by an embodiment of the present disclosure. Figure 1 The epitaxial wafer shown. Figure 2 As shown, the preparation method comprises:

[0095] S11: providing a substrate 10.

[0096] S12 : growing an n-type layer 20 , a light-emitting layer 30 , and a p-type layer 40 in sequence on the substrate 10 .

[0097] The light-emitting layer 30 includes a plurality of InGaN quantum well layers 31, a plurality of n-type GaN quantum barrier layers 32, and a composite quantum barrier layer 320. The plurality of InGaN quantum well layers 31 and the plurality of n-type GaN quantum barrier layers 32 are alternately stacked. The composite quantum barrier layer 320 is located on the InGaN quantum well layer 31 closest to the p-type layer 40. The composite quantum barrier layer 320 includes a first sublayer 321, a second sublayer 322, a third sublayer 323, a fourth sublayer 324, and a fifth sublayer 325 stacked in sequence. The first sublayer 321 and the fifth sublayer 325 are both GaN layers, the second sublayer 322 is an AlN layer, and the third sublayer 323 is an AlN layer. x Ga 1-x N layer, 0.02≤x≤0.08, the fourth sublayer 324 is an InN layer.

[0098] In the light-emitting layer 30 of the epitaxial wafer prepared by this preparation method, the composite quantum barrier layer 320 closest to the p-type layer 40 includes a first sublayer 321, a second sublayer 322, a third sublayer 323, a fourth sublayer 324 and a fifth sublayer 325 stacked in sequence.

[0099] The first sublayer 321 is a GaN layer, which can prevent In in the InGaN quantum well layer 31 from diffusing into the P region and also prevent Al from diffusing into the InGaN quantum well layer 31 to form a non-radiative energy level and cause carrier overflow.

[0100] The second sublayer 322 is an AlN layer, and the third sublayer 323 is an AlGaN layer. AlN / AlGaN as wide bandgap semiconductors can increase the potential barrier, reduce the carrier escape velocity, and improve the luminous efficiency of the last InGaN quantum well layer 31 .

[0101] The fourth sublayer 324 is an InN layer. The bandgap width of the InN layer is relatively narrow, which can effectively increase the carrier injection efficiency. The gradient decrease in the bandgap width from the second sublayer 322, the third sublayer 323 to the fourth sublayer 324 can effectively increase the hole injection efficiency and improve the quantum efficiency.

[0102] The fifth sublayer 325 is a GaN layer. The last GaN layer is used to prevent In in the InN layer from entering the p-type layer 40 to form non-radiative recombination centers, causing carrier loss and thus affecting luminous efficiency.

[0103] In step S11, the substrate 10 is a sapphire substrate 10, a silicon substrate 10, or a silicon carbide substrate 10. The substrate 1010 can be a flat substrate 10 or a patterned substrate 10.

[0104] As an example, in the embodiment of the present disclosure, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 is a commonly used substrate 10 with mature technology and low cost. Specifically, it can be a patterned sapphire substrate 10 or a sapphire flat sheet substrate 10.

[0105] In step S11 , the sapphire substrate 10 may be subjected to a high-temperature cleaning treatment in a hydrogen atmosphere at 1000° C. to 1200° C. for 5 to 20 minutes, and then subjected to a nitriding treatment.

[0106] In step S11, the sapphire substrate 10 may be pre-treated by placing the sapphire substrate 10 in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate 10 for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0107] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0108] The following steps may also be included before step S12:

[0109] In the first step, a buffer layer 51 is grown on the substrate 10 .

[0110] In the embodiment of the present disclosure, the buffer layer 51 may be a low-temperature GaN layer, which is a GaN layer grown at a temperature between 500° C. and 650° C.

[0111] The thickness of the buffer layer 51 may be 10 nm to 15 nm. For example, the thickness of the buffer layer 51 may be 12 nm.

[0112] Specifically, after the high-temperature treatment of the sapphire substrate 10 is completed, the temperature is lowered to 500°C to 650°C, and a low-temperature GaN buffer layer 51 with a thickness of 10nm to 15nm is first grown, and then the temperature is raised to 1000°C to 1100°C, annealed for 3min to 10min, the growth pressure is 50Torr to 200Torr, V / III is 50 to 300, and the rotation speed is 200r / min to 600r / min.

[0113] In the second step, a non-doped GaN layer 52 is grown on the buffer layer 51 .

[0114] In the embodiment of the present disclosure, an undoped GaN layer 52 is also grown between the buffer layer 51 and the n-type layer 20. Compared with the substrate 10, since the crystal structure of the undoped GaN layer 52 is similar to that of the n-type layer 20, by providing the undoped GaN layer 52 as a transition layer, the crystal quality of the subsequent epitaxial layer can be improved.

[0115] The thickness of the non-doped GaN layer 52 is 1.5 μm to 3.5 μm. For example, the thickness of the non-doped GaN layer 52 is 2 μm.

[0116] Specifically, after the growth of the low-temperature GaN buffer layer 51 is completed, the temperature is adjusted to 1000° C. to 1200° C., and an epitaxial non-doped GaN layer 52 with a thickness of 1 μm to 2 μm is grown. The growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 200 to 3000.

[0117] Step S12 may include the following steps:

[0118] In the first step, an n-type layer 20 is grown on the undoped GaN layer 52 .

[0119] Optionally, the n-type layer 20 may be an n-type GaN layer. The thickness of the n-type layer 20 is 1.5 μm to 3.5 μm. Among them, the dopant of the n-type layer 20 is silane.

[0120] Specifically, after the growth of the undoped GaN layer 52, an n-type GaN layer with a stable Si doping concentration is grown, with a thickness of 1.5 μm to 3.5 μm, a growth temperature of 950 °C to 1150 °C, a growth pressure of 300 Torr to 500 Torr, and a V / III ratio of 400 to 3000.

[0121] In the second step, a shallow well layer 60 is grown on the n-type layer 20.

[0122] Among them, the shallow well layer 60 may include 5 to 20 sequentially overlapping In x Ga 1-x N (0 < x < 0.1) well layers 61 and GaN barrier layers 62.

[0123] Exemplarily, the thickness of the In x Ga 1-x N well layer 61 is 1 nm to 4 nm. For example, the thickness of the In x Ga 1-x N well layer 61 is 3 nm.

[0124] Exemplarily, the thickness of the GaN barrier layer 62 is 10 nm to 30 nm. For example, the thickness of the GaN barrier layer 62 is 20 nm.

[0125] Specifically, after the growth of the n-type doped GaN layer, the shallow well layer 60 is grown. Among them, the growth temperature of the In x Ga 1-x N well layer 61 is 750 °C to 850 °C, the growth pressure is 100 Torr to 500 Torr, the thickness is 1 nm to 4 nm, and the V / III ratio is 500 to 10000. The growth temperature of the GaN barrier layer 62 is 850 °C to 950 °C, the growth pressure is 100 Torr to 500 Torr, the V / III ratio is 500 to 10000, and the thickness is 10 nm to 30 nm.

[0126] In the third step, a light-emitting layer 30 is grown on the shallow well layer 60.

[0127] Specifically, after the growth of the shallow well layer 60, the light-emitting layer 30 is grown. Among them, the InGaN quantum well layer 31 is In y Ga 1-yThe N(0.2 < y < 0.5) layer, the growth temperature of the InGaN quantum well layer 31 is 700 °C to 850 °C, the growth pressure is 100 Torr to 500 Torr, the V / III ratio is 2000 to 20000, and the thickness is 2 nm to 5 nm. The growth temperature of the n-type GaN quantum barrier layer 32 and the composite quantum barrier layer 320 is 850 °C to 950 °C, the growth pressure is 100 Torr to 500 Torr, the V / III ratio is 2000 to 20000, and the thickness is 5 nm to 15 nm.

[0128] Optionally, the sum of the thicknesses of the first sub-layer 321, the second sub-layer 322, the third sub-layer 323, the fourth sub-layer 324, and the fifth sub-layer 325 is not greater than 15 nm.

[0129] Exemplarily, the thickness of the first sub-layer 321 is 1 nm to 5 nm. For example, the thickness of the first sub-layer 321 is 3 nm.

[0130] Exemplarily, the thickness of the second sub-layer 322 is 0.5 nm to 1.5 nm. For example, the thickness of the second sub-layer 322 is 1 nm.

[0131] Exemplarily, the thickness of the third sub-layer 323 is 1 nm to 2 nm. For example, the thickness of the third sub-layer 323 is 1.5 nm.

[0132] Exemplarily, the thickness of the fourth sub-layer 324 is 0.5 nm to 1.5 nm. For example, the thickness of the fourth sub-layer 324 is 1 nm.

[0133] Exemplarily, the thickness of the fifth sub-layer 325 is 1 nm to 5 nm. For example, the thickness of the fifth sub-layer 325 is 3 nm.

[0134] In the embodiment of the present disclosure, the thickness of the InGaN quantum well layer 31 in the light-emitting layer 30 is 2 nm to 5 nm. Exemplarily, the thickness of the InGaN quantum well layer 31 can be 3 nm.

[0135] Optionally, the thickness of the n-type GaN quantum barrier layer 32 is 5 nm to 15 nm. Exemplarily, the thickness of the n-type GaN quantum barrier layer 32 is 10 nm.

[0136] Optionally, the number of layers of the InGaN quantum well layer 31 is 7 to 15 layers, and the number of layers of the n-type GaN quantum barrier layer 32 is 6 to 14 layers. Exemplarily, the number of layers of the InGaN quantum well layer 31 can be 10 layers, and the number of layers of the n-type GaN quantum barrier layer 32 can be 9 layers, plus a composite quantum barrier layer 320, so that the total number of layers of the quantum barrier layer is the same as the number of layers of the InGaN quantum well layer.

[0137] The third step is to grow a p-type layer 40 on the light-emitting layer 30.

[0138] Optionally, the thickness of the p-type layer 40 is 30 nm to 120 nm, wherein the dopant of the p-type layer 40 is bis(cyclopentadienyl)magnesium.

[0139] The p-type layer 40 may include a low-temperature p-type GaN layer 41, a p-type AlGaN layer 42, a high-temperature p-type GaN layer 43, and a p-type ohmic contact layer 44 sequentially stacked on the light-emitting layer 30. Both the low-temperature p-type GaN layer 41 and the high-temperature p-type GaN layer 43 are doped with Mg.

[0140] The thickness of the low-temperature p-type GaN layer 41 may be 50 nm to 150 nm. For example, the thickness of the low-temperature p-type GaN layer 41 may be 100 nm.

[0141] The high temperature p-type GaN layer 43 may have a thickness of 50 nm to 150 nm. For example, the low temperature p-type GaN layer 43 may have a thickness of 100 nm.

[0142] In the embodiment of the present disclosure, the p-type AlGaN layer 42 serves as an electron blocking layer for blocking electrons from entering the p-type layer 40. Both the p-type AlGaN layer 42 and the p-type ohmic contact layer 44 are doped with Mg.

[0143] Optionally, the thickness of the p-type AlGaN layer 42 may be 5 nm to 15 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type AlGaN layer 42 is 10 nm.

[0144] Optionally, the thickness of the p-type ohmic contact layer 44 may be 3 nm to 10 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type ohmic contact layer 44 is 8 nm.

[0145] Specifically, after the growth of the light emitting layer 30 is completed, a low-temperature p-type GaN layer 41 with a thickness of 30nm to 120nm is grown at a growth temperature of 700°C to 800°C, a growth time of 3min to 15min, a pressure of 100Torr to 600Torr, and a V / III ratio of 1000 to 4000.

[0146] After the growth of the low-temperature p-type GaN layer 41 is completed, a p-type AlGaN layer 42 with a thickness of 50nm to 150nm is grown at a growth temperature of 900°C to 1000°C, a growth time of 4min to 15min, a growth pressure of 50Torr to 300Torr, and a V / III ratio of 1000 to 10000.

[0147] After the growth of the p-type AlGaN layer 42 is completed, a high-temperature p-type GaN layer 43 with a thickness of 50 nm to 150 nm is grown at a growth temperature between 900° C. and 1050° C., a growth time of 10 min to 20 min, a growth pressure of 100 Torr to 500 Torr, and a V / III ratio of 500 to 4000.

[0148] After the high-temperature p-type GaN layer 43 is grown, a p-type ohmic contact layer 44 with a thickness of 3 nm to 10 nm is grown at a growth temperature of 700° C. to 850° C., a growth time of 0.5 min to 5 min, a growth pressure of 100 Torr to 500 Torr, and a V / III ratio of 10,000 to 20,000.

[0149] After step S12 , the preparation method may further include: annealing the epitaxial wafer.

[0150] After the epitaxial growth is completed, the temperature of the reaction chamber is lowered to 600℃ to 900℃, and annealing treatment is carried out in PN2 atmosphere for 10min to 30min, and then gradually lowered to room temperature. Subsequently, a single 22×40mil chip is made through subsequent processing processes such as cleaning, deposition, photolithography and etching.

[0151] In specific implementation, the embodiments of the present disclosure can use high-purity H2 and / or N2 as carrier gas, TEGa or TMGa as Ga source, TMIn as In source, SiH4 as n-type dopant, TMAl as aluminum source, ammonia as N source, and Cp2Mg as p-type dopant.

[0152] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. An epitaxial wafer for a light-emitting diode with improved luminous efficiency, characterized in that: The epitaxial wafer comprises a substrate (10) and an n-type layer (20), a light-emitting layer (30) and a p-type layer (40) sequentially formed on the substrate (10); The light-emitting layer (30) includes a plurality of InGaN quantum well layers (31), a plurality of n-type GaN quantum barrier layers (32) and a composite quantum barrier layer (320), wherein the plurality of InGaN quantum well layers (31) and the plurality of n-type GaN quantum barrier layers (32) are alternately stacked, and the composite quantum barrier layer (320) is located on the InGaN quantum well layer (31) closest to the p-type layer (40). The composite quantum barrier layer (320) includes a first sublayer (321), a second sublayer (322), a third sublayer (323), a fourth sublayer (324) and a fifth sublayer (325) stacked in sequence, wherein the first sublayer (321) and the fifth sublayer (325) are both GaN layers, the second sublayer (322) is an AlN layer, and the third sublayer (323) is an AlN layer. x Ga 1-x N layer, 0.02≤x≤0.08, the fourth sublayer (324) is an InN layer, the thickness of the first sublayer (321) is 1nm to 5nm, the thickness of the second sublayer (322) is 0.5nm to 1.5nm, the thickness of the third sublayer (323) is 1nm to 2nm, the thickness of the fourth sublayer (324) is 0.5nm to 1.5nm, and the thickness of the fifth sublayer (325) is 1nm to 5nm.

2. The epitaxial wafer according to claim 1, characterized in that The thickness of the composite quantum barrier layer (320) is no greater than 15 nm.

3. The epitaxial wafer according to claim 1 or 2, characterized in that: The thickness of the InGaN quantum well layer (31) is 2nm to 5nm.

4. The epitaxial wafer according to claim 1 or 2, characterized in that: The thickness of the n-type GaN quantum barrier layer (32) is 5nm to 15nm.

5. The epitaxial wafer according to claim 1 or 2, characterized in that: The number of layers of the InGaN quantum well layer (31) is 7 to 15.

6. A method for preparing an epitaxial wafer of a light-emitting diode with improved luminous efficiency, characterized in that: The preparation method comprises: providing a substrate; An n-type layer, a light-emitting layer, and a p-type layer are sequentially grown on the substrate; the light-emitting layer comprises a plurality of InGaN quantum well layers, a plurality of n-type GaN quantum barrier layers, and a composite quantum barrier layer; the plurality of InGaN quantum well layers and the plurality of n-type GaN quantum barrier layers are alternately stacked; the composite quantum barrier layer is located on the InGaN quantum well layer closest to the p-type layer; the composite quantum barrier layer comprises a first sublayer, a second sublayer, a third sublayer, a fourth sublayer, and a fifth sublayer stacked in sequence; the first sublayer and the fifth sublayer are both GaN layers, the second sublayer is an AlN layer, and the third sublayer is an AlN layer. x Ga 1-x N layer, 0.02≤x≤0.08, the fourth sublayer is an InN layer, the sum of the thicknesses of the first sublayer, the second sublayer, the third sublayer, the fourth sublayer and the fifth sublayer is not greater than 15nm, the thickness of the first sublayer is 1nm to 5nm, the thickness of the second sublayer is 0.5nm to 1.5nm, the thickness of the third sublayer is 1nm to 2nm, the thickness of the fourth sublayer is 0.5nm to 1.5nm, and the thickness of the fifth sublayer is 1nm to 5nm.

7. The preparation method according to claim 6, characterized in that When growing the n-type GaN quantum barrier layer and the composite quantum barrier layer, the growth temperature is 850° C. to 950° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

8. The preparation method according to claim 6, characterized in that When growing the InGaN quantum well layer, the growth temperature is 700° C. to 850° C., the growth pressure is 100 Torr to 500 Torr, and the V / III ratio is 2000 to 20000.

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