Inductor current peak clamping circuit for dc-dc converter and dc-dc converter

Abstract

Embodiments of the present disclosure provide an inductor current peak clamping circuit for a DC-DC converter, which includes a clamping signal generating circuit, a clamping signal amplitude detecting circuit, a clamping trigger circuit, a clamping state control circuit and a clamping signal control circuit. The clamping signal generating circuit generates a clamping signal according to a feedback voltage and a first reference voltage. The clamping signal amplitude detecting circuit generates a detecting signal according to the clamping signal and a second reference voltage. The clamping trigger circuit generates a clamping trigger signal according to a first and a second indication signal and the detecting signal. The active level of the first indication signal indicates that the feedback voltage is greater than or equal to the first reference voltage. The active level of the second indication signal indicates that the main phase inductor current reaches a peak value. The clamping state control circuit generates a clamping state control signal according to the first indication signal, the detecting signal and the clamping trigger signal. The clamping signal control circuit clamps the clamping signal at a clamping reference voltage when the clamping state control signal is at an active level.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to an inductor current peak clamping circuit for a DC-DC converter and a DC-DC converter. BACKGROUND

[0002] With the rapid development of the integrated circuit industry and the increasing expansion of the analog integrated circuit market, DC-DC (Direct Current to Direct Current) converters have also received extensive attention and rapid development. As a kind of high-efficiency switching power supply technology, the DC-DC converter has the advantages of fast dynamic response, simple control, and direct control of output current. The power tube and the freewheeling tube in the DC-DC converter are alternately turned on to control the charging and discharging of the inductor in the DC-DC converter, thereby realizing the stable output of the DC-DC converter. A current detection circuit can be provided in the DC-DC converter, and when the inductor current flowing through the inductor is too large, the charging of the inductor can be stopped by controlling the power tube and the freewheeling tube, thereby realizing the peak clamping of the inductor current.

[0003] In a control system for output voltage regulation, in the case of light load applied to the DC-DC converter, if the output voltage is higher than the steady-state design value, the peak value of the inductor current is usually clamped to a lower level to limit the energy supply of the power stage, and the auxiliary output voltage falls to the steady-state design value. In a multi-phase control circuit with forced continuous current mode (FCCM), when the control system has all phases turned on and the output voltage is too high, clamping the peak value of the inductor current to 0A to adjust the adaptive turn-off time of the voltage regulation mode can make the average inductor current of the turned-on phase negative, effectively realizing energy discharge. SUMMARY

[0004] Embodiments described herein provide an inductor current peak clamping circuit for a DC-DC converter and a DC-DC converter.

[0005] According to a first aspect of the present disclosure, an inductor current peak clamping circuit for a DC-DC converter is provided. The inductor current peak clamping circuit comprises a clamping signal generating circuit, a clamping signal amplitude detecting circuit, a clamping trigger circuit, a clamping state control circuit, and a clamping signal control circuit. The clamping signal generating circuit is configured to generate a clamping signal according to a feedback voltage of the DC-DC converter and a first reference voltage from a first reference voltage terminal, and provide the clamping signal to the clamping signal amplitude detecting circuit via a first node. The clamping signal is used to adjust a peak value of an inductor current of the DC-DC converter. The clamping signal amplitude detecting circuit is configured to generate a detection signal according to the clamping signal and a second reference voltage from a second reference voltage terminal, and provide the detection signal to the clamping trigger circuit and the clamping state control circuit via a second node. The clamping trigger circuit is configured to generate a clamping trigger signal according to a first indication signal, a second indication signal, and the detection signal, and provide the clamping trigger signal to the clamping state control circuit via a third node. An active level of the first indication signal indicates that the feedback voltage is greater than or equal to the first reference voltage. An active level of the second indication signal indicates that a main phase inductor current of the DC-DC converter reaches a peak value. The clamping state control circuit is configured to generate a clamping state control signal according to the first indication signal, the detection signal, and the clamping trigger signal, and provide the clamping state control signal to the clamping signal control circuit via a fourth node. The clamping signal control circuit is configured to clamp a voltage value of the clamping signal at a clamping reference voltage when the clamping state control signal is at an active level.

[0006] In some embodiments of the present disclosure, the clamping signal generating circuit is further configured to clamp a valley value of the clamping signal according to the first indication signal.

[0007] In some embodiments of the present disclosure, the clamping signal generating circuit comprises an error amplifier. A first input terminal of the error amplifier is coupled to the first reference voltage terminal. A second input terminal of the error amplifier is provided with the feedback voltage. An output terminal of the error amplifier is coupled to the first node.

[0008] In some embodiments of the present disclosure, the clamping signal amplitude detecting circuit comprises a hysteretic voltage comparator. A first input terminal of the hysteretic voltage comparator is coupled to the first node. A second input terminal of the hysteretic voltage comparator is coupled to the second reference voltage terminal. An output terminal of the hysteretic voltage comparator is coupled to the second node.

[0009] In some embodiments of the present disclosure, the clamping trigger circuit comprises a first AND gate, a first inverter, a second inverter, and an RS flip-flop. Wherein a first input terminal of the first AND gate is provided with the first indication signal. A second input terminal of the first AND gate is coupled to an output terminal of the first inverter. An output terminal of the first AND gate is coupled to an input terminal of the second inverter. An input terminal of the first inverter is coupled to the second node. An output terminal of the second inverter is coupled to a reset terminal of the RS flip-flop. A set terminal of the RS flip-flop is provided with the second indication signal, and a non-inverted output terminal of the RS flip-flop is coupled to the third node.

[0010] In some embodiments of the present disclosure, the clamping state control circuit comprises a third inverter, a monostable trigger, a fourth inverter, a fifth inverter, a D flip-flop, a second AND gate, and a third AND gate. Wherein an input terminal of the third inverter is coupled to the fourth node. An output terminal of the third inverter is coupled to an input terminal of the monostable trigger. An output terminal of the monostable trigger is coupled to an input terminal of the fourth inverter. An output terminal of the fourth inverter is coupled to a reset terminal of the D flip-flop. An input terminal of the fifth inverter is coupled to the second node. An output terminal of the fifth inverter is coupled to a clock signal terminal of the D flip-flop. A data input terminal of the D flip-flop is coupled to an inverted output terminal of the D flip-flop. A non-inverted output terminal of the D flip-flop is coupled to a first input terminal of the second AND gate. A second input terminal of the second AND gate is provided with the first indication signal. An output terminal of the second AND gate is coupled to a first input terminal of the third AND gate. A second input terminal of the third AND gate is coupled to the third node.

[0011] In some embodiments of the present disclosure, the monostable trigger is a rising edge triggered monostable trigger. The valid level of the output signal of the monostable trigger is a high level.

[0012] In some embodiments of the present disclosure, the clamping signal control circuit comprises a voltage-controlled switch and an operational amplifier. Wherein a controlled terminal of the voltage-controlled switch is coupled to the fourth node. A first terminal of the voltage-controlled switch is coupled to the first node. A second terminal of the voltage-controlled switch is coupled to a first input terminal of the operational amplifier and an output terminal of the operational amplifier. A second input terminal of the operational amplifier is provided with a clamping reference voltage.

[0013] In some embodiments of the present disclosure, the inductor current peak clamping circuit further comprises a delay circuit. Wherein the delay circuit is configured to delay the detection signal to generate a phase selection signal. Wherein the phase selection signal is provided to a phase selection circuit of the DC-DC converter. In a case that the phase selection signal is at a first level, the DC-DC converter is in a full phase on control mode. In a case that the phase selection signal is at a second level, the DC-DC converter is in a main phase on and auxiliary phase shielded control mode.

[0014] According to a second aspect of the present disclosure, an inductor current peak clamping circuit for a DC-DC converter is provided. The inductor current peak clamping circuit comprises an error amplifier, a hysteresis voltage comparator, a first AND gate, a first inverter, a second inverter, an RS flip-flop, a third inverter, a monostable trigger, a fourth inverter, a fifth inverter, a D flip-flop, a second AND gate, a third AND gate, a voltage-controlled switch, an operational amplifier, and a delay circuit. The first input terminal of the error amplifier is coupled to a first reference voltage terminal. The second input terminal of the error amplifier is provided with a feedback voltage of the DC-DC converter. The output terminal of the error amplifier is coupled to the first input terminal of the hysteresis voltage comparator and the first terminal of the voltage-controlled switch. The second input terminal of the hysteresis voltage comparator is coupled to a second reference voltage terminal. The output terminal of the hysteresis voltage comparator is coupled to the input terminal of the first inverter and the input terminal of the fifth inverter. The output terminal of the first inverter is coupled to the second input terminal of the first AND gate. The first input terminal of the first AND gate is provided with a first indication signal. The output terminal of the first AND gate is coupled to the input terminal of the second inverter. The active level of the first indication signal indicates that the feedback voltage is greater than or equal to the first reference voltage from the first reference voltage terminal. The output terminal of the second inverter is coupled to the reset terminal of the RS flip-flop. The set terminal of the RS flip-flop is provided with a second indication signal. The non-inverting output terminal of the RS flip-flop is coupled to the second input terminal of the third AND gate. The active level of the second indication signal indicates that the primary inductor current of the DC-DC converter reaches a peak value. The input terminal of the third inverter is coupled to the output terminal of the third AND gate. The output terminal of the third inverter is coupled to the input terminal of the monostable trigger. The output terminal of the monostable trigger is coupled to the input terminal of the fourth inverter. The output terminal of the fourth inverter is coupled to the reset terminal of the D flip-flop. The output terminal of the fifth inverter is coupled to the clock signal terminal of the D flip-flop. The data input terminal of the D flip-flop is coupled to the inverting output terminal of the D flip-flop. The non-inverting output terminal of the D flip-flop is coupled to the first input terminal of the second AND gate. The second input terminal of the second AND gate is provided with the first indication signal. The output terminal of the second AND gate is coupled to the first input terminal of the third AND gate. The output terminal of the third AND gate is coupled to the controlled terminal of the voltage-controlled switch. The second terminal of the voltage-controlled switch is coupled to the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The second input terminal of the operational amplifier is provided with a clamping reference voltage. The input terminal of the delay circuit is coupled to the output terminal of the hysteresis voltage comparator. The delay circuit is configured to delay a detection signal output from the output terminal of the hysteresis voltage comparator to generate a phase selection signal. The phase selection signal is provided to a phase selection circuit of the DC-DC converter. When the phase selection signal is at a first level, the DC-DC converter is in a full-phase-on control mode. When the phase selection signal is at a second level, the DC-DC converter is in a primary-phase-on and secondary-phase-masked control mode.

[0015] According to a third aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter comprises the inductor current peak clamping circuit according to the first aspect or the second aspect of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some of the embodiments of the present disclosure, rather than limiting the present disclosure. Among them:

[0017] Figure 1 is an exemplary circuit diagram of an inductor current peak clamping circuit for a DC-DC converter;

[0018] Figure 2 is an exemplary circuit diagram of an inductor current peak clamping circuit for a DC-DC converter; Figure 1 is an exemplary timing diagram of some signals of the inductor current peak clamping circuit shown in FIG. 2;

[0019] Figure 3 is a schematic block diagram of an inductor current peak clamping circuit for a DC-DC converter according to an embodiment of the present disclosure;

[0020] Figure 4 is an exemplary circuit diagram of an inductor current peak clamping circuit for a DC-DC converter according to an embodiment of the present disclosure;

[0021] Figure 5 is another exemplary circuit diagram of an inductor current peak clamping circuit for a DC-DC converter according to an embodiment of the present disclosure; and

[0022] Figure 6 is an exemplary circuit diagram of an inductor current peak clamping circuit for a DC-DC converter; Figure 5 is an exemplary timing diagram of some signals of the inductor current peak clamping circuit shown in FIG. 2.

[0023] In the drawings, the same reference signs correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort are also within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts or components are "connected" or "coupled" together shall mean that the parts or components are joined or operate together either directly or through one or more intermediate parts or components.

[0026] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current direction between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor is opposite, in the embodiments of the present disclosure, the controlled middle terminal of the transistor is referred to as the control electrode, and the remaining two terminals of the transistor are referred to as the first electrode and the second electrode, respectively. The transistor used in the embodiments of the present disclosure is mainly a switching transistor. In addition, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0027] In the design of inductor current peak clamping, the entry and exit of clamping is usually based on the quantization result of error amplification of the feedback (i.e., feedback voltage) of the output voltage of the DC-DC converter and the reference voltage. In a control system with good feedback regulation capability, the system has sufficient bandwidth, and the response of the error amplifier is quite fast, so the error quantization result of its output is extremely easy to change, which in turn easily causes the repeated entry and exit of the peak current clamping in the process of output voltage stabilization, resulting in a large output voltage ripple, and even causes large signal oscillation in severe cases.

[0028] Figure 1 An exemplary circuit diagram of an inductor current peak clamping circuit 100 for a DC-DC converter is shown. The inductor current peak clamping circuit 100 includes an error amplifier EA, a hysteresis voltage comparator COMP, a first inverter NG1, a first AND gate AND1, a second inverter NG2, an RS flip-flop LH, an operational amplifier AMP, and a voltage-controlled switch S1.

[0029] In Figure 1In the example, a feedback voltage VFB of the DC-DC converter is input to the inverting input of the error amplifier EA. A first reference voltage VREF1 (as a reference of the output voltage) is input to the non-inverting input of the error amplifier EA. The error amplifier EA can amplify the voltage difference between the first reference voltage VREF1 and the feedback voltage VFB to generate a signal EAO. In the DC-DC converter with the peak current mode control, the signal EAO can be used to adjust the peak value of the inductor current of the DC-DC converter, which in turn represents the voltage level of the applied load of the DC-DC converter at the moment.

[0030] The signal EAO is provided to the non-inverting input of the hysteretic voltage comparator COMP. The inverting input of the hysteretic voltage comparator COMP is provided with a second reference voltage VREF2. In the case that the voltage at the non-inverting input of the hysteretic voltage comparator COMP is lower than the voltage at the inverting input, the second reference voltage VREF2 is set to a first value VH. The voltage at the non-inverting input of the hysteretic voltage comparator COMP needs to be higher than or equal to the first value VH for the output signal of the hysteretic voltage comparator COMP to flip to high. In the case that the voltage at the non-inverting input of the hysteretic voltage comparator COMP is higher than the voltage at the inverting input, the second reference voltage VREF2 is set to a second value VL. The voltage at the non-inverting input of the hysteretic voltage comparator COMP needs to be lower than the second value VL for the output signal of the hysteretic voltage comparator COMP to flip to low. The first value VH is higher than the second value VL.

[0031] In the case that the level of the applied load of the DC-DC converter becomes heavy, the voltage value of the feedback voltage VFB decreases, thereby causing the voltage value of the signal EAO to increase. When the voltage value of the signal EAO is higher than or equal to the first value VH of the second reference voltage VREF2, the output signal of the hysteretic voltage comparator COMP flips to high. The output signal of the hysteretic voltage comparator COMP can be output as a phase selection signal PHASE SEL to a phase selection circuit of the DC-DC converter. The phase selection signal PHASE SEL at high can cause the DC-DC converter to be in a full-phase-on control mode.

[0032] In the case that the level of the applied load of the DC-DC converter becomes light, the voltage value of the feedback voltage VFB increases, thereby causing the voltage value of the signal EAO to decrease. When the voltage value of the signal EAO is lower than the second value VL of the second reference voltage VREF2, the output signal (the phase selection signal PHASE SEL) of the hysteretic voltage comparator COMP flips to low. The phase selection signal PHASE SEL at low can cause the DC-DC converter to be in a main-phase-on only and sub-phase-masked control mode.

[0033] A low-level phase selection signal PHASE_SEL is input to the input of the first inverter NG1, causing the output of the first inverter NG1 to be a high-level signal. This high-level signal is then provided to one input of the first AND gate AND1. The other input of the first AND gate AND1 is provided with a signal LPM. Signal LPM represents the comparison result between the feedback voltage VFB and the first reference voltage VREF1. Signal LPM is high when the feedback voltage VFB is higher than or equal to the first reference voltage VREF1, and low otherwise.

[0034] The IPEAK signal is a pulse signal representing the peak value of the main phase inductor current of the DC-DC converter. The amplitude of the IPEAK_CLAMP signal represents the voltage value corresponding to the peak inductor current sampling signal at 0A. The EAO_CLAMP signal is the control signal for the clamping switch S1.

[0035] exist Figure 1 In the example, when the DC-DC converter is fully operational and the output voltage is high enough that the signal EAO falls below the second value VL of the second reference voltage VREF2, the output voltage of the hysteresis voltage comparator COMP flips from high to low. The low-level phase selection signal PHASE_SEL is output to the phase selection circuit of the DC-DC converter, thereby selecting the control mode where the main phase is on and the secondary phase is shielded (single-phase control mode). Since the signal LPM flips to high when the feedback voltage VFB is slightly higher than the first reference voltage VREF1, the DC-DC converter in single-phase control mode will output the signal EAO_CLAMP, which flips from low to high, when the next pulse of the signal IPEAK arrives, through the setting of the RS flip-flop LH. The high-level signal EAO_CLAMP can close the clamping switch S1, thus clamping the voltage value of the signal EAO to the amplitude of the signal IPEAK_CLAMP, thereby clamping the peak value of the inductor current to 0A. Under these conditions, if the DC-DC converter using adaptive turn-off time loop regulation is in FCCM mode, the average value of the inductor current of the DC-DC converter is negative, and the output voltage gradually drops through the energy dissipation of the power stage in the DC-DC converter.

[0036] exist Figure 1In the example, since the signal LPM can flip from high to low when the feedback voltage VFB is slightly lower than the first reference voltage VREF1, the drop in the output voltage of the DC-DC converter can easily cause the DC-DC converter to exit the 0A inductor current peak clamp. However, the rebound in output voltage caused by the inductor current adjusting to the current applied load after exiting the 0A inductor current peak clamp can easily cause it to re-enter the 0A inductor current peak clamp. This cycle repeats, leading to a deterioration in the output voltage ripple of the DC-DC converter or even causing oscillation.

[0037] Figure 2 It shows the use of Figure 1 The diagram shows an exemplary timing diagram of some signals in the inductor current peak clamping circuit. Before time T1, the output voltage VOUT of the DC-DC converter gradually increases as the load lightens. At time T1, the feedback voltage VFB is higher than the first reference voltage VREF1, so the signal LPM flips to a high level. At time T2, the voltage difference between the feedback voltage VFB and the first reference voltage VREF1 widens, causing the signal EAO to fall below the second value VL of the second reference voltage VREF2. Therefore, the phase selection signal PHASE_SEL flips to a low level, and the DC-DC converter enters a control mode where the primary phase is on and the secondary phase is shielded. The secondary phase inductor current i L2 to i Li It becomes 0A. At time T3, the main phase inductor current i L1 When a peak occurs, the IPEAK signal becomes a high-level pulse. This triggers the RS flip-flop, causing the EAO_CLAMP signal to flip high. The high-level EAO_CLAMP signal closes the clamping switch S1, clamping the voltage value of the EAO signal to the amplitude of the IPEAK_CLAMP signal, thus clamping the peak inductor current to 0A. At time T4, the output voltage VOUT of the DC-DC converter drops below the preset value, causing the feedback voltage VFB to fall below the first reference voltage VREF1, thus causing the LPM signal to flip low. The RS flip-flop is reset, outputting the low-level EAO_CLAMP signal. The low-level EAO_CLAMP signal opens the clamping switch S1. The peak inductor current is no longer clamped to 0A. The main phase inductor current iL1 increases. At time T5, the feedback voltage VFB again exceeds the first reference voltage VREF1. This cycle repeats. In the power stage of a DC-DC converter, repeated discharging and charging occur, which worsens the output voltage ripple of the DC-DC converter, resulting in an unstable state of large-signal oscillation.

[0038] Embodiments of this disclosure provide an inductor current peak clamping circuit for a DC-DC converter to avoid the aforementioned problems. Figure 3A schematic block diagram of an inductor current peak clamping circuit 300 for a DC-DC converter according to an embodiment of the present disclosure is shown.

[0039] The inductor current peak clamping circuit 300 can include a clamping signal generation circuit 310, a clamping signal amplitude detection circuit 320, a clamping trigger circuit 330, a clamping state control circuit 340, and a clamping signal control circuit 350.

[0040] The clamping signal generation circuit 310 can couple the clamping signal amplitude detection circuit 320 and the clamping signal control circuit 350 via a first node N1. The clamping signal generation circuit 310 can also couple a first reference voltage terminal VREF1 and a feedback voltage terminal VFB of the DC-DC converter. The clamping signal generation circuit 310 can be configured to generate a clamping signal EAO according to the feedback voltage VFB of the DC-DC converter and a first reference voltage VREF1 from the first reference voltage terminal VREF1, and provide the clamping signal EAO to the clamping signal amplitude detection circuit 320 via the first node N1. Wherein, the clamping signal EAO is used to adjust the peak value of the inductor current of the DC-DC converter. In some embodiments of the present disclosure, the clamping signal EAO can reflect the voltage difference between the feedback voltage VFB and the first reference voltage VREF1.

[0041] In some embodiments of the present disclosure, although not shown in Figure 3 The clamping signal generation circuit 310 can also be provided with a first indication signal LPM, and be configured to clamp the valley value of the clamping signal EAO according to the first indication signal LPM. Wherein, the active level of the first indication signal LPM indicates that the feedback voltage VFB is greater than or equal to the first reference voltage VREF1. In the case that the first indication signal LPM is at the active level, the clamping signal generation circuit 310 can limit the valley value of the clamping signal EAO so as to prevent the amplitude of the clamping signal EAO from being too low to cause the peak value of the inductor current to be too low.

[0042] The clamping signal amplitude detection circuit 320 can be coupled to the clamping signal generation circuit 310 and the clamping signal control circuit 350 via a first node N1. The clamping signal amplitude detection circuit 320 can be coupled to the clamping trigger circuit 330 and the clamping state control circuit 340 via a second node N2. The clamping signal amplitude detection circuit 320 can also be coupled to a second reference voltage terminal VREF2. The clamping signal amplitude detection circuit 320 can be configured to generate a detection signal N_OUT according to the clamping signal EAO and a second reference voltage VREF2 from the second reference voltage terminal VREF2, and provide the detection signal N_OUT to the clamping trigger circuit 330 and the clamping state control circuit 340 via the second node N2. In some embodiments of the present disclosure, the second reference voltage VREF2 can have a first value VH and a second value VL. A first level (e.g., a high level) of the detection signal N_OUT can indicate that the clamping signal EAO falls below the second value VL. A second level (e.g., a low level) of the detection signal N_OUT can indicate that the clamping signal EAO rises above the first value VH.

[0043] The clamping trigger circuit 330 can be coupled to the clamping signal amplitude detection circuit 320 and the clamping state control circuit 340 via the second node N2. The clamping trigger circuit 330 can be coupled to the clamping state control circuit 340 via a third node N3. The clamping trigger circuit 330 can be provided with a first indication signal LPM and a second indication signal IPEAK. An active level of the second indication signal IPEAK indicates that the main phase inductor current of the DC-DC converter reaches a peak value. In the case that the main phase inductor current of the DC-DC converter reaches the peak value, the second indication signal IPEAK can present as a pulse signal. In one example, the pulse signal is a pulse signal of high level. The clamping trigger circuit 330 can be configured to generate a clamping trigger signal EAO_TRG according to the first indication signal LPM, the second indication signal IPEAK, and the detection signal N_OUT, and provide the clamping trigger signal EAO_TRG to the clamping state control circuit 340 via the third node N3. In some embodiments of the present disclosure, the clamping trigger signal EAO_TRG is at an active level in the case that the first indication signal LPM, the second indication signal IPEAK, and the detection signal N_OUT are all at active levels.

[0044] The clamping state control circuit 340 can be coupled to the clamping signal amplitude detection circuit 320 and the clamping trigger circuit 330 via a second node N2. The clamping state control circuit 340 can be coupled to the clamping trigger circuit 330 via a third node N3. The clamping state control circuit 340 can be coupled to the clamping signal control circuit 350 via a fourth node N4. The clamping state control circuit 340 can be further provided with a first indication signal LPM. The clamping state control circuit 340 can be configured to generate a clamping state control signal EAO_CLAMP according to the first indication signal LPM, the detection signal N_OUT, and the clamping trigger signal EAO_TRG, and provide the clamping state control signal EAO_CLAMP to the clamping signal control circuit 350 via the fourth node N4. In some embodiments of the present disclosure, the clamping state control signal EAO_CLAM is at an active level in the case that both the first indication signal LPM and the clamping trigger signal EAO_TRG are at active levels and the detection signal N_OUT is at a rising edge.

[0045] The clamping signal control circuit 350 can be coupled to the clamping signal generation circuit 310 and the clamping signal amplitude detection circuit 320 via a first node N1. The clamping signal control circuit 350 can be coupled to the clamping state control circuit 340 via the fourth node N4. The clamping signal control circuit 350 can be further coupled to a clamping reference voltage terminal IPEAK_CLAMP. The clamping signal control circuit 350 can be configured to clamp the voltage value of the clamping signal EAO at the clamping reference voltage IPEAK_CLAMP from the clamping reference voltage terminal IPEAK_CLAMP in the case that the clamping state control signal EAO_CLAMP is at an active level. The amplitude of the clamping reference voltage IPEAK_CLAMP is set as the corresponding voltage value of the inductor current peak value sampling signal at 0A. In the case that the voltage value of the clamping signal EAO is clamped at the clamping reference voltage IPEAK_CLAMP, the DC-DC converter enters the inductor current peak value clamping at 0A, at which time the average value of the inductor current of the DC-DC converter is negative.

[0046] The inductor current peak value clamping circuit 300 according to the embodiments of the present disclosure can exit the inductor current peak value clamping at 0A in the case that the first indication signal LPM flips to an inactive level, and the DC-DC converter will not enter the inductor current peak value clamping at 0A again on the premise that the applied load does not change.

[0047] Figure 4 An exemplary circuit diagram of an inductor current peak value clamping circuit 400 for a DC-DC converter according to embodiments of the present disclosure is shown.

[0048] The clamping signal generating circuit 410 can include an error amplifier EA. A first input terminal of the error amplifier EA is coupled to the first reference voltage terminal VREF1. A second input terminal of the error amplifier EA is provided with the feedback voltage VFB. An output terminal of the error amplifier EA is coupled to the first node N1. In some embodiments of the present disclosure, as shown in FIG. 4, the error amplifier EA can also be provided with the first indication signal LPM. The error amplifier EA can clamp the valley value of the clamping signal EAO according to the first indication signal LPM. In the case that the first indication signal LPM is at an effective level, the error amplifier EA can limit the valley value of the clamping signal EAO so as to prevent the amplitude of the clamping signal EAO from being too low to cause the peak value of the inductor current to be too low. Figure 4

[0049] The clamping signal amplitude detecting circuit 420 can include a hysteretic voltage comparator COMP. A first input terminal of the hysteretic voltage comparator COMP is coupled to the first node N1. A second input terminal of the hysteretic voltage comparator COMP is coupled to the second reference voltage terminal VREF2. An output terminal of the hysteretic voltage comparator COMP is coupled to the second node N2.

[0050] The clamping trigger circuit 430 can include a first AND gate AND1, a first inverter NG1, a second inverter NG2, and an RS flip-flop LH. A first input terminal of the first AND gate AND1 is provided with the first indication signal LPM. A second input terminal of the first AND gate AND1 is coupled to an output terminal of the first inverter NG1. An output terminal of the first AND gate AND1 is coupled to an input terminal of the second inverter NG2. An input terminal of the first inverter NG1 is coupled to the second node. An output terminal of the second inverter NG2 is coupled to a reset terminal R of the RS flip-flop LH. A set terminal S of the RS flip-flop LH is provided with the second indication signal IPEAK. A non-inverted output terminal Q of the RS flip-flop LH is coupled to the third node N3.

[0051] The clamping state control circuit 440 can include a third inverter NG3, a monostable trigger 441, a fourth inverter NG4, a fifth inverter NG5, a D flip-flop DT, a second AND gate AND2, and a third AND gate AND3. An input terminal of the third inverter NG3 is coupled to the fourth node N4. An output terminal of the third inverter NG3 is coupled to an input terminal of the monostable trigger 441. An output terminal of the monostable trigger 441 is coupled to an input terminal of the fourth inverter NG4. An output terminal of the fourth inverter NG4 is coupled to a reset terminal Reset of the D flip-flop DT. An input terminal of the fifth inverter NG5 is coupled to the second node N2. An output terminal of the fifth inverter NG5 is coupled to a clock signal terminal Clk of the D flip-flop DT. A data input terminal D of the D flip-flop DT is coupled to an inverted output terminal Q of the D flip-flop DT ​The non-inverting output terminal Q of the D flip-flop DT is coupled to the first input terminal of the second AND gate AND2. The second input terminal of the second AND gate AND2 is provided with the first indication signal LPM. The output terminal of the second AND gate AND2 is coupled to the first input terminal of the third AND gate AND3. The second input terminal of the third AND gate AND3 is coupled to the third node N3.

[0052] In some embodiments of the present disclosure, the monostable flip-flop 441 is a rising edge triggered monostable flip-flop 441. The active level of the output signal of the monostable flip-flop 441 is a high level.

[0053] The clamping signal control circuit 450 can include a voltage-controlled switch S1 and an operational amplifier AMP. The controlled terminal of the voltage-controlled switch S1 is coupled to the fourth node N4. The first terminal of the voltage-controlled switch S1 is coupled to the first node N1. The second terminal of the voltage-controlled switch S1 is coupled to the first input terminal of the operational amplifier AMP and the output terminal of the operational amplifier AMP. The second input terminal of the operational amplifier AMP is provided with the clamping reference voltage IPEAK_CLAMP.

[0054] Those skilled in the art should understand that, Figure 4 The internal structures of various circuits in the above embodiments are exemplary, and the above circuits can also be implemented by other variants. The embodiments of the present disclosure do not limit the specific implementation manner of the above circuits.

[0055] Figure 5 Another exemplary circuit diagram of the inductor current peak clamping circuit 500 for a DC-DC converter according to an embodiment of the present disclosure is shown. In the exemplary circuit diagram of the inductor current peak clamping circuit 500, Figure 4 On the basis of the example of the inductor current peak clamping circuit 500, the inductor current peak clamping circuit 500 can further include a delay circuit 560. The input terminal of the delay circuit 560 can be coupled to the second node N2. The output terminal of the delay circuit 560 can be coupled to the phase selection circuit (not shown) of the DC-DC converter. The delay circuit 560 can be configured to perform delay processing on the detection signal N_OUT to generate a phase selection signal PHASE_SEL. The phase selection signal PHASE_SEL is provided to the phase selection circuit of the DC-DC converter. In the case where the phase selection signal PHASE_SEL is at a first level (for example, a high level), the DC-DC converter is in a full-phase-on control mode. In the case where the phase selection signal PHASE_SEL is at a second level (for example, a low level), the DC-DC converter is in a main-phase-on and auxiliary-phase-screening control mode.

[0056] Figure 6 Another exemplary circuit diagram of the inductor current peak clamping circuit 500 for a DC-DC converter according to an embodiment of the present disclosure is shown. In the exemplary circuit diagram of the inductor current peak clamping circuit 500, Figure 5 An exemplary timing diagram of some signals of the inductor current peak clamping circuit 500 shown in FIG. 5 is shown. The following describes the exemplary timing diagram of some signals of the inductor current peak clamping circuit 500 shown in FIG. 5 in conjunction with Figure 5 and Figure 6The working process of the inductance current peak clamping circuit 500 according to the embodiments of the present disclosure is described by taking the example of the working process of the inductance current peak clamping circuit 500 shown in FIG. 5.

[0057] In Figure 6 Before the time t1 shown in the figure, the output voltage VOUT of the DC-DC converter gradually rises as the load becomes lighter, at which time the DC-DC converter has been fully opened. At the time t1, the feedback voltage VFB is higher than the first reference voltage VREF1, so the first indication signal LPM flips to the high level. When the output voltage VOUT rises and the clamping signal EAO falls below the second value VL of the second reference voltage VREF2, the detection voltage N_OUT output by the hysteresis voltage comparator COMP flips from the high level to the low level. Therefore, the signal provided to the clock signal end Clk of the D flip-flop DT flips from the low level to the high level. The D flip-flop DT outputs the high level signal from the in-phase output end Q. Since both input ends of the second AND gate AND2 are input with the high level signal, the second AND gate AND2 outputs the high level signal. At this time, due to the action of the delay circuit 560, the phase selection signal PHASE_SEL does not immediately flip with the flip of the detection voltage N_OUT, and the DC-DC converter is still fully opened.

[0058] At the time t2, the main phase inductance current i L1 peaks, and the second indication signal IPEAK presents the high level pulse. In this way, the RS flip-flop LH is triggered, so that the clamping trigger signal EAO_TRG flips to the high level. Since both input ends of the third AND gate AND3 are input with the high level signal, the clamping state control signal EAO_CLAMP flips to the high level. The clamping state control signal EAO_CLAMP at the high level can make the clamping switch S1 closed, so that the voltage value of the clamping signal EAO is clamped at the amplitude of the clamping reference voltage IPEAK_CLAMP, thereby clamping the peak of the inductance current to 0A.

[0059] In the time duration designed by the delay circuit 560, the average of each phase inductor current is negative, and the energy discharge speed of the power stage of the DC-DC converter is more obvious compared with the single-phase DC-DC converter. If the applied load level of the DC-DC converter is light, the DC-DC converter will discharge the output voltage to the rising of the clamping signal EAO to the second value VL above in the time duration of the peak value of the inductor current of 0A clamping state, and the maintaining time duration is longer than the time duration designed by the delay circuit 560. At the time t3, the phase selection signal PHASE_SEL controlled by the delay circuit 560 is flipped to low. The DC-DC converter enters the working state of single-phase regulation. The output voltage VOUT of the DC-DC converter is reduced to below the preset value at the time t4, so that the feedback voltage VFB is lower than the first reference voltage VREF1, and thus the first indication signal LPM is flipped to low. The RS flip-flop LH is reset, so that the clamping trigger signal EAO_TRG of low level is output. Therefore, the clamping state control signal EAO_CLAMP is flipped to low. The DC-DC converter exits the peak value of the inductor current of 0A clamping state.

[0060] In the clamping state control circuit 440, since the clamping state control signal EAO_CLAMP is flipped from high to low, the monostable trigger outputs a pulse signal of high level. After the inversion of the fourth inverter NG4, the D flip-flop DT is reset, so that a signal of low level is output from the non-inverted output end. Under this condition, the peak value of the inductor current of 0A clamping state will only exit after the first time that the first indication signal LPM is flipped from high to low, and cannot enter again under the premise that the applied load does not change (the peak value of the inductor current of 0A clamping state can enter again only when the detection signal N_OUT is flipped from high to low again). The DC-DC converter will adjust the output voltage VOUT to the stable state by single-phase load carrying.

[0061] Although it is not shown in Figure 6 , if the applied load level of the DC-DC converter is heavy, the clamping state of the DC-DC converter will not last for more than the time duration designed by the delay circuit 560, and the DC-DC converter will still maintain full-phase load carrying and adjust the output voltage to the stable state after the clamping state exits. Under the premise that the applied load does not change, the DC-DC converter will not enter the clamping state again.

[0062] In summary, the inductor current peak clamping circuit according to the embodiments of the present disclosure can avoid the DC-DC converter repeatedly entering and exiting the inductor current peak clamping state of 0A. The entering of the inductor current peak clamping state of 0A requires the first indication signal LPM to flip to high level while the detection signal of the D flip-flop DT locking the output of the hysteresis voltage comparator COMP flips from high level to low level. In the inductor current peak clamping state of 0A, the output voltage VOUT is discharged by the multi-phase negative average current until the clamping signal EAO rises above the second value VL and maintains a sufficient delay time, and the DC-DC converter still remains at a high level. Until the output voltage VOUT is discharged to a magnitude slightly lower than the first reference signal VREF1 by the single-phase negative current, the DC-DC converter exits the inductor current peak clamping state of 0A. Under the premise that the external load remains unchanged, the DC-DC converter will maintain a single-phase working state for loop regulation, which is of great significance to the stability of the output voltage in the FCCM mode. In addition, the inductor current peak clamping circuit can limit the valley value of the clamping signal EAO to prevent the amplitude of the clamping signal EAO from being too low, resulting in a too low peak value of the inductor current.

[0063] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of "a," "an," and "the" herein and in the following claims are to be construed as meaning "one or more" unless the context dictates otherwise. Similarly, the words "comprise," "comprises," and "comprising," and the like, when used in the following description and claims, are understood to be inclusive or open-ended and specifically intended to mean "including but not limited to." Likewise, the term "comprising" and / or "comprises" each means the following embodiments: A / B comprising C; A / B comprising C and D; A / B comprising C, D, and E; only A; only B; only C; only D; only E; A and / or B; A and / or B and / or C; A and / or B and / or C and / or D; A and / or B and / or C and / or D and / or E; etc. The terms "program" or software are used herein in a broad sense to include one or more computer programs, and / or executable logic, which can be written in any suitable programming language, and / or implemented in hardware or firmware, and / or any combination thereof.

[0064] Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for illustrative purposes only and are not intended to limit the scope of the present application.

[0065] The above detailed description of several embodiments of the present disclosure has been described, but it is obvious to those skilled in the art that various modifications and variations of the embodiments of the present disclosure can be made without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. An inductor current peak clamping circuit for a DC-DC converter, comprising: The clamp signal generation circuit, the clamp signal amplitude detection circuit, the clamp trigger circuit, the clamp state control circuit, and the clamp signal control circuit, The clamp signal generation circuit is configured to generate a clamp signal according to a feedback voltage of the DC-DC converter and a first reference voltage from a first reference voltage terminal, and provide the clamp signal to the clamp signal amplitude detection circuit via a first node, wherein the clamp signal indicates a voltage difference between the feedback voltage and the first reference voltage, and the clamp signal is used to adjust a peak value of an inductor current of the DC-DC converter. The clamp signal amplitude detection circuit is configured to generate a detection signal according to the clamp signal and a second reference voltage from a second reference voltage terminal, and provide the detection signal to the clamp trigger circuit and the clamp state control circuit via a second node, wherein the second reference voltage includes a first value and a second value, the first value is higher than the second value, a first level of the detection signal indicates that the clamp signal drops below the second value, and a second level of the detection signal indicates that the clamp signal rises above the first value. The clamp trigger circuit is configured to generate a clamp trigger signal according to a first indication signal, a second indication signal, and the detection signal, and provide the clamp trigger signal to the clamp state control circuit via a third node, wherein the first indication signal is in an effective level when the feedback voltage is greater than or equal to the first reference voltage, the second indication signal is in an effective level when a main phase inductor current of the DC-DC converter reaches a peak value, and the clamp trigger signal is in an effective level when the first indication signal, the second indication signal, and the detection signal are all in the effective level. The clamp state control circuit is configured to generate a clamp state control signal according to the first indication signal, the detection signal, and the clamp trigger signal, and provide the clamp state control signal to the clamp signal control circuit via a fourth node, wherein the clamp state control signal is in an effective level when the first indication signal and the clamp trigger signal are both in the effective level and the detection signal flips from a high level to a low level. The clamp signal control circuit is configured to clamp a voltage value of the clamp signal at a clamp reference voltage when the clamp state control signal is in the effective level.

2. The inductor current peak clamping circuit of claim 1, wherein, The clamp signal generation circuit is further configured to clamp a valley value of the clamp signal according to the first indication signal.

3. The inductor current peak clamping circuit of claim 1 or 2, wherein, The clamp signal generation circuit includes an error amplifier, wherein a first input terminal of the error amplifier is coupled to the first reference voltage terminal, a second input terminal of the error amplifier is provided with the feedback voltage, and an output terminal of the error amplifier is coupled to the first node.

4. The inductor current peak clamping circuit of claim 1, wherein, The clamp signal amplitude detection circuit includes a hysteresis voltage comparator, The first input end of the hysteresis voltage comparator is coupled to the first node, the second input end of the hysteresis voltage comparator is coupled to the second reference voltage end, and the output end of the hysteresis voltage comparator is coupled to the second node.

5. The inductor current peak clamping circuit of claim 1, wherein, The clamp trigger circuit comprises a first AND gate, a first inverter, a second inverter, and an RS flip-flop, The first input end of the first AND gate is provided with the first indication signal, the second input end of the first AND gate is coupled to the output end of the first inverter, and the output end of the first AND gate is coupled to the input end of the second inverter; The input end of the first inverter is coupled to the second node; The output end of the second inverter is coupled to the reset end of the RS flip-flop; The set end of the RS flip-flop is provided with the second indication signal, and the non-inverted output end of the RS flip-flop is coupled to the third node.

6. The inductor current peak clamping circuit of claim 1, wherein, The clamp state control circuit comprises a third inverter, a monostable trigger, a fourth inverter, a fifth inverter, a D flip-flop, a second AND gate, and a third AND gate, The input end of the third inverter is coupled to the fourth node, and the output end of the third inverter is coupled to the input end of the monostable trigger; The output end of the monostable trigger is coupled to the input end of the fourth inverter; The output end of the fourth inverter is coupled to the reset end of the D flip-flop; The input end of the fifth inverter is coupled to the second node, and the output end of the fifth inverter is coupled to the clock signal end of the D flip-flop; The data input end of the D flip-flop is coupled to the inverted output end of the D flip-flop, and the non-inverted output end of the D flip-flop is coupled to the first input end of the second AND gate; The second input end of the second AND gate is provided with the first indication signal, and the output end of the second AND gate is coupled to the first input end of the third AND gate; The second input end of the third AND gate is coupled to the third node.

7. The inductor current peak clamping circuit of claim 1, wherein, The clamp signal control circuit comprises a voltage-controlled switch and an operational amplifier, The controlled end of the voltage-controlled switch is coupled to the fourth node, the first end of the voltage-controlled switch is coupled to the first node, and the second end of the voltage-controlled switch is coupled to the first input end of the operational amplifier and the output end of the operational amplifier; The second input end of the operational amplifier is provided with the clamp reference voltage.

8. The inductor current peak clamping circuit of any one of claims 1-2 and 4-7, further comprising: A delay circuit, The delay circuit is configured to perform delay processing on the detection signal to generate a phase selection signal. The phase selection signal is provided to a phase selection circuit of the DC-DC converter; in a case where the phase selection signal is at a first level, the DC-DC converter is in a control mode of full-phase opening; and in a case where the phase selection signal is at a second level, the DC-DC converter is in a control mode of main-phase opening and auxiliary-phase shielding.

9. An inductor current peak clamping circuit for a DC-DC converter, comprising: An error amplifier, a hysteresis voltage comparator, a first AND gate, a first inverter, a second inverter, an RS flip-flop, a third inverter, a monostable trigger, a fourth inverter, a fifth inverter, a D flip-flop, a second AND gate, a third AND gate, a voltage-controlled switch, an operational amplifier, and a delay circuit, The first input end of the error amplifier is coupled with a first reference voltage terminal, the second input end of the error amplifier is provided with a feedback voltage of the DC-DC converter, and the output end of the error amplifier is coupled with the first input end of the hysteresis voltage comparator and the first end of the voltage-controlled switch. The second input end of the hysteresis voltage comparator is coupled with a second reference voltage terminal, and the output end of the hysteresis voltage comparator is coupled with the input end of the first inverter and the input end of the fifth inverter. The output end of the first inverter is coupled with the second input end of the first AND gate. The first input end of the first AND gate is provided with a first indication signal, and the output end of the first AND gate is coupled with the input end of the second inverter, wherein the active level of the first indication signal indicates that the feedback voltage is greater than or equal to the first reference voltage from the first reference voltage terminal. The output end of the second inverter is coupled with the reset end of the RS flip-flop. The set end of the RS flip-flop is provided with a second indication signal, and the non-inverted output end of the RS flip-flop is coupled with the second input end of the third AND gate, wherein the active level of the second indication signal indicates that the main phase inductance current of the DC-DC converter reaches a peak value. The input end of the third inverter is coupled with the output end of the third AND gate, and the output end of the third inverter is coupled with the input end of the monostable trigger. The output end of the monostable trigger is coupled with the input end of the fourth inverter, and the output end of the fourth inverter is coupled with the reset end of the D flip-flop. The output end of the fifth inverter is coupled with the clock signal end of the D flip-flop. The data input end of the D flip-flop is coupled with the inverted output end of the D flip-flop, and the non-inverted output end of the D flip-flop is coupled with the first input end of the second AND gate. The second input end of the second AND gate is provided with the first indication signal, and the output end of the second AND gate is coupled with the first input end of the third AND gate. The output end of the third AND gate is coupled with the controlled end of the voltage-controlled switch. The second end of the voltage-controlled switch is coupled with the first input end of the operational amplifier and the output end of the operational amplifier. The second input end of the operational amplifier is provided with a clamping reference voltage. The input end of the delay circuit is coupled with the output end of the hysteresis voltage comparator, and the delay circuit is configured to perform delay processing on a detection signal output from the output end of the hysteresis voltage comparator to generate a phase selection signal. The phase selection signal is provided to a phase selection circuit of the DC-DC converter; in the case that the phase selection signal is at a first level, the DC-DC converter is in a full-phase open control mode; in the case that the phase selection signal is at a second level, the DC-DC converter is in a main phase open and auxiliary phase shielding control mode.

10. A DC-DC converter comprising: The inductance current peak value clamping circuit according to any one of claims 1 to 9. The inductance current peak value clamping circuit according to any one of claims 1 to 9.

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