An operational amplifier

Abstract

The present invention provides an operational amplifier, comprising: a first operational amplifier unit and a second operational amplifier unit, wherein the first operational amplifier unit comprises: a first differential pair, a first mirror circuit, and a first output stage circuit, for generating a first output signal and feeding it back to the first differential pair; the second operational amplifier unit comprises: a second differential pair, a second mirror circuit, and a second output stage circuit, for generating a second output signal and feeding it back to the second differential pair. Beneficial Effects: The operational amplifier provided by the present invention can support negative voltage input, and its output has high linearity performance. It converts a single-ended input signal that can be below ground into a differential output signal that meets the requirements of high input impedance and high precision, for use by subsequent circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of operational amplifiers, and in particular to an operational amplifier that supports negative voltage input, has high input impedance, and is high-precision. Background Art

[0002] An operational amplifier (op amp) is a circuit unit with a very high amplification factor. In practical circuits, it is often combined with a feedback network to form a functional module. It is an amplifier with special coupling circuits and feedback. Its output signal can be the result of mathematical operations such as addition, subtraction, differentiation, and integration of the input signal. Op amps can be implemented as discrete components or on semiconductor chips. With the advancement of semiconductor technology, most op amps exist in single-chip form. There are many types of op amps, which are widely used in the electronics industry. Unity-gain op amps used to provide drive must meet high input impedance and high precision (i.e., high linearity) for use in subsequent circuits.

[0003] Existing unity-gain operational amplifiers are implemented using PMOS input differential pairs. While meeting high input impedance and high-precision performance, they are limited by the output swing. Their output signal range needs to meet the requirements of gnd+vds-vdd-vds. The input swing and output swing of a typical unity-gain operational amplifier are the same, that is, the input range of the PMOS input differential pair must also meet the requirements of being greater than the gnd+vds voltage to ensure high-precision performance, where gnd represents the ground voltage; vds represents the minimum drain-source voltage of the output-stage MOS pull-up and pull-down transistors; and vdd represents the power supply voltage. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides an operational amplifier.

[0005] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0006] An operational amplifier, comprising:

[0007] The first operational amplifier unit is configured to receive an input signal and generate a first output signal, wherein the first operational amplifier unit includes:

[0008] a first differential pair, configured to receive the input signal and the first output signal;

[0009] A first mirror circuit, configured to mirror a reference current to the first common source terminal of the first differential pair at a first predetermined ratio;

[0010] A first output stage circuit is connected between a power supply terminal and a ground terminal, and includes a first input terminal and a second input terminal, each connected to the first differential pair; a first output terminal is used to generate the first output signal and feed it back to the first differential pair;

[0011] The second operational amplifier unit is configured to receive a ground signal and generate a second output signal, wherein the second operational amplifier unit includes:

[0012] a second differential pair, configured to receive the ground signal and the second output signal;

[0013] a second mirror circuit, configured to mirror the reference current to a second common source terminal of the second differential pair at a second predetermined ratio;

[0014] The second output stage circuit is connected between the power supply terminal and the ground terminal, and includes a third input terminal and a fourth input terminal, which are respectively connected to the second differential pair; and a second output terminal, which is used to generate the second output signal and feed it back to the second differential pair.

[0015] Preferably, it also includes:

[0016] A clamping circuit is connected between the second mirror circuit and the second common source terminal, wherein an input terminal of the clamping circuit is connected to the input signal and is used to clamp the current flowing through the second differential pair to be consistent with the current flowing through the first differential pair.

[0017] Preferably, the first differential pair includes:

[0018] a first transistor, wherein a gate of the first transistor is connected to the input signal, a source of the first transistor is connected to the first common source terminal via a first resistor, and a drain of the first transistor is connected to the first input terminal;

[0019] A second transistor, wherein the gate of the second transistor is connected to the first output signal, the source of the second transistor is connected to the first common source terminal, and the drain of the second transistor is connected to the second input terminal via a second resistor.

[0020] Preferably, the second differential pair includes:

[0021] a third transistor, wherein a gate of the third transistor is connected to the ground signal, a source of the third transistor is connected to the second common source terminal via a third resistor, and a drain of the third transistor is connected to the third input terminal;

[0022] a fourth transistor, wherein the gate of the fourth transistor is connected to the second output signal, the source of the fourth transistor is connected to the second common source terminal, and the drain of the fourth transistor is connected to the fourth input terminal via a fourth resistor.

[0023] Preferably, the resistance value of the second resistor is the same as the resistance value of the first resistor;

[0024] The resistance value of the fourth resistor is the same as the resistance value of the third resistor;

[0025] The first resistor and the third resistor have the same resistance value.

[0026] Preferably, a current source circuit is further included for generating the reference current, and the current source circuit includes:

[0027] a fifth transistor, wherein a gate of the fifth transistor is connected to a first node, and a source of the fifth transistor is connected to the power supply terminal;

[0028] A sixth transistor, wherein a gate of the sixth transistor is connected to a second node, a source of the sixth transistor is connected to the drain of the fifth transistor, and a drain of the sixth transistor is connected to a current source.

[0029] Preferably, the first mirror circuit includes:

[0030] a seventh transistor, wherein a gate of the seventh transistor is connected to the first node, and a source of the seventh transistor is connected to the power supply terminal;

[0031] an eighth transistor, wherein the gate of the eighth transistor is connected to the second node, the source of the eighth transistor is connected to the drain of the seventh transistor, and the drain of the eighth transistor is connected to the first common source terminal.

[0032] Preferably, the second mirror circuit includes:

[0033] a ninth transistor, wherein a gate of the ninth transistor is connected to the first node, and a source of the ninth transistor is connected to the power supply terminal;

[0034] a tenth transistor, wherein a gate of the tenth transistor is connected to the second node, and a source of the tenth transistor is connected to the drain of the ninth transistor.

[0035] Preferably, the clamping circuit comprises:

[0036] an eleventh transistor, wherein the gate of the eleventh transistor is connected to the input signal, the source of the eleventh transistor is connected to the drain of the tenth transistor, and the drain of the eleventh transistor is connected to the second common source terminal.

[0037] Preferably, the first predetermined ratio is the same as the second predetermined ratio.

[0038] The advantages or beneficial effects of the technical solution of the present invention are:

[0039] The operational amplifier provided by the present invention can support negative voltage input and has high linearity output performance. It converts a single-ended input signal that can be lower than the ground signal into a differential output signal that can meet the requirements of high input impedance and high precision for use by subsequent circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of an operational amplifier in a preferred embodiment of the present invention;

[0041] Figure 2-3 FIG. 1 is an equivalent schematic diagram of a specific embodiment of an operational amplifier in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0044] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0045] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, an operational amplifier is provided, which belongs to the technical field of operational amplifiers and is used to convert an input negative voltage signal into an output differential signal without distortion, such as Figure 1 As shown, the operational amplifier includes:

[0046] The first operational amplifier unit is configured to receive an input signal VIN and generate a first output signal. The first operational amplifier unit includes:

[0047] A first differential pair, configured to receive an input signal VIN and a first output signal VOUTP;

[0048] A first mirror circuit, configured to mirror a reference current to a first common source terminal of the first differential pair at a first predetermined ratio;

[0049] The first output stage circuit is connected between a power supply terminal VDD and a ground terminal, and includes a first input terminal and a second input terminal, each of which is connected to the first differential pair; the first output terminal is used to generate a first output signal VOUTP and feed it back to the first differential pair;

[0050] The second operational amplifier unit is configured to receive a ground signal GND and generate a second output signal VOUTN. The second operational amplifier unit includes:

[0051] A second differential pair, configured to receive a ground signal GND and a second output signal VOUTN;

[0052] A second mirror circuit, configured to mirror the reference current to a second common source terminal of the second differential pair at a second predetermined ratio;

[0053] The second output stage circuit is connected between the power supply terminal VDD and the ground terminal, and includes a third input terminal and a fourth input terminal respectively connected to the second differential pair; and a second output terminal for generating a second output signal VOUTN and feeding it back to the second differential pair.

[0054] As a preferred embodiment, the present invention further comprises:

[0055] The clamping circuit is connected between the second mirror circuit and the second common source terminal. The input terminal of the clamping circuit is connected to the input signal and is used to clamp the current flowing through the second differential pair to be consistent with the current flowing through the first differential pair.

[0056] As a preferred embodiment, the first differential pair includes:

[0057] a first transistor MPIN1, wherein a gate of the first transistor MPIN1 is connected to an input signal VIN, a source of the first transistor MPIN1 is connected to a first common source terminal via a first resistor R1, and a drain of the first transistor MPIN1 is connected to the first input terminal;

[0058] The second transistor MPIN2 has a gate connected to the first output signal VOUTP, a source connected to the first common source terminal, and a drain connected to the second input terminal via a second resistor R2.

[0059] As a preferred embodiment, the second differential pair includes:

[0060] a third transistor MPIN3, wherein a gate of the third transistor MPIN3 is connected to the ground signal GND, a source of the third transistor MPIN3 is connected to the second common source terminal via a third resistor R3, and a drain of the third transistor MPIN3 is connected to the third input terminal;

[0061] The fourth transistor MPIN4 has a gate connected to the second output signal VOUTN, a source connected to the second common source terminal, and a drain connected to the fourth input terminal via a fourth resistor R4.

[0062] As a preferred embodiment, the substrate-source of the first transistor MPIN1 is short-circuited. Similarly, the substrate-source of the second transistor MPIN2 , the third transistor MPIN3 , and the fourth transistor MPIN4 are also short-circuited.

[0063] Specifically, in this embodiment, the first transistor MPIN1 , the second transistor MPIN2 , the third transistor MPIN3 , and the fourth transistor MPIN4 need to be substrate-source shorted to prevent harmonics from being generated due to a voltage difference vsb between the transistor source and substrate varying with the input signal.

[0064] As a preferred embodiment, the resistance of the second resistor R2 is the same as the resistance of the first resistor R1;

[0065] The resistance of the fourth resistor R4 is the same as the resistance of the third resistor R3.

[0066] Specifically, in this embodiment, the first resistor R1 and the second resistor R2 are the same to ensure that the drain-source voltages of the first transistor MPIN1 and the second transistor MPIN2 are the same; similarly, the third resistor R3 and the fourth resistor R4 are the same to ensure that the drain-source voltages of the third transistor MPIN3 and the fourth transistor MPIN4 are the same.

[0067] As a preferred embodiment, the resistance values ​​of the first resistor R1 and the third resistor R3 are the same.

[0068] Specifically, in this embodiment, the first resistor R1 and the third resistor R3 have the same resistance, so as to better match the mirror current I1 flowing into the first differential pair and the mirror current I3 flowing into the second differential pair.

[0069] As a preferred embodiment, the present invention further includes a current source circuit for generating a reference current, and the current source circuit includes:

[0070] a fifth transistor MPB1 , wherein a gate of the fifth transistor MPB1 is connected to a first node, and a source of the fifth transistor MPB1 is connected to a power supply terminal;

[0071] The sixth transistor MPB2 has a gate connected to a second node, a source connected to the drain of the fifth transistor MPB1 , and a drain connected to a current source.

[0072] As a preferred embodiment, the first mirror circuit includes:

[0073] a seventh transistor MPB3, wherein a gate of the seventh transistor MPB3 is connected to the first node, and a source of the seventh transistor MPB3 is connected to the power supply terminal;

[0074] The eighth transistor MPB4 has a gate connected to the second node, a source connected to the drain of the seventh transistor MPB3, and a drain connected to the first common source terminal.

[0075] As a preferred embodiment, the second mirror circuit includes:

[0076] a ninth transistor MPB5, wherein a gate of the ninth transistor MPB5 is connected to the first node, and a source of the ninth transistor MPB5 is connected to the power supply terminal;

[0077] The tenth transistor MPB6 has a gate connected to the second node, and a source connected to the drain of the ninth transistor MPB5.

[0078] As a preferred embodiment, the clamping circuit includes:

[0079] The eleventh transistor MPB7 has a gate connected to the input signal, a source connected to the drain of the tenth transistor MPB6, and a drain connected to the second common source terminal.

[0080] Specifically, the drain voltage V d4 =V IN +V gs4 +V R1 ; Among them, V IN Represents the voltage of the input signal VIN; V gs4 represents the gate-source voltage of the eighth transistor MPB4; V R1 Represents the voltage across the first resistor R1; V d4 represents the drain voltage of the eighth transistor MPB4.

[0081] Even though the output impedance of the seventh transistor MPB3 is increased by the eighth transistor MPB4 , the mirror current I1 flowing through the seventh transistor MPB3 will still slightly change with the input signal VIN due to the channel modulation effect.

[0082] The drain voltage V d6 =V gs6 +V R3 , where V gs6 represents the gate-source voltage of the tenth transistor MPB6; V R3 Represents the voltage across the third resistor R3; V d6 represents the drain voltage of the tenth transistor MPB6.

[0083] That is, the drain voltage of the tenth transistor MPB6 is a fixed voltage, the mirror current I3 flowing through the ninth transistor MPB5 does not change with the input signal, and the mirror current I1 flowing through the seventh transistor MPB3 will change slightly with the input signal VIN, resulting in V R1 With V R3 The differences cannot be completely offset, so the linearity of the output differential signal deteriorates;

[0084] In the embodiment of the present invention, the eleventh transistor MPB7 is added for clamping, and the drain voltage of the tenth transistor MPB6 is V IN +V gs6 , the mirror current of the ninth transistor MPB5 will also have the same weak change with the input signal, that is, the mirror current flowing into the two differential pairs will be consistent and will also have the same weak change with the input signal, V R1 With V R3 Completely offset, ensuring the linearity of the output differential signal.

[0085] Alternatively, a resistor may be inserted into the clamp circuit so that the drain voltage of the tenth transistor MPB6 becomes V IN +V gs6 +V R3 , which is completely consistent with the drain voltage of the eighth transistor MPB4.

[0086] As a preferred embodiment, the first predetermined ratio is the same as the second predetermined ratio. Preferably, both the first predetermined ratio and the second predetermined ratio are 2, that is, the mirror current I1 flowing into the first differential pair and the mirror current I3 flowing into the second differential pair are twice the current source current.

[0087] As a preferred embodiment, the first transistor MPIN1 , the second transistor MPIN2 , the third transistor MPIN3 , the fourth transistor MPIN4 , and the eleventh transistor MPB7 have the same width-to-length ratio.

[0088] Furthermore, a plurality of the first transistor MPIN1 , the second transistor MPIN2 , the third transistor MPIN3 , and the fourth transistor MPIN4 may be provided, but the number of the provided transistors is the same.

[0089] A plurality of eleventh transistors MPB7 may be provided, and the number of the eleventh transistors MPB7 is twice the number of the third transistors MPIN3 .

[0090] As a preferred embodiment, the fifth transistor MPB1 , the sixth transistor MPB2 , the seventh transistor MPB3 , the eighth transistor MPB4 , the ninth transistor MPB5 , and the tenth transistor MPB6 have the same width-to-length ratio.

[0091] Furthermore, a plurality of the fifth transistor MPB1 and a plurality of the sixth transistor MPB2 can be provided respectively, but the provided numbers are the same.

[0092] Multiple seventh transistors MPB3, eighth transistors MPB4, ninth transistors MPB5, and tenth transistors MPB6 may be provided, but the number of the seventh transistors MPB3, eighth transistors MPB4, ninth transistors MPB5, and tenth transistors MPB6 is twice the number of the fifth transistor MPB1 or the sixth transistor MPB2.

[0093] Furthermore, the aspect ratio of the transistors in the differential pair is the same as or different from the aspect ratio of the transistors in the mirror circuit.

[0094] An embodiment of the present invention provides an operational amplifier capable of supporting negative input voltage, meeting high input impedance and high precision, for use in a subsequent circuit (ADC).

[0095] like Figure 2 and Figure 3 As shown, the operational amplifier converts the single-ended signal into a differential signal. The conversion process must meet high-precision characteristics, and due to input impedance requirements, the input signal needs to be connected to the gate of the differential pair tube.

[0096] To meet the requirements of high-precision performance, the first output signal VOUTP and the second output signal VOUTN of the operational amplifier input must be greater than the drain-source voltage Vds of the transistor; then the sum of the voltage of the input signal VIN and the voltage of the voltage source Va must be greater than the drain-source voltage Vds of the transistor, that is, VIN+Va>Vds, that is, Va>Vds-VIN; Va needs to be guaranteed not to change with VIN, and to be completely offset by differential subtraction.

[0097] like Figure 1 As shown, when VIN+I1*R1>Vds, I3*R3>Vds, the operational amplifier has a high linearity performance, that is, I1*R1>Vds-VIN. For example, assuming that the input signal needs to meet the input range of -0.2V-VDD-Vgs-Vds sine wave, that is, the transistor drain-source voltage Vds>0.05V, the input signal VIN=-0.2V, then I1*R1>0.25V;

[0098] At this point, the first output signal, VOUTP, equals VIN + I1*R1; the second output signal, VOUTN, equals I3*R3. The operational amplifier's gain is significantly greater than 1. Simply satisfying R1=R3 and I1=I3 suffices, resulting in VOUTP-VOUTN=VIN. This results in a differential signal with excellent linearity. The input terminal, connected to the transistor's gate, provides high input impedance.

[0099] The above technical solution has the following advantages or beneficial effects: the operational amplifier provided by the present invention can support negative voltage input, and the output differential voltage has high linearity performance, and can convert the single-ended input signal that can be lower than the ground signal into a differential output signal that can meet the requirements of high input impedance and high precision for use by the subsequent circuit.

[0100] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. An operational amplifier, characterized in that: include: The first operational amplifier unit is configured to receive an input signal and generate a first output signal, wherein the first operational amplifier unit includes: a first differential pair, configured to receive the input signal and the first output signal; A first mirror circuit, configured to mirror a reference current to the first common source terminal of the first differential pair at a first predetermined ratio; A first output stage circuit is connected between a power supply terminal and a ground terminal, and includes a first input terminal and a second input terminal, each connected to the first differential pair; a first output terminal is used to generate the first output signal and feed it back to the first differential pair; The second operational amplifier unit is configured to receive a ground signal and generate a second output signal, wherein the second operational amplifier unit includes: a second differential pair, configured to receive the ground signal and the second output signal; a second mirror circuit, configured to mirror the reference current to a second common source terminal of the second differential pair at a second predetermined ratio; The second output stage circuit is connected between the power supply terminal and the ground terminal, and includes a third input terminal and a fourth input terminal, which are respectively connected to the second differential pair; and a second output terminal, which is used to generate the second output signal and feed it back to the second differential pair.

2. The operational amplifier according to claim 1, wherein: Also includes: A clamping circuit is connected between the second mirror circuit and the second common source terminal, wherein an input terminal of the clamping circuit is connected to the input signal and is used to clamp the current flowing through the second differential pair to be consistent with the current flowing through the first differential pair.

3. The operational amplifier according to claim 1, wherein: The first differential pair includes: a first transistor, wherein a gate of the first transistor is connected to the input signal, a source of the first transistor is connected to the first common source terminal via a first resistor, and a drain of the first transistor is connected to the first input terminal; A second transistor, wherein the gate of the second transistor is connected to the first output signal, the source of the second transistor is connected to the first common source terminal, and the drain of the second transistor is connected to the second input terminal via a second resistor.

4. The operational amplifier according to claim 3, wherein: The second differential pair includes: a third transistor, wherein a gate of the third transistor is connected to the ground signal, a source of the third transistor is connected to the second common source terminal via a third resistor, and a drain of the third transistor is connected to the third input terminal; a fourth transistor, wherein the gate of the fourth transistor is connected to the second output signal, the source of the fourth transistor is connected to the second common source terminal, and the drain of the fourth transistor is connected to the fourth input terminal via a fourth resistor.

5. The operational amplifier according to claim 4, wherein: The resistance value of the second resistor is the same as the resistance value of the first resistor; The resistance value of the fourth resistor is the same as the resistance value of the third resistor; The first resistor and the third resistor have the same resistance value.

6. The operational amplifier according to claim 2, wherein: The invention also includes a current source circuit for generating the reference current, wherein the current source circuit includes: a fifth transistor, wherein a gate of the fifth transistor is connected to a first node, and a source of the fifth transistor is connected to the power supply terminal; A sixth transistor, wherein a gate of the sixth transistor is connected to a second node, a source of the sixth transistor is connected to the drain of the fifth transistor, and a drain of the sixth transistor is connected to a current source.

7. The operational amplifier according to claim 6, wherein: The first mirror circuit includes: a seventh transistor, wherein a gate of the seventh transistor is connected to the first node, and a source of the seventh transistor is connected to the power supply end; an eighth transistor, wherein the gate of the eighth transistor is connected to the second node, the source of the eighth transistor is connected to the drain of the seventh transistor, and the drain of the eighth transistor is connected to the first common source terminal.

8. The operational amplifier according to claim 6, wherein: The second mirror circuit includes: a ninth transistor, wherein a gate of the ninth transistor is connected to the first node, and a source of the ninth transistor is connected to the power supply end; A tenth transistor, wherein a gate of the tenth transistor is connected to the second node, and a source of the tenth transistor is connected to the drain of the ninth transistor.

9. The operational amplifier according to claim 8, wherein: The clamping circuit comprises: an eleventh transistor, wherein the gate of the eleventh transistor is connected to the input signal, the source of the eleventh transistor is connected to the drain of the tenth transistor, and the drain of the eleventh transistor is connected to the second common source terminal.

10. The operational amplifier according to claim 1, wherein: The first predetermined ratio is the same as the second predetermined ratio.

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