limiter circuit
By uniformly distributing the parasitic capacitance and turn-on power voltage of the limiter branch in the limiter circuit, and using N-type and P-type diode structure design, the problem of current imbalance in the limiter circuit is solved, and impedance matching and bandwidth performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-08
- Publication Date
- 2026-03-27
AI Technical Summary
In the existing technology, the off-chip limiter architecture requires an additional system impedance matching network, which leads to parasitic effects affecting the limiter bandwidth and insertion loss; although the on-chip integrated limiter architecture reduces the effect of parasitic capacitance, current imbalance leads to impedance matching and bandwidth limitations.
Design a limiter circuit that uses multiple transmission lines connected in series and uniformly distributed limiter branches, combined with a limiter bias circuit, to make the parasitic capacitance and turn-on power voltage of each branch uniform. The design uses N-type and P-type diode structures, and the number and size of the branches are adjusted to balance the current density.
It achieves current density balance in the limiter, improves impedance matching and bandwidth, and enhances power protection capability and insertion loss performance.
Smart Images
Figure CN115276580B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor technology, in particular to a limiter circuit. BACKGROUND
[0002] As a key module of the first stage of the receiving link of the radio frequency transceiver system, the low noise amplifier is usually damaged or burned by the high power blocking interference signal or the high power leakage signal of the transmitting link. Therefore, a limiter protection design is generally needed to limit the power of the signal entering the low noise amplifier to a safe receiving power. The design of the limiter of the low noise amplifier needs to have a strong power limiting protection capability, and cannot have a large impedance mismatch, insertion loss and noise contribution so as to avoid affecting the impedance matching, noise and gain, linearity and other intrinsic radio frequency performances of the low noise amplifier in the small signal receiving.
[0003] Referring to Figure 1 , the off-chip limiter architecture generally has a strong power protection capability, but usually needs to introduce an additional system impedance matching network, and the parasitic effect of the network will affect the bandwidth of the limiter and the degradation of the insertion loss and contribute to the noise.
[0004] Referring to Figure 2 and Figure 3 , the on-chip integrated limiter architecture incorporates the parasitic effect into the input impedance matching network of the on-chip low noise amplifier to utilize the wideband distribution effect of the transmission line to weaken the influence of the parasitic capacitance on the impedance matching and the bandwidth and the insertion loss, so as to improve the insertion loss and the impedance matching to a certain extent and improve the bandwidth. However, the impedance effect of the distributed transmission line will bring about the voltage distribution effect, which causes the uneven distribution of the current of different branches of the limiter, thereby limiting the improvement of the impedance matching and the bandwidth, the power protection capability and the insertion loss of the integrated limiter.
[0005] Therefore, a new type of on-chip integrated limiter and circuit design is needed to improve the bandwidth, the impedance matching and the insertion loss and improve the power protection capability of the limiter. SUMMARY
[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a limiter circuit to solve the problems that the off-chip limiter architecture of the prior art usually needs to introduce an additional system impedance matching network, and the parasitic effect of the network will affect the bandwidth of the limiter and the degradation of the insertion loss and contribute to the noise; and the on-chip integrated limiter architecture incorporates the parasitic effect into the input impedance matching network of the on-chip low noise amplifier to utilize the wideband distribution effect of the transmission line to weaken the influence of the parasitic capacitance on the impedance matching and the bandwidth and the insertion loss, but the impedance effect of the distributed transmission line will bring about the voltage distribution effect, which causes the uneven distribution of the current of different branches of the limiter, thereby limiting the improvement of the impedance matching and the bandwidth, the power protection capability and the insertion loss of the integrated limiter.
[0007] To achieve the above object and other related objects, the present application provides a limiter circuit, comprising:
[0008] a plurality of transmission lines connected in series, one end of the transmission line as the input end of the radio frequency signal, the other end of the transmission line connected with the input end of the amplifier, the output end of the amplifier as the output end of the radio frequency signal;
[0009] a limiter branch connected between the adjacent transmission line and the amplifier, the parasitic capacitance of each limiter branch is equal;
[0010] a limiter bias circuit electrically connected with each limiter branch, for making the opening power voltage of each limiter branch equal.
[0011] Preferably, the transmission line is the first to third transmission line.
[0012] Preferably, the limiter branch includes N-type diode, P-type diode, capacitor and resistor.
[0013] Preferably, from the input end to the output end, the series layering level ratio and the size ratio of the P-type and N-type diodes in each adjacent two limiter branches are the same.
[0014] Preferably, the number of P-type diodes and the number of N-type diodes are equal.
[0015] Preferably, the clipper bias circuit comprises: first to fourth three-terminal adjustable resistors, first and second two-terminal variable resistors, first and second NMOS, first and second PMOS, a fifteenth P-type diode and a sixteenth N-type diode; wherein a first fixed terminal of the first three-terminal adjustable resistor is connected to a power supply voltage VDD, a second fixed terminal thereof is connected to a drain of the first NMOS, and an active terminal thereof is connected to a gate of the first NMOS; a source of the first NMOS is connected to a positive electrode of the sixteenth N-type diode; a negative electrode of the sixteenth N-type diode is connected to a first fixed terminal of a third three-terminal adjustable resistor; a second fixed terminal of the third three-terminal adjustable resistor is connected to a drain of the second NMOS; an active terminal of the third three-terminal adjustable resistor is connected to a gate of the second NMOS; a source of the second NMOS is fixedly connected to one end of the first two-terminal variable resistor; and the other end of the first two-terminal variable resistor is grounded; a source of the first PMOS is connected to a power supply voltage VCC; a drain of the first PMOS is connected to a first fixed terminal of a second three-terminal adjustable resistor; a second fixed terminal of the second three-terminal adjustable resistor is connected to a negative electrode of the fifteenth P-type diode; an active terminal of the second three-terminal adjustable resistor is connected to a gate of the first PMOS; a positive electrode of the fifteenth P-type diode is connected to a source of the second PMOS; a drain of the second PMOS is connected to a first fixed terminal of a fourth three-terminal adjustable resistor; an active terminal of the fourth three-terminal adjustable resistor is connected to a gate of the second PMOS; a second fixed terminal of the fourth three-terminal adjustable resistor is connected to a first end of the second two-terminal variable resistor; and the other end of the second two-terminal variable resistor is grounded.
[0016] Preferably, the clipper branch comprises first to third clipper branches.
[0017] Preferably, the first clipper branch comprises first, third, fifth, seventh P-type diodes, first, second capacitors, second, fourth, sixth, eighth N-type diodes and first, second resistors; wherein the first, third, fifth, seventh P-type diodes are connected in series, the second, fourth, sixth, eighth N-type diodes are connected in series, the positive electrode of the first P-type diode is connected with the negative electrode of the second N-type diode and is connected between the first transmission line and the second transmission line, the negative electrode of the seventh P-type diode is connected with the first end of the first capacitor, the second end of the first capacitor is grounded, one end of the first resistor is connected with the negative electrode of the seventh P-type diode and the first end of the first capacitor, the other end of the first resistor is connected with the gate of the first PMOS and the movable terminal of the second three-terminal adjustable resistor, the positive electrode of the eighth N-type diode is connected with the first end of the second capacitor, the second end of the second capacitor is grounded, one end of the second resistor is connected with the positive electrode of the eighth N-type diode and the first end of the second capacitor, the other end of the second resistor is connected with the gate of the first NMOS and the movable terminal of the first three-terminal adjustable resistor.
[0018] Preferably, the second clipper branch comprises ninth, eleventh P-type diodes, third, fourth capacitors, tenth, twelfth N-type diodes and third, fourth resistors; wherein the ninth, eleventh P-type diodes are connected in series, the tenth, twelfth N-type diodes are connected in series, the positive electrode of the ninth P-type diode is connected with the negative electrode of the tenth N-type diode and is connected between the second transmission line and the third transmission line, the negative electrode of the eleventh P-type diode is connected with the first end of the third capacitor, the second end of the third capacitor is grounded, one end of the third resistor is connected with the negative electrode of the eleventh P-type diode and the first end of the third capacitor, the other end of the third resistor is connected with the source of the second PMOS and the positive electrode of the fifteenth P-type diode, the positive electrode of the twelfth N-type diode is connected with the first end of the fourth capacitor, the second end of the fourth capacitor is grounded, one end of the fourth resistor is connected with the positive electrode of the twelfth N-type diode and the first end of the fourth capacitor, the other end of the fourth resistor is connected with the negative electrode of the sixteenth N-type diode and the first end of the third three-terminal adjustable resistor.
[0019] Preferably, the third limiter branch comprises a thirteenth P-type diode, a fourteenth N-type diode, a fifth resistor, a sixth resistor and a fifth capacitor; wherein the positive electrode of the thirteenth P-type diode is connected with the negative electrode of the fourteenth N-type diode and between the third transmission line and the amplifier, the negative electrode of the thirteenth P-type diode is connected with the first end of the fifth capacitor, the second end of the fifth capacitor is grounded, one end of the fifth resistor is connected with the negative electrode of the thirteenth P-type diode and the first end of the fifth capacitor, the other end of the fifth resistor is connected with the second end of the fourth three-terminal adjustable resistor and the non-grounded end of the second two-terminal variable resistor; one end of the sixth resistor is connected with the positive electrode of the fourteenth N-type diode and the first end of the sixth capacitor, the second end of the sixth capacitor is grounded, the other end of the sixth resistor is connected with the source electrode of the second NMOS and the non-grounded end of the first two-terminal variable resistor.
[0020] As described above, the limiter circuit of the present application has the following beneficial effects:
[0021] The present application adjusts the size of each limiter branch according to the uneven distribution of current, so that the current density of each branch limiter is balanced. The forward and reverse design distribution of each branch uses N and P type diode limiter structure design to improve noise and linearity performance; according to the different adjustment size of the limiter branch, the corresponding branch order is adjusted, so that the parasitic capacitance of each branch is the same and is more evenly distributed, which improves the impedance matching and bandwidth influence problem, and improves the insertion loss; increasing the limiter bias circuit adjusts the limiter branch bias to improve the uneven current and the parasitic effect of the parasitic resistance on the current distribution and the turn-on voltage under the size of the order, further improving the current density and the balanced distribution, realizing the same turn-on power voltage of different branches, and improving the power limit protection ability; under the premise of realizing the balanced current density and improving the power protection ability, the insertion loss and impedance matching can be effectively improved, and the bandwidth is improved. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 A schematic diagram of an off-chip limiter architecture in the prior art is shown;
[0023] Figure 2 A schematic diagram of an on-chip integrated limiter architecture of the present prior art is shown;
[0024] Figure 3 A schematic diagram of the branch current distribution of the on-chip integrated limiter architecture of the prior art is shown;
[0025] Figure 4 A schematic diagram of the on-chip integrated limiter architecture of the present application is shown;
[0026] Figure 5 A schematic diagram of the on-chip integrated limiter bias circuit of the present application is shown;
[0027] Figure 6 The figure is an insertion loss and impedance simulation analysis schematic diagram of an embodiment of the application. DETAILED DESCRIPTION
[0028] The present application is described below by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. The present application can also be implemented or applied by different specific embodiments, and various modifications or changes can be made to the details in the specification without departing from the spirit of the present application.
[0029] Referring to Figure 4 The present application provides a limiter circuit, comprising:
[0030] A plurality of transmission lines connected in series, one end of the transmission line as the input end of the radio frequency signal, the other end of the transmission line connected with the input end of the amplifier LMA, and the output end of the amplifier LMA as the output end of the radio frequency signal;
[0031] In the embodiment of the present application, the transmission lines are the first to third transmission lines TL3.
[0032] The limiter branches connected between adjacent transmission lines and the amplifier LMA in sequence, the parasitic capacitance of each limiter branch is equal, that is, the size is adjusted according to the different limiter branches, and the corresponding branch order is adjusted, so that the parasitic capacitance of each branch is the same size and is more evenly distributed, the impedance matching and bandwidth influence problem is improved, and the insertion loss is improved.
[0033] In the embodiment of the present application, the limiter branch includes an N-type diode, a P-type diode, a capacitor and a resistor.
[0034] In the embodiment of the present application, from the input end to the output end, the series connection and size ratio of the P-type and N-type diodes in each adjacent two limiter branches are the same, specifically, the series connection and size ratio of the diodes in each limiter branch are the same, and the size of each diode is the same, so that the total size ratio of the P-type diodes in series connection and the N-type diodes in series connection in each adjacent two limiter branches is also the same, that is, the size of each limiter branch is adjusted according to the uneven distribution of current, so that the current density of each branch limiter is balanced. The forward and reverse design distribution of each branch is improved by using the N and P type diode limiter structure design to improve the noise and linearity performance.
[0035] In the embodiment of the present application, the number of P-type diodes is equal to the number of N-type diodes.
[0036] In the embodiment of the present application, the clipper branches include first to third clipper branches, and the size and series ratio of each different clipper branch voltage and current distribution effect is m:n:1, that is, the ratio of m:n and n:1 is equal.
[0037] It should be understood that the clipper branches include first to third clipper branches, and in actual design, there are more distribution branch proportion designs, and the parasitic effect zone adjusts the corresponding clipper bias output to achieve balanced current density, synchronous opening voltage, consistent parasitic capacitance, improved insertion loss and impedance matching.
[0038] The clipper bias circuit electrically connected with each clipper branch is used to make the opening power voltage of each clipper branch equal, and the clipper bias circuit adjusts the clipper branch bias to improve the parasitic influence of the parasitic resistance under the unbalanced current and series size on the current distribution and opening voltage, further improve the current density capability and balanced distribution, realize the same opening power voltage of different branches, and improve the power limit protection capability.
[0039] In the embodiment of the present application, please refer to Figure 5In the case that the clipper branch includes the first to third clipper branches, the clipper bias circuit includes: first to fourth three-terminal adjustable resistors, first and second two-terminal variable resistors, first and second NMOS, first and second PMOS, a fifteenth P-type diode PD1 and a sixteenth N-type diode ND1; wherein a first fixed terminal of the first three-terminal adjustable resistor RT1 is connected to a power supply voltage VDD, a second fixed terminal thereof is connected to a drain of the first NMOS MN1, and an active terminal thereof is connected to a gate of the first NMOS MN1; a source of the first NMOS MN1 is connected to an anode of the sixteenth N-type diode ND1; a cathode of the sixteenth N-type diode ND1 is connected to a first fixed terminal of the third three-terminal adjustable resistor RT3; a second fixed terminal of the third three-terminal adjustable resistor is connected to a drain of the second NMOS MN2; an active terminal of the third three-terminal adjustable resistor is connected to a gate of the second NMOS MN2; a source of the second NMOS MN2 is fixedly connected to one end of the first two-terminal variable resistor Rs1; and the other end of the first two-terminal variable resistor Rs1 is grounded; a source of the first PMOS MP1 is connected to a power supply voltage VCC; a drain of the first PMOS MP1 is connected to a first fixed terminal of the second three-terminal adjustable resistor RT2; a second fixed terminal of the second three-terminal adjustable resistor RT2 is connected to a cathode of the fifteenth P-type diode PD1; an active terminal of the second three-terminal adjustable resistor RT2 is connected to a gate of the first PMOS MP1; an anode of the fifteenth P-type diode PD1 is connected to a source of the second PMOS MP3; a drain of the second PMOS MP3 is connected to a first fixed terminal of the fourth three-terminal adjustable resistor RT4; an active terminal of the fourth three-terminal adjustable resistor RT4 is connected to a gate of the second PMOS MP3; a second fixed terminal of the fourth three-terminal adjustable resistor RT4 is connected to a first end of the second two-terminal variable resistor Rs2; and the other end of the second two-terminal variable resistor Rs2 is grounded.
[0040] In the embodiment of the present application, the first limiter branch includes first, third, fifth, seventh P-type diodes, first and second capacitors, second, fourth, sixth, eighth N-type diodes and first and second resistors; wherein the first, third, fifth, seventh P-type diodes are connected in series, i.e. the negative electrode of the first P-type diode Pdio1 is connected with the positive electrode of the third P-type diode Pdio3, the negative electrode of the third P-type diode Pdio3 is connected with the positive electrode of the fifth P-type diode Pdio5, the negative electrode of the fifth P-type diode Pdio5 is connected with the positive electrode of the seventh P-type diode Pdio7, the second, fourth, sixth, eighth N-type diodes are connected in series, i.e. the positive electrode of the second N-type diode Ndio2 is connected with the negative electrode of the fourth N-type diode Ndio4, the positive electrode of the fourth N-type diode Ndio4 is connected with the negative electrode of the sixth N-type diode Ndio6, the positive electrode of the sixth N-type diode Ndio6 is connected with the negative electrode of the eighth N-type diode Ndio8, the positive electrode of the first P-type diode Pdio1 is connected with the negative electrode of the second N-type diode Ndio2 and is connected between the first transmission line TL1 and the second transmission line TL2, the negative electrode of the seventh P-type diode Pdio7 is connected with the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, one end of the first resistor R1 is connected with the negative electrode of the seventh P-type diode Pdio7 and the first end of the first capacitor C1, the other end of the first resistor R1 is connected with the gate of the first PMOS MP1 and the movable end of the second three-terminal adjustable resistor RT2, the positive electrode of the eighth N-type diode Ndio8 is connected with the first end of the second capacitor C2, the second end of the second capacitor C2 is grounded, one end of the second resistor R2 is connected with the positive electrode of the eighth N-type diode Ndio8 and the first end of the second capacitor C2, the other end of the second resistor R2 is connected with the gate of the first NMOS MN1 and the movable end of the first three-terminal adjustable resistor RT1.
[0041] In the embodiment of the present application, the second limiter branch comprises a ninth P-type diode, an eleventh P-type diode, a third capacitor, a fourth capacitor, a tenth N-type diode, a twelfth N-type diode, and a third resistor and a fourth resistor; wherein the ninth P-type diode and the eleventh P-type diode are connected in series, the tenth N-type diode and the twelfth N-type diode are connected in series, the positive electrode of the ninth P-type diode Pdio9 is connected with the negative electrode of the tenth N-type diode Ndio10 and is connected between the second transmission line TL2 and the third transmission line TL3, the negative electrode of the eleventh P-type diode Pdio11 is connected with the first end of the third capacitor C3, the second end of the third capacitor C3 is grounded, one end of the third resistor R3 is connected with the negative electrode of the eleventh P-type diode Pdio11 and the first end of the third capacitor C3, the other end of the third resistor R3 is connected with the source electrode of the second PMOS MP3 and the positive electrode of the fifteenth P-type diode PD1, the positive electrode of the twelfth N-type diode Ndio12 is connected with the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is grounded, one end of the fourth resistor R4 is connected with the positive electrode of the twelfth N-type diode Ndio12 and the first end of the fourth capacitor C4, the other end of the fourth resistor R4 is connected with the negative electrode of the sixteenth N-type diode ND1 and the first end of the third three-terminal adjustable resistor RT3.
[0042] In the embodiment of the present application, the third limiter branch comprises a thirteenth P-type diode, a fourteenth N-type diode, a fifth resistor, a sixth resistor, a fifth capacitor and a sixth capacitor; wherein the positive electrode of the thirteenth P-type diode Pdio13 is connected with the negative electrode of the fourteenth N-type diode Ndio14 and is connected between the third transmission line TL3 and the amplifier LMA, the negative electrode of the thirteenth P-type diode Pdio13 is connected with the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is grounded, one end of the fifth resistor R5 is connected with the negative electrode of the thirteenth P-type diode Pdio13 and the first end of the fifth capacitor C5, the other end of the fifth resistor R5 is connected with the second end of the fourth three-terminal adjustable resistor RT4 and the non-ground end of the second two-terminal variable resistor Rs2; one end of the sixth resistor R6 is connected with the positive electrode of the fourteenth N-type diode Ndio14 and the first end of the sixth capacitor C6, the second end of the sixth capacitor C6 is grounded, the other end of the sixth resistor R6 is connected with the source electrode of the second NMOS MN2 and the non-ground end of the first two-terminal variable resistor Rs1.
[0043] In the embodiment of the present application, please refer to Figure 6 It can be known from the simulation that the embodiment of the present application can effectively improve the insertion loss and impedance matching and improve the bandwidth under the premise of realizing the current density balance and improving the power protection capability.
[0044] It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented. The shape, number and ratio of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complex.
[0045] In summary, the present application adjusts the size of each limiter branch according to the uneven distribution of current, so that the current density of each branch limiter is balanced. The positive and negative design distribution of each branch uses N and P type diode limiter structure design to improve noise and linearity performance; according to the different adjustment size of the limiter branch, the corresponding branch order is adjusted, so that the parasitic capacitance of each branch is the same and is more uniformly distributed, which improves the impedance matching and bandwidth influence problem, and improves the insertion loss; increasing the limiter bias circuit adjusts the limiter branch bias to improve the uneven current and the parasitic effect of the parasitic resistance on the current distribution and the opening voltage under the size of the order, further improve the current density and the balanced distribution, realize the same opening power voltage of different branches, improve the power limit protection ability; under the premise of realizing the balanced current density and improving the power protection ability, the insertion loss and impedance matching can be effectively improved, and the bandwidth is improved. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.
[0046] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.
Claims
1. A limiter circuit, characterized in that, include: Multiple transmission lines are connected in series. One end of the transmission line serves as the input terminal of the radio frequency signal, and the other end of the transmission line is connected to the input terminal of an amplifier. The output terminal of the amplifier serves as the output terminal of the radio frequency signal. A limiter branch is sequentially connected between adjacent transmission lines and the amplifier. The limiter branch includes an N-type diode, a P-type diode, a capacitor, and a resistor. The parasitic capacitance of each limiter branch is equal. A limiter bias circuit electrically connected to each of the limiter branches is used to ensure that the turn-on power voltage of each limiter branch is equal. The limiter bias circuit includes: first to fourth three-terminal adjustable resistors, first and second two-terminal variable resistors, first and second NMOS transistors, first and second PMOS transistors, a fifteenth P-type diode, and a sixteenth N-type diode; wherein, the first fixed terminal of the first three-terminal adjustable resistor is connected to the power supply voltage VDD, its second fixed terminal is connected to the drain of the first NMOS transistor, its movable terminal is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the anode of the sixteenth N-type diode, the cathode of the sixteenth N-type diode is connected to the first fixed terminal of the third three-terminal adjustable resistor, the second fixed terminal of the third three-terminal adjustable resistor is connected to the drain of the second NMOS transistor, the movable terminal of the third three-terminal adjustable resistor is connected to the gate of the second NMOS transistor, and the source of the second NMOS transistor is connected to the first two-terminal variable resistor. One end of the device is fixedly connected, and the other end of the first two-terminal variable resistor is grounded; the source of the first PMOS is connected to the power supply voltage VCC, the drain of the first PMOS is connected to the first fixed end of the second three-terminal adjustable resistor, the second fixed end of the second three-terminal adjustable resistor is connected to the negative terminal of the fifteenth P-type diode, the movable end of the second three-terminal adjustable resistor is connected to the gate of the first PMOS, the positive terminal of the fifteenth P-type diode is connected to the source of the second PMOS, the drain of the second PMOS is connected to the first fixed end of the fourth three-terminal adjustable resistor, the movable end of the fourth three-terminal adjustable resistor is connected to the gate of the second PMOS, the second fixed end of the fourth three-terminal adjustable resistor is connected to the first end of the second two-terminal variable resistor, and the other end of the second two-terminal variable resistor is grounded.
2. The limiter circuit according to claim 1, characterized in that: The transmission lines are the first to the third transmission lines.
3. The limiter circuit according to claim 1, characterized in that: In the direction from the input terminal to the output terminal, the ratio of the number of series stacked P-type and N-type diodes in each of the two adjacent limiter branches is the same as the ratio of their size.
4. The limiter circuit according to claim 3, characterized in that: The number of P-type diodes is equal to the number of N-type diodes.
5. The limiter circuit according to claim 2, characterized in that: The limiter branch includes the first to third limiter branches.
6. The limiter circuit according to claim 5, characterized in that: The first limiter branch includes first, third, fifth, and seventh P-type diodes, first and second capacitors, second, fourth, sixth, and eighth N-type diodes, and first and second resistors. The first, third, fifth, and seventh P-type diodes are connected in series, as are the second, fourth, sixth, and eighth N-type diodes. The anode of the first P-type diode is connected to the cathode of the second N-type diode and is connected between the first transmission line and the second transmission line. The cathode of the seventh P-type diode is connected to the first terminal of the first capacitor, and the second terminal of the first capacitor is grounded. One end of the first resistor is connected to the cathode of the seventh P-type diode and the first terminal of the first capacitor, and the other end of the first resistor is connected to the gate of the first PMOS and the movable terminal of the second three-terminal adjustable resistor. The anode of the eighth N-type diode is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded. One end of the second resistor is connected to the anode of the eighth N-type diode and the first terminal of the second capacitor, and the other end of the second resistor is connected to the gate of the first NMOS and the movable terminal of the first three-terminal adjustable resistor.
7. The limiter circuit according to claim 5, characterized in that: The second limiter branch includes ninth and eleventh P-type diodes, third and fourth capacitors, tenth and twelfth N-type diodes, and third and fourth resistors; wherein the ninth and eleventh P-type diodes are connected in series, the tenth and twelfth N-type diodes are connected in series, the anode of the ninth P-type diode is connected to the cathode of the tenth N-type diode and connected between the second transmission line and the third transmission line, the cathode of the eleventh P-type diode is connected to the first terminal of the third capacitor, the second terminal of the third capacitor is grounded, one end of the third resistor is connected to the cathode of the eleventh P-type diode and the first terminal of the third capacitor, the other end of the third resistor is connected to the source of the second PMOS and the anode of the fifteenth P-type diode, the anode of the twelfth N-type diode is connected to the first terminal of the fourth capacitor, the second terminal of the fourth capacitor is grounded, one end of the fourth resistor is connected to the anode of the twelfth N-type diode and the first terminal of the fourth capacitor, the other end of the fourth resistor is connected to the cathode of the sixteenth N-type diode and the first terminal of the third three-terminal adjustable resistor.
8. The limiter circuit according to claim 5, characterized in that: The third limiter branch includes a thirteenth P-type diode, a fourteenth N-type diode, fifth and sixth resistors, and fifth and sixth capacitors. The anode of the thirteenth P-type diode is connected to the cathode of the fourteenth N-type diode and is connected between the third transmission line and the amplifier. The cathode of the thirteenth P-type diode is connected to the first terminal of the fifth capacitor, and the second terminal of the fifth capacitor is grounded. One end of the fifth resistor is connected to the cathode of the thirteenth P-type diode and the first terminal of the fifth capacitor, and the other end of the fifth resistor is connected to the second terminal of the fourth three-terminal adjustable resistor and the non-grounded terminal of the second two-terminal variable resistor. One end of the sixth resistor is connected to the anode of the fourteenth N-type diode and the first terminal of the sixth capacitor, and the second terminal of the sixth capacitor is grounded. The other end of the sixth resistor is connected to the source of the second NMOS and the non-grounded terminal of the first two-terminal variable resistor.
Citation Information
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