Scan structure D flip-flop with soft error self-repair function

Abstract

The application provides a scan structure D flip-flop with a soft error self-repairing function. The scan structure D flip-flop comprises sequentially connected data input buffer circuit, scan control circuit, main latch, main latch error detection circuit, main latch error correction circuit, slave latch, slave latch error detection circuit, slave latch error correction circuit and output circuit, further comprises clock circuit connected with the main latch and the slave latch respectively, the main latch is connected with the main latch error correction circuit, and the slave latch is connected with the slave latch error correction circuit. When the data input signal D or the clock signal CK is affected by a single event transient, and glitches or glitches are generated on the data input signal and the clock signal, the structure in the data input buffer circuit and the clock circuit is connected through a delay unit and a Miller C unit, so that the single event transient is inhibited.

Description

Technical Field

[0001] This invention belongs to the field of triggers and relates to a master-slave D trigger with a scanning structure. In particular, a scanning structure D trigger with soft error self-repair function is designed. Background Technology

[0002] With the continuous reduction in feature size and operating voltage of semiconductor devices, device and circuit failures caused by soft errors have become a primary problem for the safe and reliable operation of space electronic systems. Neutrons from cosmic rays or alpha particles from circuit packaging and bonding materials can induce soft errors in electronic systems. These particles interact with atoms in the device materials, releasing a large number of electron-hole pairs, causing changes in the device node potential, ultimately leading to Single Event Upset (SEU) and Single Event Transient (SET). Typically, the main method for suppressing SEU is to use a Triple Modular Redundancy (TMR) structure, which copies the circuit to be protected three times and then uses a voter to output the correct logic state. However, this method consumes 200% more area and power, making it costly. While using Dual Interlocked Storage Cells (DICE) can suppress SEU, its effect on suppressing SET is not ideal. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by proposing a scan structure D flip-flop with self-healing function that resists single-event upsets and single-event transients, thus solving the reliability problem of scan type D flip-flops resisting both single-event upsets and single-event transients. The present invention can be applied to high-reliability circuit chips.

[0004] The technical solution adopted by the present invention to achieve the above objectives is as follows:

[0005] A scan-structure D flip-flop with soft error self-correction function includes a data input buffer circuit, a scan control circuit, a master latch, a master latch error detection circuit, a master latch error correction circuit, a slave latch, a slave latch error detection circuit, a slave latch error correction circuit, and an output circuit, all connected in sequence. It also includes a clock circuit connected to the master latch and the slave latch respectively. The master latch is connected to the master latch error correction circuit, and the slave latch is connected to the slave latch error correction circuit.

[0006] The clock circuit includes: the input terminal of the inverting MOS unit M1 is connected to the gate of PMOS transistor P5 and the gate of NMOS transistor N6, respectively, serving as the clock signal input terminal of the clock circuit; the output terminal of the inverting MOS unit M4 is connected to the gate of PMOS transistor P6 and the gate of NMOS transistor N5, respectively; the inverting MOS units M1 to M4 are connected in series; the source of PMOS transistor P5 is connected to the power supply VDD; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the drain of PMOS transistor P6 is connected to the input terminal of the inverting MOS unit M5 and the drain of NMOS transistor N5, respectively. The source of S-MOSFET N5 is connected to the drain of NMOS transistor N6, the source of NMOS transistor N6 is grounded, the source of PMOS transistor P7 is grounded, the gate of PMOS transistor P7 is connected to the gate of NMOS transistor N7, the gate of NMOS transistor N8, and the output of the inverting MOS unit M5, serving as the positive clock output of the clock circuit. The drain of PMOS transistor P7 is connected to the drain of NMOS transistor N7 and the input of the inverting MOS unit M5, serving as the inverting clock output of the clock circuit. The source of NMOS transistor N7 is connected to the drain of NMOS transistor N8, and the source of NMOS transistor N8 is grounded.

[0007] The data input buffer circuit consists of eight sets of series-connected inverted MOS units M6 to M13. The input terminal of the inverted MOS unit M6 serves as the input terminal of the data input buffer circuit, and the output terminal of the inverted MOS unit M13 serves as the output terminal of the data input buffer circuit.

[0008] The scan control circuit includes: the input terminal of the inverting MOS unit M14 is connected to the gate of PMOS transistor P18 and the gate of NMOS transistor N21, respectively, serving as the scan input selection terminal of the scan control circuit; the output terminal of the inverting MOS unit M14 is connected to the gate of PMOS transistor P21 and the gate of NMOS transistor N20, respectively; the source of PMOS transistor P18 is connected to the power supply VDD; the drain of PMOS transistor P18 is connected to the source of PMOS transistor P19; the drain of PMOS transistor P19 is connected to the drain of NMOS transistor N19, the drain of PMOS transistor P21, and the input terminal of the inverting MOS unit M15, respectively; the source of NMOS transistor N19 is connected to the drain of NMOS transistor N20; and the NMOS transistor N20... The source of S-MOSFET N20 is grounded. The gate of PMOS transistor P19 is connected to the gate of NMOS transistor N19, serving as the input terminal of the scan control circuit and the output terminal of the data input buffer circuit. The source of PMOS transistor P20 is connected to the power supply VDD. The drain of PMOS transistor P20 is connected to the source of PMOS transistor P21. The drain of PMOS transistor P21 is connected to the drain of NMOS transistor N21. The source of NMOS transistor N21 is connected to the drain of NMOS transistor N22. The source of NMOS transistor N22 is grounded. The gate of PMOS transistor P20 is connected to the gate of NMOS transistor N22, serving as the scan input data terminal of the scan control circuit. The output terminal of the inverting MOS unit M15 serves as the signal output terminal of the scan control circuit.

[0009] The master latch and slave latch have the same structure. The master latch includes: the source of PMOS transistor P23 is connected to power supply VDD; the drain of PMOS transistor P23 is connected to the source of PMOS transistor P23; the drain of PMOS transistor P24 is connected to the drain of NMOS transistor N24, the input terminal of the inverting MOS unit M16, and the drain of PMOS transistor P27; the source of NMOS transistor N24 is connected to the drain of NMOS transistor N25; the source of NMOS transistor N25 is grounded; the gate of PMOS transistor P23 is connected to the gate of NMOS transistor N25, serving as the signal input terminal of the master latch and connected to the signal output terminal of the scan control circuit; the gate of PMOS transistor P24 serves as the positive clock signal input terminal of the master latch and is connected to the positive clock output terminal of the clock circuit; the gate of NMOS transistor N24 serves as the negative clock signal input terminal of the master latch and is connected to the negative clock output terminal of the clock circuit. The clock output is connected. The source of PMOS transistor P26 is connected to the power supply VDD. The drain of PMOS transistor P26 is connected to the source of PMOS transistor P27. The drain of PMOS transistor P27 is connected to the drain of NMOS transistor N27. The source of NMOS transistor N27 is connected to the drain of NMOS transistor N28. The source of NMOS transistor N28 is grounded. The gate of PMOS transistor P26 is connected to the gate of NMOS transistor N25 and the output of the inverting MOS unit M16. The gate of PMOS transistor P27 serves as the inverted clock signal input of the main latch and is connected to the inverted clock output of the clock circuit. The gate of NMOS transistor N27 serves as the positive clock signal input of the main latch and is connected to the positive clock output of the clock circuit. The input of the inverting MOS unit M16 serves as the first output of the main latch, and the output of the inverting MOS unit M16 serves as the second output of the main latch.

[0010] The master latch error detection circuit and the slave latch error detection circuit have the same structure. The master latch error detection circuit includes: the input terminal of the inverting MOS unit M17 serves as the first input terminal of the master latch error detection circuit and is connected to the first output terminal of the master latch; the output terminal of the inverting MOS unit M17 is connected to the gate of PMOS transistor P30, the gate of NMOS transistor N32, the source of PMOS transistor P33, and the source of NMOS transistor N33, respectively; the input terminal of the inverting MOS unit M18 serves as the second input terminal of the master latch error detection circuit and is connected to the second output terminal of the master latch, the gate of NMOS transistor N31, and the gate of PMOS transistor P32, respectively; the output terminal of the inverting MOS unit M18 is connected to the gate of PMOS transistor P31 and the gate of NMOS transistor N33, respectively. The source of PMOS transistor P30 is connected to power supply VDD. The drain of PMOS transistor P30 is connected to the source of PMOS transistor P31. The drain of PMOS transistor P31 is connected to the drain of NMOS transistor N31. The source of NMOS transistor N31 is connected to the drain of NMOS transistor N32. The source of NMOS transistor N32 is grounded. The gate of PMOS transistor P30 is connected to the gate of NMOS transistor N32. The drain of PMOS transistor P32 is connected to the drain of PMOS transistor P31, the drain of NMOS transistor N33, and the input of the inverting MOS unit M19. The output of the inverting MOS unit M19 serves as the first output of the main latch error detection circuit and is connected to the input of the inverting MOS unit M20. The output of the inverting MOS unit M20 serves as the second output of the main latch error detection circuit.

[0011] The master latch error correction circuit and the slave latch error correction circuit have the same structure. The master latch error correction circuit includes: one end of resistor R1 is connected to the second output terminal of the master latch, the drain of PMOS transistor P35, and the drain of NMOS transistor N36, respectively; one end of resistor R1 serves as the output terminal of the master latch error correction circuit, and is connected to the source of PMOS transistor P35, the source of NMOS transistor N36, the drain of PMOS transistor P36, and the drain of NMOS transistor N37, respectively. The source of transistor 36 is connected to the source of NMOS transistor N37, the gate of PMOS transistor P37, and the gate of NMOS transistor N38, respectively. The gates of NMOS transistor N36 and PMOS transistor P36 are both connected to the first output terminal of the main latch error detection circuit. The gates of PMOS transistor P35 and NMOS transistor N37 are both connected to the second output terminal of the main latch error detection circuit. The source and drain of PMOS transistor P37 are both connected to the power supply VDD, and the source and drain of NMOS transistor N38 are both grounded.

[0012] The output circuit includes: the input terminal of the inverting MOS unit M22 serves as the input terminal of the output circuit, and is connected to the input terminal of the inverting MOS unit M25 and the output terminal of the latch error correction circuit, respectively; the output terminal of the inverting MOS unit M22 is connected to the input terminal of the inverting MOS unit M23; the output terminal of the inverting MOS unit M23 is connected to the input terminal of the inverting MOS unit M24; the output terminal of the inverting MOS unit M24 serves as the inverted signal output terminal of the output circuit; the output terminal of the inverting MOS unit M25 is connected to the output terminal of the inverting MOS unit M26; and the output terminal of the inverting MOS unit M26 serves as the signal output terminal of the output circuit.

[0013] The reverse MOS unit includes a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected as the input terminal of the reverse MOS unit, and the drains of the PMOS transistor and the NMOS transistor are connected as the output terminal of the reverse MOS unit. The source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is grounded.

[0014] The present invention has the following beneficial effects and advantages:

[0015] 1. The present invention provides a scanning structure D flip-flop with self-healing function to resist single-event upsets and single-event transients. When the data input signal D or the clock signal CK is affected by a single-event transient, resulting in glitches or ripples on the data input signal and the clock signal, the structure in the data input buffer circuit and the clock circuit achieves suppression of the single-event transient through the connection of the delay unit and the Miller C unit.

[0016] 2. The present invention provides a scan structure D flip-flop with self-healing function to resist single-event upsets and single-event transients. When a single-event upset occurs at the sensitive node of the master latch or slave latch inside the D flip-flop, the error detection circuit of the master latch and the error detection circuit of the slave latch will detect the occurrence of the logic flip phenomenon, and then activate the error correction circuit of the master latch and the error correction circuit of the slave latch to alleviate and release the circuit deposition generated at the sensitive node, thereby ensuring the stability of the output signal. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall logical structure of the present invention;

[0018] Figure 2 This is a schematic diagram of the clock circuit in this invention;

[0019] Figure 3 This is a schematic diagram of the data input buffer circuit in this invention;

[0020] Figure 4 This is a schematic diagram of the scanning control circuit in this invention;

[0021] Figure 5 This is a schematic diagram of the main latch circuit in this invention;

[0022] Figure 6 This is a schematic diagram of the main latch error detection circuit in this invention;

[0023] Figure 7 This is a schematic diagram of the main latch error correction circuit in this invention;

[0024] Figure 8 This is a schematic diagram of the latch circuit in this invention;

[0025] Figure 9 This is a schematic diagram of the latch error detection circuit in this invention;

[0026] Figure 10 This is a schematic diagram of the latch error correction circuit in this invention;

[0027] Figure 11 This is a schematic diagram of the output circuit in this invention;

[0028] Figure 12 A schematic diagram of the SEU fault injection simulation results for a general-type scan structure D flip-flop without error detection and error correction circuitry;

[0029] Figure 13 This is a schematic diagram of the simulation results of SEU fault injection in this invention;

[0030] Figure 14 A schematic diagram of simulation results for injecting a fault into the data terminal SET of a general-type scan-structure D flip-flop;

[0031] Figure 15 This is a schematic diagram of the simulation results for the data terminal SET fault injection of the present invention;

[0032] Figure 16 A schematic diagram of the simulation results for injecting a fault SET at the clock terminal of a general-type scan structure D flip-flop;

[0033] Figure 17 This is a schematic diagram of the simulation results for the clock terminal SET fault injection of the present invention. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0035] Figure 1 This is a schematic diagram of the overall logic structure of the scan-structure D flip-flop with soft error self-correction function of the present invention. The present invention consists of a clock circuit (such as...). Figure 2 As shown), data input buffer circuit (such as...) Figure 3 (as shown), scanning control circuit (such as) Figure 4As shown), the main latch circuit (such as...) Figure 5 (as shown), main latch error detection circuit (such as) Figure 6 As shown), the main latch error correction circuit (such as...) Figure 7 As shown), from the latch circuit (such as Figure 8 As shown), from the latch error detection circuit (such as...) Figure 9 As shown), from the latch error correction circuit (such as...) Figure 10 As shown), output circuit (such as) Figure 11 (As shown)

[0036] This invention discloses a scan-structured D flip-flop with self-healing capabilities, resistant to single-event upsets and single-event transients. It has four inputs and one output. The four inputs are a clock signal input (CK), a data signal input (D), a scan input selection input (SEL), and a scan input data input (TD). The outputs are Q and QN. The clock circuit receives CK, buffers the CK signal, and outputs CN and C. The data input buffer circuit receives the data signal D, buffers D, and outputs DS. The scan control circuit receives the DS signal, the scan input selection signal SEL, and the scan input data signal TD. When SEL is high, the scan input data signal is valid; when SEL is low, the buffered data input signal DS is valid. The master latch receives the valid signal S from the scan control circuit and sends it into its internal storage. When a single-event flip occurs in an internal storage node, the master latch error detection circuit detects that the logic levels of nodes MN1 and MN2 are the same and sends error detection signals MD1 and MD2 to the master latch error correction circuit. The master latch error correction circuit releases the charge pulse of the flipped node through low-pass filtering, thereby restoring the circuit's logic level. The slave latch receives the output signal MC from the master latch error correction circuit and sends it into its internal storage. When a single-event flip occurs in a storage node of the slave latch, the slave latch error detection circuit detects that the logic levels of nodes SN1 and SN2 are the same and sends error detection signals SD1 and SD2 to the slave latch error correction circuit. The slave latch error correction circuit releases the charge pulse of the flipped node through low-pass filtering, restoring the circuit's logic level. The output circuit receives the output signal SC from the slave latch error correction circuit, buffers it, and outputs Q and QN.

[0037] like Figure 2As shown, the clock circuit has one input terminal and two output terminals. The input terminal is the clock signal input terminal CK, and the two output terminals are CN and C, respectively. The clock circuit includes eight PMOS transistors and nine NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg1 of the first PMOS transistor is connected to CK, the drain Pd1 is connected to the drain Nd1 of the first NMOS transistor, and the source Ps1 is connected to the power supply VDD. The gate Pg2 of the second PMOS transistor is connected to the drain Pd1 of the first PMOS transistor, the drain Nd1 of the first NMOS transistor, and the gate Ng2 of the second NMOS transistor. The third PMOS transistor's gate Ps2 is connected to the power supply VDD; the third PMOS transistor's gate Pg3 is connected to the drain Pd1 of the second PMOS transistor, the drain Nd1 of the second NMOS transistor, and the gate Ng3 of the third NMOS transistor, with its source Ps3 connected to the power supply VDD; the fourth PMOS transistor's gate Pg4 is connected to the drain Pd3 of the third PMOS transistor, the drain Nd3 of the third NMOS transistor, and the gate Ng4 of the fourth NMOS transistor, with its source Ps4 connected to the power supply VDD; the fifth PMOS transistor's gate Pg5 is connected to the input clock signal CK and the gate Ng6 of the sixth NMOS transistor, with its drain Pd5 connected to the source Ps6 of the sixth PMOS transistor. Ps5 is connected to the power supply VDD; the gate Pg6 of the sixth PMOS transistor is connected to the drain Pd4 of the fourth PMOS transistor, the drain Nd4 of the fourth NMOS transistor, and the drain Nd5 of the fifth NMOS transistor; the drain Pd6 of the sixth PMOS transistor is connected to the drain Nd5 of the fifth NMOS transistor; the source of the sixth PMOS transistor is connected to the drain Pd5 of the fifth PMOS transistor; the gate Pg7 of the seventh PMOS transistor is connected to the gate Ng7 of the seventh NMOS transistor, the gate Ng8 of the eighth NMOS transistor, and the output terminal C of the clock circuit; the drain Pd7 of the seventh PMOS transistor is connected to the drain Nd7 of the seventh NMOS transistor and the gate Pg8 of the eighth PMOS transistor. The gate Ng9 of the ninth NMOS transistor and the output terminal CN of the clock circuit are connected to the power supply VDD; the source of the seventh PMOS transistor is connected to the power supply VDD; the gate Pg8 of the eighth PMOS transistor is connected to the drain Pd7 of the seventh PMOS transistor, the drain Nd7 of the seventh NMOS transistor, and the gate Ng9 of the ninth NMOS transistor; the drain of the eighth PMOS transistor is connected to the drain Nd9 of the ninth NMOS transistor; the source of the eighth PMOS transistor is connected to the power supply VDD; the gate Ng1 of the first NMOS transistor is connected to the gate Pg1 of the first PMOS transistor; the drain Nd1 of the first NMOS transistor is connected to the drain Pd1 of the first PMOS transistor; the source of the first NMOS transistor is connected to ground VSS.The gate of the second NMOS transistor is connected to the drain Pd1 of the first PMOS transistor, the drain Nd1 of the first NMOS transistor, and the gate Ng2 of the second NMOS transistor. The drain of the second NMOS transistor is connected to the drain Pd2 of the second PMOS transistor, the gate Pg3 of the third PMOS transistor, and the gate Ng3 of the third NMOS transistor. The source of the second NMOS transistor is connected to ground VSS. The gate Ng3 of the third NMOS transistor is connected to the drain Pd2 of the second PMOS transistor, the drain Nd2 of the second NMOS transistor, and the gate Pg3 of the third PMOS transistor. The drain Nd3 of the third NMOS transistor is connected to the drain Pd3 of the third PMOS transistor, the gate Pg4 of the fourth PMOS transistor, and the gate Ng4 of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to ground VSS; the gate Ng4 of the fourth NMOS transistor is connected to the drain Pd3 of the third PMOS transistor, the drain Nd3 of the third NMOS transistor, and the gate Pg4 of the fourth PMOS transistor. The drain of the fourth NMOS transistor is connected to the logic Pd4 of the fourth PMOS transistor, the gate Pg6 of the sixth PMOS transistor, and the gate Ng5 of the fifth NMOS transistor. The source of the fourth NMOS transistor is connected to ground VSS; the gate Ng5 of the fifth NMOS transistor is connected to the gate Pg6 of the sixth PMOS transistor, the drain Pd4 of the fourth PMOS transistor, and the drain Nd4 of the fourth NMOS transistor. The drain Nd5 of the fifth NMOS transistor is connected to the drain Pd6 of the sixth PMOS transistor, the drain Pd7 of the seventh PMOS transistor, and the drain of the seventh NMOS transistor. The gates of Nd7, Pg8, and Ng9 of the eighth and ninth NMOS transistors are connected. The source Ns5 of the fifth NMOS transistor is connected to the drain Nd6 of the sixth NMOS transistor. The gate Ng6 of the sixth NMOS transistor is connected to the gate Pg5 of the fifth PMOS transistor and the input clock CK. The drain Nd6 of the sixth NMOS transistor is connected to the source Ns5 of the fifth NMOS transistor. The source Ns6 of the sixth NMOS transistor is connected to ground VSS. The gate Ng7 of the seventh NMOS transistor is connected to the gate Pg7 of the seventh PMOS transistor and the gate Ng8 of the eighth NMOS transistor. The drain Nd7 of the seventh NMOS transistor is connected to the drain Pd7 of the seventh PMOS transistor, the drain Pd6 of the sixth PMOS transistor, and the drain Nd5 of the fifth NMOS transistor. The gate of the eighth PMOS transistor (Pg8) and the gate of the ninth NMOS transistor (Ng9) are connected. The source of the seventh NMOS transistor (Ns7) is connected to the drain of the eighth NMOS transistor (Nd8). The gate of the eighth NMOS transistor (Ng8) is connected to the gate of the seventh NMOS transistor (Ng7) and the gate of the seventh PMOS transistor (Pg7). The drain of the eighth NMOS transistor (Nd8) is connected to the source of the seventh NMOS transistor (Ns7), and the source of the eighth NMOS transistor (Ns8) is connected to ground (VSS). The gate of the ninth NMOS transistor (Ng9) is connected to the drain of the seventh PMOS transistor (Pd7), the drain of the sixth PMOS transistor (Pd6), and the drain of the fifth NMOS transistor (Nd5). The drain of the ninth NMOS transistor (Nd9) is connected to the drain of the eighth PMOS transistor (Pd8) and the output signal C of the clock circuit.

[0038] like Figure 3As shown, the data input buffer circuit has one input terminal and one output terminal. One input terminal is connected to the input data signal D, and the other output terminal DS is connected to the scan control circuit. The data input buffer circuit includes eight PMOS transistors and eight NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg9 of the ninth PMOS transistor is connected to the gate Ng10 of the tenth NMOS transistor and the input signal D. The drain Pd9 of the ninth PMOS transistor is connected to the drain Nd10 of the tenth NMOS transistor, and the source Ps9 of the ninth PMOS transistor is connected to the power supply VDD. The gate Pg10 of the tenth PMOS transistor is connected to the gate Ng11 of the eleventh NMOS transistor and the ninth PMOS transistor. The drain of the PMOS transistor Pd9 and the drain of the tenth NMOS transistor Nd10 are connected. The drain of the tenth PMOS transistor Pd10 is connected to the drain of the eleventh NMOS transistor Nd11, the gate of the eleventh PMOS transistor Pg11, and the gate of the twelfth NMOS transistor Ng12. The source of the tenth PMOS transistor Ps10 is connected to the power supply VDD. The gate of the eleventh PMOS transistor Pg11 is connected to the gate of the twelfth NMOS transistor Ng12, the drain of the tenth PMOS transistor Pd10, and the drain of the eleventh NMOS transistor Nd11. The drain of the eleventh PMOS transistor Pd11 is connected to the drain of the twelfth NMOS transistor Nd12, the gate of the twelfth PMOS transistor Pg12, and the gate of the thirteenth NMOS transistor Ng13. The source Ps11 of the eleventh PMOS transistor is connected to the power supply VDD; the gate Pg12 of the twelfth PMOS transistor is connected to the gate Ng13 of the thirteenth NMOS transistor, the drain Pd11 of the eleventh PMOS transistor, and the drain Nd12 of the twelfth NMOS transistor; the drain Pd12 of the twelfth PMOS transistor is connected to the drain Nd13 of the thirteenth NMOS transistor, the gate Pg13 of the thirteenth PMOS transistor, and the gate Ng14 of the fourteenth NMOS transistor; the source Ps12 of the twelfth PMOS transistor is connected to the power supply VDD; the gate Pg13 of the thirteenth PMOS transistor is connected to the gate Ng14 of the fourteenth NMOS transistor, the drain Pd12 of the twelfth PMOS transistor, and the drain Nd13 of the thirteenth NMOS transistor. The drain Pd13 of the thirteenth PMOS transistor is connected to the drain Nd14 of the fourteenth NMOS transistor, the gate Pg14 of the fourteenth PMOS transistor, and the gate Ng15 of the fifteenth NMOS transistor. The source Ps13 of the thirteenth PMOS transistor is connected to the power supply VDD. The gate Pg14 of the fourteenth PMOS transistor is connected to the gate Ng15 of the fifteenth NMOS transistor, the drain Pd13 of the thirteenth PMOS transistor, and the drain Nd14 of the fourteenth NMOS transistor. The drain Pd14 of the fourteenth PMOS transistor is connected to the drain Nd15 of the fifteenth NMOS transistor, the gate Pg15 of the fifteenth PMOS transistor, and the gate Ng16 of the sixteenth NMOS transistor. The source Ps14 of the fourteenth PMOS transistor is connected to the power supply VDD.The gate Pg15 of the fifteenth PMOS transistor is connected to the gate Ng16 of the sixteenth NMOS transistor, the drain Pd14 of the fourteenth PMOS transistor, and the drain Nd15 of the fifteenth NMOS transistor. The drain Pd15 of the fifteenth PMOS transistor is connected to the drain Nd16 of the sixteenth NMOS transistor, the gate Pg16 of the sixteenth PMOS transistor, and the gate Ng17 of the seventeenth NMOS transistor. The source Ps15 of the fifteenth PMOS transistor is connected to the power supply VDD. The gate Pg16 of the sixteenth PMOS transistor is connected to the gate Ng17 of the seventeenth NMOS transistor, the drain Pd15 of the fifteenth PMOS transistor, and the drain Nd16 of the sixteenth NMOS transistor. The drain Pd16 of the sixteenth PMOS transistor is connected to the drain Nd16 of the seventeenth NMOS transistor and the output signal DS of the data input buffer circuit. The source Ps16 of the sixteenth PMOS transistor is connected to the power supply VDD.

[0039] like Figure 4As shown, the scan control circuit has three input terminals and one output terminal. The three input terminals are respectively connected to the output terminal DS of the data input buffer circuit, the scan input selection terminal SEL, and the scan input data terminal TD. The output terminal S is connected to the main latch. The scan control circuit includes six PMOS transistors and six NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg17 of the seventeenth PMOS transistor is connected to the gate Ng18 of the eighteenth NMOS transistor, the gate Ng21 of the twenty-first NMOS transistor, and the scan input selection terminal. The drain Pd17 of the seventeenth PMOS transistor is connected to the drain Nd18 of the eighteenth NMOS transistor and the gate Pg21 of the twenty-first PMOS transistor. The gates of the 1st and 20th NMOS transistors (Ng20) and the source of the 17th PMOS transistor (Ps17) are connected to the power supply VDD. The gate of the 18th PMOS transistor (Pg18) is connected to the scan input selection terminal, and the drain of the 18th PMOS transistor (Pd18) is connected to the drain of the 19th PMOS transistor (Nd19). The source of the 18th PMOS transistor (Ps18) is connected to the power supply VDD. The gate of the 19th PMOS transistor (Pg19) is connected to the gate of the 19th NMOS transistor (Ng19) and the output terminal DS of the data input buffer circuit. The drain of the 19th PMOS transistor (Pd19) is connected to the drain of the 19th NMOS transistor (Nd19), the drain of the 21st PMOS transistor (Pd21), the drain of the 21st NMOS transistor (Nd21), and the gate of the 22nd PMOS transistor (Pg18). The gates of NMOS transistors g22 and 23 (Ng23) are connected; the source of PMOS transistor Ps19 is connected to the drain of PMOS transistor Pd18; the gate of PMOS transistor 20 is connected to the gate of NMOS transistor 22 and the scan input data terminal TD; the drain of PMOS transistor 20 is connected to the source of PMOS transistor 21 (Ps21); the source of PMOS transistor 20 (Ps20) is connected to the power supply VDD; the gate of PMOS transistor 21 (Pg21) is connected to the drain of PMOS transistor 17 (Nd17) and the drain of PMOS transistor 18 (Nd18); the drain of PMOS transistor 21 (Pd21) is connected to the drain of PMOS transistor 21 (Nd21) and the drain of PMOS transistor 22 (Ng23). The gate Pg22 of the 22nd PMOS transistor is connected to the gate Pg23 of the 23rd NMOS transistor, the drain Pd19 of the 19th PMOS transistor, and the drain Nd19 of the 19th NMOS transistor. The source Ps21 of the 21st PMOS transistor is connected to the drain Pd20 of the 20th PMOS transistor. The gate Pg22 of the 22nd PMOS transistor is connected to the gate Pg23 of the 23rd NMOS transistor, the drain Pd21 of the 21st PMOS transistor, the drain Nd21 of the 21st NMOS transistor, the drain Pd19 of the 19th PMOS transistor, and the drain Nd19 of the 19th NMOS transistor. The drain Pd22 of the 22nd PMOS transistor is connected to the drain Pd23 of the 23rd NMOS transistor. The source Ps22 of the 22nd PMOS transistor is connected to the power supply VDD.The gate Pn18 of the eighteenth NMOS transistor is connected to the gate Ng17 of the seventeenth NMOS transistor, the gate Ng21 of the twenty-first NMOS transistor, and the scan input select terminal SEL. The drain Pd18 of the eighteenth NMOS transistor is connected to the drain Nd17 of the seventeenth NMOS transistor and the gate Ng20 of the twentieth NMOS transistor. The source Ns18 of the eighteenth NMOS transistor is connected to ground VSS. The gate Ng19 of the nineteenth NMOS transistor is connected to the gate Pg19 of the nineteenth PMOS transistor and the output terminal DS of the data input buffer circuit. The drain Nd19 of the nineteenth NMOS transistor is connected to the drain Pd19 of the nineteenth PMOS transistor and the twenty-first PMOS transistor. The drain Pd21 of the OS transistor, the drain Nd21 of the 21st NMOS transistor, the gate Pg22 of the 22nd PMOS transistor, and the gate Ng23 of the 23rd NMOS transistor are connected. The source Ns19 of the 19th NMOS transistor is connected to the drain Nd20 of the 20th NMOS transistor. The gate Ng18 of the 20th NMOS transistor is connected to the drain Nd18 of the 18th NMOS transistor and the drain Pd17 of the 17th PMOS transistor. The drain Nd20 of the 20th NMOS transistor is connected to the source Ns19 of the 19th NMOS transistor. The source Ns20 of the 20th NMOS transistor is connected to ground VSS. The gate Ng21 of the 21st NMOS transistor is connected to the scan. The input selection terminal SEL is connected to the gate Pd17 of the seventeenth PMOS transistor and the gate Ng18 of the eighteenth NMOS transistor. The drain Nd21 of the twenty-first NMOS transistor is connected to the drain Pd21 of the twenty-first PMOS transistor, the gate Pg22 of the twenty-second PMOS transistor, the gate Ng23 of the twenty-third NMOS transistor, the drain Pd19 of the nineteenth PMOS transistor, and the drain Nd19 of the nineteenth NMOS transistor. The source Ns21 of the twenty-first NMOS transistor is connected to the drain Nd22 of the twenty-second NMOS transistor. The gate Ng20 of the twenty-second NMOS transistor is connected to the gate Pg20 of the twentieth PMOS transistor and the scan input data terminal T. D, the drain Pd22 of the 22nd NMOS transistor is connected to the source Ns21 of the 21st NMOS transistor, and the source Ns22 of the 22nd NMOS transistor is connected to ground VSS; the gate Ng23 of the 23rd NMOS transistor is connected to the gate Pg22 of the 22nd PMOS transistor, the drain Pd21 of the 21st PMOS transistor, the drain Nd21 of the 21st NMOS transistor, the drain Pd19 of the 19th PMOS transistor, and the drain Nd19 of the 19th NMOS transistor; the drain Nd23 of the 23rd NMOS transistor is connected to the drain Pd22 of the 22nd PMOS transistor, and the source Ns23 of the 23rd NMOS transistor is connected to ground VSS;

[0040] like Figure 5As shown, the main latch circuit has three input terminals and two output terminals. The three input terminals are connected to the output signal S of the scan control circuit, the positive clock signal C, and the negative clock signal CN, respectively. The two output terminals are connected to the main latch error detection circuit and the main latch error correction circuit. The main latch circuit includes five PMOS transistors and five NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg23 of the twenty-third PMOS transistor is connected to the gate Ng25 of the twenty-fifth NMOS transistor and the output terminal S of the scan control circuit. The drain Pd23 of the twenty-third PMOS transistor is connected to the source Pd24 of the twenty-fourth PMOS transistor. The source Ps23 of the 23rd PMOS transistor is connected to the power supply VDD; the gate Pg24 of the 24th PMOS transistor is connected to the positive output terminal C of the clock circuit; the drain Pd24 of the 24th PMOS transistor is connected to the source Nd24 of the 24th NMOS transistor, the gate Pg25 of the 25th PMOS transistor, and the gate Ng26 of the 26th NMOS transistor; the source Ps24 of the 24th PMOS transistor is connected to the drain Pd23 of the 23rd PMOS transistor; the gate Pg25 of the 25th PMOS transistor is connected to the gate Pg26 of the 26th PMOS transistor, the drain Pd24 of the 24th PMOS transistor, and the drain Nd24 of the 24th NMOS transistor; the 25th PMOS transistor... The drain Pd25 of the S-MOSFET is connected to the drain Nd26 of the 26th NMOS transistor, the gate Pg26 of the 26th PMOS transistor, and the gate Ng28 of the 28th NMOS transistor. The source of the 25th PMOS transistor is connected to the power supply VDD. The gate Pg26 of the 26th PMOS transistor is connected to the gate Ng28 of the 28th NMOS transistor, the drain Pd25 of the 25th PMOS transistor, and the drain Nd26 of the 26th NMOS transistor. The drain Pd26 of the 26th PMOS transistor is connected to the source Ps27 of the 27th PMOS transistor. The source of the 26th PMOS transistor is connected to VDD. The gate Pg27 of the 27th PMOS transistor is connected to the inverting output CN of the clock circuit. The drain Pd27 of the 27th PMOS transistor is connected to the drain Nd27 of the 26th NMOS transistor, the drain Pd24 of the 24th PMOS transistor, and the drain Nd24 of the 24th NMOS transistor. The source of the 27th PMOS transistor is connected to the drain Pd26 of the 26th PMOS transistor. The gate Ng24 of the 24th NMOS transistor is connected to the inverted output terminal CN of the clock circuit. The drain Nd24 of the 24th NMOS transistor is connected to the source Pd24 of the 24th PMOS transistor, the gate Pg25 of the 25th PMOS transistor, and the gate Ng26 of the 26th NMOS transistor. The source Ns24 of the 24th NMOS transistor is connected to the drain Pd25 of the 25th NMOS transistor.The gate Ng25 of the 25th NMOS transistor is connected to the gate Pg23 of the 23rd PMOS transistor and the output terminal S of the scan control circuit. The drain Pd53 of the 25th NMOS transistor is connected to the source Nd24 of the 24th NMOS transistor. The source Ns25 of the 25th NMOS transistor is connected to ground VSS. The gate Ng25 of the 26th NMOS transistor is connected to the gate Pg25 of the 25th PMOS transistor, the drain Pd24 of the 24th PMOS transistor, and the drain Nd24 of the 24th NMOS transistor. The drain Nd26 of the 26th NMOS transistor is connected to the drain Pd25 of the 25th PMOS transistor, the gate Pg26 of the 26th PMOS transistor, and the gate Ng28 of the 28th NMOS transistor. The source of the 26th NMOS transistor is connected to... VSS is connected to ground; the gate Ng27 of the 27th NMOS transistor is connected to the positive output terminal C of the clock circuit; the drain Pd27 of the 27th NMOS transistor is connected to the drain Pd27 of the 27th PMOS transistor, the drain Pd24 of the 24th PMOS transistor, and the drain Nd24 of the 24th NMOS transistor; the source of the 27th NMOS transistor is connected to the drain Nd28 of the 28th NMOS transistor; the gate Ng28 of the 28th NMOS transistor is connected to the gate Pg26 of the 26th PMOS transistor, the drain Pd25 of the 25th PMOS transistor, and the drain Nd26 of the 26th NMOS transistor; the drain Nd28 of the 28th NMOS transistor is connected to the source Ns27 of the 27th NMOS transistor; the source of the 28th NMOS transistor is connected to ground VSS.

[0041] like Figure 6As shown, the main latch error detection circuit has two input terminals and two output terminals. The two input terminals are connected to the internal nodes MN1 and MN2 of the main latch, respectively, and the two output terminals are connected to the input terminals MD1 and MD2 of the main latch error correction circuit, respectively. The main latch error detection circuit includes fourteen PMOS transistors and fourteen NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg28 of the twenty-eighth PMOS transistor is connected to the internal node MN1 of the main latch, and the drain Pd28 of the twenty-eighth PMOS transistor is connected to the drain Nd29 of the twenty-ninth NMOS transistor and the gate Pg30 of the thirtieth PMOS transistor. The gate Ng32 of the 32nd NMOS transistor, the source Pg32 of the 32nd PMOS transistor, and the source Ns33 of the 33rd NMOS transistor, and the source Ps28 of the 28th PMOS transistor are connected to the power supply VDD; the gate Pg29 of the 29th PMOS transistor is connected to the internal node MN2 of the main latch, and the drain Pd29 of the 29th PMOS transistor is connected to the drain Nd30 of the 30th NMOS transistor, the gate Pg31 of the 31st PMOS transistor, and the gate Ng33 of the 33rd NMOS transistor; the source Ps29 of the 29th PMOS transistor is connected to the power supply VDD; the gate Pg30 of the 30th PMOS transistor is connected to the gate Ng32 of the 32nd NMOS transistor. The drain of the 28th PMOS transistor (Pd28) and the drain of the 29th NMOS transistor (Nd29), and the drain of the 30th PMOS transistor (Pd30) are connected to the source of the 31st PMOS transistor (Ps31). The source of the 30th PMOS transistor is connected to the power supply VDD. The gate of the 31st PMOS transistor (Pg31) is connected to the drains of the 29th PMOS transistor (Pd29), the 30th NMOS transistor (Nd30), and the 33rd NMOS transistor (Ng33). The drain of the 31st PMOS transistor is connected to the drains of the 31st NMOS transistor (Nd31), the 32nd PMOS transistor (Pd32), and the 33rd NMOS transistor (Nd33). The source is connected to the drain of the 30th PMOS transistor; the gate Pg32 of the 32nd PMOS transistor is connected to the gate Ng31 of the 31st NMOS transistor, the gate Pg29 of the 29th PMOS transistor, and the gate Ng30 of the 30th NMOS transistor; the drain of the 32nd PMOS transistor is connected to the drain Pd31 of the 31st PMOS transistor, the drain Nd31 of the 31st NMOS transistor, the gate Pg33 of the 33rd PMOS transistor, and the gate Ng34 of the 34th NMOS transistor; the source of the 32nd PMOS transistor is connected to the source Ns33 of the 33rd NMOS transistor, the drain Pd28 of the 28th PMOS transistor, and the drain Nd29 of the 29th NMOS transistor.The gate Pg33 of the 33rd PMOS transistor is connected to the gate Ng34 of the 34th NMOS transistor, the drain Pd32 of the 32nd PMOS transistor, the drain Nd33 of the 33rd NMOS transistor, the drain Pd31 of the 31st PMOS transistor, and the drain Nd31 of the 31st NMOS transistor. The drain of the 33rd PMOS transistor is connected to the drain Nd34 of the 34th NMOS transistor, the gate Pg34 of the 34th PMOS transistor, and the gate Ng35 of the 35th NMOS transistor. The source of the 33rd PMOS transistor is connected to the power supply VDD. The gate Pg34 of the 34th PMOS transistor is connected to the gate of the 35th NMOS transistor. The drain of the 33rd PMOS transistor (Ng35), the drain of the 34th NMOS transistor (Pd33), and the drain of the 34th NMOS transistor (Nd34) are connected. The drain of the 34th PMOS transistor (Pd34) is connected to the drain of the 35th NMOS transistor (Nd35), and the source of the 34th PMOS transistor is connected to the power supply VDD. The gate of the 29th NMOS transistor (Ng29) is connected to the internal node MN1 of the main latch. The drain of the 29th NMOS transistor (Nd29) is connected to the drain of the 28th PMOS transistor (Pd28), the gate of the 30th PMOS transistor (Pg30), the gate of the 32nd NMOS transistor (Ng32), the source of the 32nd PMOS transistor (Pg32), and the source of the 33rd NMOS transistor (Ng35). The source of the S-MOSFET, Ns33, and the source of the 29th NMOS transistor, Ps28, are connected to ground VSS. The gate of the 30th NMOS transistor, Ng30, is connected to the internal node MN2 of the main latch. The drain of the 30th NMOS transistor, Nd30, is connected to the drain of the 29th PMOS transistor, Nd30, the gate of the 31st PMOS transistor, Pg31, and the gate of the 33rd NMOS transistor, Ng33. The source of the 30th NMOS transistor, Ns29, is connected to ground VSS. The gate of the 31st NMOS transistor, Ng31, is connected to the gate of the 29th PMOS transistor, Pg29, the source of the 32nd PMOS transistor, Ps32, and the source of the 33rd NMOS transistor, N. s33, the drain of the thirty-first NMOS transistor is connected to the drain of the thirty-first PMOS transistor Pd31, the drain of the thirty-second PMOS transistor Pd32, and the drain of the thirty-third NMOS transistor Nd33; the source of the thirty-first NMOS transistor is connected to the drain of the thirty-second NMOS transistor; the gate of the thirty-second NMOS transistor Ng32 is connected to the gate of the thirtieth PMOS transistor Pg30, the drain of the twenty-eighth PMOS transistor Pd28, and the drain of the twenty-ninth NMOS transistor Nd29; the drain of the thirty-second NMOS transistor Nd32 is connected to the source of the thirty-first NMOS transistor Ns31; the source of the thirty-second NMOS transistor is connected to ground VSS.The gate Ng33 of the 33rd NMOS transistor is connected to the gate Pg31 of the 31st PMOS transistor, the drain Pd29 of the 29th PMOS transistor, and the drain Nd30 of the 30th NMOS transistor. The drain of the 33rd NMOS transistor is connected to the drain Pd31 of the 31st PMOS transistor, the drain Nd31 of the 31st NMOS transistor, the gate Pg33 of the 33rd PMOS transistor, and the gate Ng34 of the 34th NMOS transistor. The source of the 33rd NMOS transistor is connected to the source Ps32 of the 32nd PMOS transistor, the drain Pd28 of the 28th PMOS transistor, and the drain Nd29 of the 29th NMOS transistor. The gate Ng34 of the 34th NMOS transistor is connected to the gate Pg33 of the 33rd PMOS transistor and the drain of the 32nd PMOS transistor. Pd32, the drain of the 33rd NMOS transistor Nd33, the drain of the 31st PMOS transistor Pd31 and the drain of the 31st NMOS transistor Nd31, the drain of the 34th NMOS transistor is connected to the drain of the 33rd PMOS transistor Pd33, the gate of the 34th PMOS transistor Pg34 and the gate of the 35th NMOS transistor Ng35, the source of the 34th NMOS transistor is connected to ground VSS; the gate of the 35th NMOS transistor Ng35 is connected to the gate of the 34th PMOS transistor Pg34, the drain of the 35th NMOS transistor Nd35 and the drain of the 34th PMOS transistor Pd34, the drain of the 35th NMOS transistor Nd35 is connected to the drain of the 34th PMOS transistor Pd34, the source of the 35th NMOS transistor is connected to ground VSS;

[0042] like Figure 7As shown, the master latch error correction circuit has two input terminals and one output terminal. The two input terminals are connected to the output terminals MD1 and MD2 of the master latch error detection circuit, respectively, and the output terminal is connected to the input terminal MC of the slave latch circuit. The master latch error correction circuit includes three PMOS transistors, three NMOS transistors, and one resistor. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg35 of the thirty-fifth PMOS transistor is connected to the output terminal MD2 of the master latch error detection circuit, and the gate Pg35 of the thirty-fifth PMOS transistor is connected to the output terminal MD2 of the master latch error detection circuit. The drain Pd35 of the 36th NMOS transistor is connected to the drain Nd36 of the 36th NMOS transistor, and the source Ps35 of the 35th PMOS transistor is connected to the source Ns36 of the 36th NMOS transistor. The gate Pg35 of the 36th PMOS transistor is connected to the output terminal MD1 of the main latch error detection circuit. The drain Pd36 of the 36th PMOS transistor is connected to the drain Nd37 of the 37th NMOS transistor, and the source Ps36 of the 36th PMOS transistor is connected to the source Ns37 of the 37th NMOS transistor. The gate Pg37 of the 37th PMOS transistor is connected to the gate Pg37 of the 36th PMOS transistor. The source Ps36 and the source Ns37 of the 37th NMOS transistor, the drain Pd37 and source Ps37 of the 37th PMOS transistor are connected to the power supply VDD; the gate Ng36 of the 36th NMOS transistor is connected to the output terminal MD1 of the main latch error detection circuit; the drain Nd36 of the 36th NMOS transistor is connected to the drain Pd35 of the 35th PMOS transistor; the source Ns36 of the 36th NMOS transistor is connected to the source Ps35 of the 35th PMOS transistor; the gate Ng37 of the 37th NMOS transistor is connected to the output terminal MD1 of the main latch error detection circuit. 2. The drain Nd37 of the 37th NMOS transistor is connected to the drain Pd36 of the 36th PMOS transistor, and the source Ns37 of the 37th NMOS transistor is connected to the source Ps36 of the 36th PMOS transistor; the gate Ng38 of the 38th NMOS transistor is connected to the source Ps36 of the 36th PMOS transistor and the source Ns37 of the 37th NMOS transistor, and the drain Nd37 and source Ns37 of the 38th NMOS transistor are connected to ground VSS; resistor R1 is connected to the output terminal MD2 of the main latch error detection circuit and the output terminal MC of the main latch error correction circuit.

[0043] like Figure 8As shown, the slave latch circuit has three input terminals and two output terminals. The three input terminals are respectively connected to the output signal MC of the master latch error correction circuit, the positive clock signal C, and the negative clock signal CN. The two output terminals are connected to the slave latch error detection circuit and the slave latch error correction circuit. The slave latch circuit includes five PMOS transistors and five NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg38 of the thirty-eighth PMOS transistor is connected to the gate Ng40 of the fortieth NMOS transistor and the output terminal MC of the master latch error correction circuit. The drain Pd38 of the thirty-eighth PMOS transistor is connected to the source Pd39 of the thirty-ninth PMOS transistor. The source Ps38 of the 38th PMOS transistor is connected to the power supply VDD; the gate Pg39 of the 39th PMOS transistor is connected to the positive output terminal C of the clock circuit; the drain Pd39 of the 39th PMOS transistor is connected to the source Nd39 of the 39th NMOS transistor, the gate Pg40 of the 40th PMOS transistor, and the gate Ng41 of the 41st NMOS transistor; the source Ps39 of the 39th PMOS transistor is connected to the drain Pd38 of the 38th PMOS transistor; the gate Pg40 of the 40th PMOS transistor is connected to the gate Ng41 of the 41st NMOS transistor, the drain Pd39 of the 39th PMOS transistor, and the drain Nd39 of the 39th NMOS transistor; the drain Pd42 of the 42nd PMOS transistor is connected to the source Ps39 of the 38th PMOS transistor. The drain of the 42nd NMOS transistor (Nd42) and the drain of the 40th PMOS transistor (Pd40) are connected to the drain of the 41st NMOS transistor (Nd41), the gate of the 41st PMOS transistor (Pg41), and the gate of the 43rd NMOS transistor (Ng43). The source of the 40th PMOS transistor is connected to the power supply VDD. The gate of the 41st PMOS transistor (Pg41) is connected to the gate of the 43rd NMOS transistor (Ng43), the drain of the 40th PMOS transistor (Pd40), and the drain of the 41st NMOS transistor (Nd41). The drain of the 41st PMOS transistor (Pd41) is connected to the source of the 42nd PMOS transistor (Ps42). The source of the 41st PMOS transistor is connected to VDD. The gate of the 42nd PMOS transistor (Pg42) is connected to the clock signal. The inverting output terminal CN of the circuit is connected to the drain Pd42 of the 42nd PMOS transistor, which is connected to the drain Nd42 of the 42nd NMOS transistor, the drain Pd39 of the 39th PMOS transistor, and the drain Nd39 of the 39th NMOS transistor. The source of the 42nd PMOS transistor is connected to the drain Pd41 of the 41st PMOS transistor. The gate Ng39 of the 39th NMOS transistor is connected to the inverting output terminal CN of the clock circuit. The drain Nd39 of the 39th NMOS transistor is connected to the drain Ps39 of the 39th PMOS transistor, the gate Pg40 of the 40th PMOS transistor, and the gate Ng41 of the 41st NMOS transistor. The source Ns39 of the 39th NMOS transistor is connected to the drain Pd40 of the 40th NMOS transistor.The gate Ng40 of the 40th NMOS transistor is connected to the gate Pg38 of the 38th PMOS transistor and the output MC of the main latch error correction circuit. The drain Pd40 of the 40th NMOS transistor is connected to the source Nd39 of the 39th NMOS transistor. The source Ns40 of the 40th NMOS transistor is connected to ground VSS. The gate Ng41 of the 41st NMOS transistor is connected to the gate Pg40 of the 40th PMOS transistor, the drain Pd39 of the 39th PMOS transistor, and the drain Nd39 of the 39th NMOS transistor. The drain Nd41 of the 41st NMOS transistor is connected to the drain Pd40 of the 40th PMOS transistor, the gate Pg41 of the 41st PMOS transistor, and the gate Ng43 of the 43rd NMOS transistor. The source of the 41st NMOS transistor is connected to... VSS is connected to ground; the gate Ng42 of the 42nd NMOS transistor is connected to the positive output terminal C of the clock circuit; the drain Pd42 of the 42nd NMOS transistor is connected to the drain Pd42 of the 42nd PMOS transistor, the drain Pd39 of the 39th PMOS transistor, and the drain Nd39 of the 39th NMOS transistor; the source of the 42nd NMOS transistor is connected to the drain Nd43 of the 43rd NMOS transistor; the gate Ng43 of the 43rd NMOS transistor is connected to the gate Pg41 of the 41st PMOS transistor, the drain Pd40 of the 40th PMOS transistor, and the drain Nd41 of the 41st NMOS transistor; the drain Nd43 of the 43rd NMOS transistor is connected to the source Ns42 of the 42nd NMOS transistor; and the source of the 43rd NMOS transistor is connected to ground VSS.

[0044] like Figure 9As shown, the latch error detection circuit has two input terminals and two output terminals. The two input terminals are connected to the internal nodes SN1 and SN2 of the latch, respectively, and the two output terminals are connected to the input terminals SD1 and SD2 of the master latch error correction circuit, respectively. The latch error detection circuit includes fourteen PMOS transistors and fourteen NMOS transistors. The substrates of all PMOS transistors in the circuit are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg43 of the forty-third PMOS transistor is connected to the internal node SN1 of the latch, and the drain Pd43 of the forty-third PMOS transistor is connected to the drain Nd44 of the forty-fourth NMOS transistor, the gate Pg45 of the forty-fifth PMOS transistor, and the... The gate Ng47 of the 47th NMOS transistor, the source Pg47 of the 47th PMOS transistor, and the source Ns48 of the 48th NMOS transistor are connected to the power supply VDD. The gate Pg44 of the 44th PMOS transistor is connected to the internal node SN2 of the latch. The drain Pd44 of the 44th PMOS transistor is connected to the drain Nd45 of the 45th NMOS transistor, the gate Pg46 of the 46th PMOS transistor, and the gate Ng48 of the 48th NMOS transistor. The source Ps44 of the 44th PMOS transistor is connected to the power supply VDD. The gate Pg45 of the 45th PMOS transistor is connected to the gate Ng47 of the 47th NMOS transistor, and the source Ns48 of the 48th NMOS transistor. The drain of the 13th PMOS transistor (Pd43) and the drain of the 44th NMOS transistor (Nd44), and the drain of the 45th PMOS transistor (Pd45) are connected to the source of the 46th PMOS transistor (Ps46). The source of the 45th PMOS transistor is connected to the power supply VDD. The gate of the 46th PMOS transistor (Pg46) is connected to the drain of the 44th PMOS transistor (Pd44), the drain of the 45th NMOS transistor (Nd45), and the gate of the 48th NMOS transistor (Ng48). The drain of the 46th PMOS transistor is connected to the drain of the 46th NMOS transistor (Nd46), the drain of the 47th PMOS transistor (Pd47), and the drain of the 48th NMOS transistor (Nd48). The source of the 46th PMOS transistor is connected to... The drain of the 45th PMOS transistor is connected to Pd45; the gate of the 47th PMOS transistor is connected to the gate of the 46th NMOS transistor (Ng46), the gate of the 44th PMOS transistor (Pg44), and the gate of the 45th NMOS transistor (Ng45); the drain of the 47th PMOS transistor is connected to the drain of the 46th PMOS transistor (Pd46), the drain of the 46th NMOS transistor (Nd46), the gate of the 48th PMOS transistor (Pg48), and the gate of the 49th NMOS transistor (Ng49); the source of the 47th PMOS transistor is connected to the source of the 48th NMOS transistor (Ns48), the drain of the 43rd PMOS transistor (Pd43), and the drain of the 44th NMOS transistor (Nd44);The gate Pg48 of the 48th PMOS transistor is connected to the gate Ng49 of the 49th NMOS transistor, the drain Pd46 and Nd46 of the 46th PMOS transistor, the drain Pd47 and Nd48 of the 47th PMOS transistor, and the drain Ng49 of the 48th PMOS transistor is connected to the drain Nd49 and gate Pg49 of the 49th PMOS transistor, and the gate Ng50 of the 50th NMOS transistor. The source of the 48th PMOS transistor is connected to the power supply VDD; the gate Pg49 of the 49th PMOS transistor is connected to the gate Ng50 of the 50th NMOS transistor. 50. The drain of the 48th PMOS transistor (Pd48) and the drain of the 49th NMOS transistor (Nd49) are connected. The drain of the 49th PMOS transistor (Pd49) is connected to the drain of the 50th NMOS transistor (Nd50). The source of the 49th PMOS transistor is connected to the power supply VDD. The gate of the 44th NMOS transistor (Ng44) is connected to the internal node SN1 of the latch. The drain of the 44th NMOS transistor (Nd44) is connected to the drain of the 43rd PMOS transistor (Pd43), the gate of the 45th PMOS transistor (Pg45), the gate of the 47th NMOS transistor (Ng47), the source of the 47th PMOS transistor (Pg47), and the source of the 48th NMOS transistor. Ns48, the source Ps44 of the forty-fourth NMOS transistor is connected to ground VSS; the gate Ng45 of the forty-fifth NMOS transistor is connected to the internal node SN2 of the latch; the drain Nd45 of the forty-fifth NMOS transistor is connected to the drain Pd44 of the forty-fourth PMOS transistor, the gate Pg46 of the forty-sixth PMOS transistor, and the gate Ng48 of the forty-eighth NMOS transistor; the source Ns45 of the forty-fifth NMOS transistor is connected to ground VSS; the gate Ng46 of the forty-sixth NMOS transistor is connected to the gate Pg47 of the forty-seventh PMOS transistor, the gate Ps44 of the forty-fourth PMOS transistor, and the gate Ns45 of the forty-fifth NMOS transistor. The drain of the 46th NMOS transistor is connected to the drain of the 46th PMOS transistor (Pd46), the drain of the 47th PMOS transistor (Pd47), and the drain of the 48th NMOS transistor (Nd48). The source of the 46th NMOS transistor is connected to the drain of the 47th NMOS transistor (Nd47). The gate of the 47th NMOS transistor (Ng47) is connected to the gate of the 45th PMOS transistor (Pg45), the drain of the 43rd PMOS transistor (Pd43), and the drain of the 44th NMOS transistor (Nd44). The drain of the 47th NMOS transistor (Nd47) is connected to the source of the 46th NMOS transistor (Ns46). The source of the 47th NMOS transistor is connected to ground (VSS).The gate Ng48 of the 48th NMOS transistor is connected to the gate Pg46 of the 46th PMOS transistor, the drain Pd44 of the 44th PMOS transistor, and the drain Nd45 of the 45th NMOS transistor. The drain of the 48th NMOS transistor is connected to the drain Pd47 of the 47th PMOS transistor, the drain Nd46 of the 46th NMOS transistor, the gate Pg48 of the 48th PMOS transistor, and the gate Ng49 of the 49th NMOS transistor. The source Ns48 of the 48th NMOS transistor is connected to the source Ps47 of the 47th PMOS transistor, the drain Pd43 of the 43rd PMOS transistor, and the drain Nd44 of the 44th NMOS transistor. The gate Ng49 of the 49th NMOS transistor is connected to the gate Pg48 of the 48th PMOS transistor and the gate Ng45 of the 46th PMOS transistor. The drain of the S-MOSFET is Pd46, the drain of the 46th NMOS transistor is Nd46, the drain of the 47th PMOS transistor is Pd47, and the drain of the 48th NMOS transistor is Nd48. The drain of the 49th NMOS transistor is connected to the drain of the 48th PMOS transistor, the gate of the 49th PMOS transistor is Pg49, and the gate of the 50th NMOS transistor is Ng50. The source of the 49th NMOS transistor is connected to ground VSS. The gate of the 50th NMOS transistor is Ng50, which is connected to the gate of the 49th PMOS transistor, the drain of the 49th NMOS transistor is Nd49, and the drain of the 48th PMOS transistor is Pd48. The drain of the 50th NMOS transistor is Nd50, which is connected to the drain of the 50th PMOS transistor is Pd50. The source of the 50th NMOS transistor is connected to ground VSS.

[0045] like Figure 10As shown, the slave latch error correction circuit has two inputs and one output. The two inputs are connected to the outputs SD1 and SD2 of the master latch error detection circuit, respectively, and the output is connected to the input SC of the output circuit. The slave latch error correction circuit includes three PMOS transistors, three NMOS transistors, and one resistor. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are connected to ground VSS. The gate Pg50 of the fiftieth PMOS transistor is connected to the output SD2 of the slave latch error detection circuit, and the drain Pg50 of the fiftieth PMOS transistor is connected to the output Pg50 of the master latch error detection circuit. d50 is connected to the drain Nd51 of the 51st NMOS transistor, and Ps50 of the 50th PMOS transistor is connected to the source Ns51 of the 51st NMOS transistor; Pg51 of the 51st PMOS transistor is connected to the output SD1 of the latch error detection circuit; Pd51 of the 51st PMOS transistor is connected to the drain Nd52 of the 52nd NMOS transistor; Ps51 of the 51st PMOS transistor is connected to the source Ns52 of the 52nd NMOS transistor; Pg52 of the 52nd PMOS transistor is connected to the source of the 51st PMOS transistor. The source Ns52 of the 52nd NMOS transistor and the drain Pd52 and source Ps52 of the 52nd PMOS transistor are connected to the power supply VDD; the gate Ng51 of the 51st NMOS transistor is connected to the output terminal SD1 of the latch error detection circuit, the drain Nd51 of the 51st NMOS transistor is connected to the drain Pd50 of the 50th PMOS transistor, and the source Ns51 of the 51st NMOS transistor is connected to the source Ps50 of the 50th PMOS transistor; the gate Ng52 of the 52nd NMOS transistor is connected to the output terminal SD2 of the main latch error detection circuit. The drain Nd52 of the 52nd NMOS transistor is connected to the drain Pd51 of the 51st PMOS transistor, and the source Ns52 of the 52nd NMOS transistor is connected to the source Ps51 of the 51st PMOS transistor; the gate Ng53 of the 53rd NMOS transistor is connected to the source Ps51 of the 51st PMOS transistor and the source Ns52 of the 52nd NMOS transistor, and the drain Nd53 and source Ns53 of the 53rd NMOS transistor are connected to ground VSS; resistor R2 is connected to the output terminal SD2 of the latch error detection circuit and the output terminal SC of the latch error correction circuit.

[0046] like Figure 11As shown, the output circuit has one input and two outputs. The input is connected to the output SC of the latch error correction circuit, and the two outputs are Q and its inverted output signal QN. SC is output to QN through a three-stage inverter consisting of the 53rd PMOS and 54th NMOS, the 54th PMOS and 55th NMOS, and the 55th PMOS and 56th NMOS. SC is also output to Q through a two-stage inverter consisting of the 56th PMOS and 57th NMOS, and the 57th PMOS and 58th NMOS.

[0047] like Figure 12 As shown, the simulation results of SEU fault injection for a general-purpose D flip-flop with scan input function are presented. Fault injection is performed at node MN1 inside the main latch, using a double exponential current source. The pulse amplitude is set to 120.36 μA, the duration to 500 picoseconds, and both the rise and fall times to 50 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated after simulated particle bombardment, the output Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0048] like Figure 13 As shown, the simulation results of SEU fault injection for the scanning structure D flip-flop with self-healing function and resistance to single-event upsets and single-event transients proposed in this invention are presented. A radiation pulse with the same parameters as described above is used to inject a fault into node MN1 inside the main latch of the D flip-flop proposed in this invention. After the error detection circuit detects the flip-flop of node MN1, it sends error generation signals MD1 and MD2 to the main latch error correction circuit. The main latch error correction circuit starts to work and filters and eliminates the generated transient pulse. Therefore, it is ensured that the transient pulse generated by the particle bombardment does not affect the output signal Q.

[0049] like Figure 14 As shown, the simulation results of fault injection at the data terminal SET of a general-purpose D flip-flop with scan input function are presented. Fault injection is performed at the input data terminal D, and the transient pulse duration is set to 660 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated by the simulated particle bombardment at the data terminal, the output terminal Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0050] like Figure 15As shown, simulation results of the data terminal SET fault injection of the scanning structure D flip-flop with self-healing function and resistance to single-event upsets and single-event transients of the present invention are presented. Fault injection is performed at the input data terminal D, and the transient pulse duration is set to 660 picoseconds. As can be seen from the figure, due to the formation of an anti-SET structure composed of delay units and Miller C units in the data input circuit, the transient pulse generated by the particle bombardment of the data terminal is guaranteed not to affect the output signal Q.

[0051] like Figure 16 As shown, the simulation results of fault injection at the clock input SET of a general-purpose D flip-flop with scan input function are presented. Fault injection is performed at the clock input CK, and the transient pulse duration is set to 350 picoseconds. As can be seen from the figure, under the influence of the fault pulse generated by simulated particle bombardment of the clock input, the output Q of the general-purpose D flip-flop with scan input function exhibits an erroneous flip.

[0052] like Figure 17 As shown, simulation results of the clock input SET fault injection for the self-healing, anti-single-event upset (SWE) and anti-single-event transient (SET) scanning structure D flip-flop of this invention are presented. Fault injection is performed at the clock input CK, and the transient pulse duration is set to 350 picoseconds. As can be seen from the figure, due to the formation of an anti-SET structure consisting of delay units and Miller C units in the clock circuit, the transient pulse generated by the particle bombardment data terminal is guaranteed not to affect the output signal Q.

Claims

1. A scan-structure D flip-flop with soft error self-correction function, characterized in that, The system includes a data input buffer circuit, a scan control circuit, a master latch, a master latch error detection circuit, a master latch error correction circuit, a slave latch, a slave latch error detection circuit, a slave latch error correction circuit, and an output circuit, all connected in sequence. It also includes a clock circuit connected to the master latch and the slave latch respectively. The master latch is connected to the master latch error correction circuit, and the slave latch is connected to the slave latch error correction circuit. The master latch error detection circuit and the slave latch error detection circuit have the same structure. The master latch error detection circuit includes: the input terminal of the inverting MOS unit M17 serves as the first input terminal of the master latch error detection circuit and is connected to the first output terminal of the master latch; the output terminal of the inverting MOS unit M17 is connected to the gate of PMOS transistor P30, the gate of NMOS transistor N32, the source of PMOS transistor P32, and the source of NMOS transistor N33, respectively; the input terminal of the inverting MOS unit M18 serves as the second input terminal of the master latch error detection circuit and is connected to the second output terminal of the master latch, the gate of NMOS transistor N31, and the gate of PMOS transistor P32, respectively; the output terminal of the inverting MOS unit M18 is connected to the gate of PMOS transistor P31 and the gate of NMOS transistor N33, respectively. The source of PMOS transistor P30 is connected to power supply VDD. The drain of PMOS transistor P30 is connected to the source of PMOS transistor P31. The drain of PMOS transistor P31 is connected to the drain of NMOS transistor N31. The source of NMOS transistor N31 is connected to the drain of NMOS transistor N32. The source of NMOS transistor N32 is grounded. The gate of PMOS transistor P30 is connected to the gate of NMOS transistor N32. The drain of PMOS transistor P32 is connected to the drain of PMOS transistor P31, the drain of NMOS transistor N33, and the input of the inverting MOS unit M19. The output of the inverting MOS unit M19 serves as the first output of the main latch error detection circuit and is connected to the input of the inverting MOS unit M20. The output of the inverting MOS unit M20 serves as the second output of the main latch error detection circuit.

2. The scan structure D flip-flop with soft error self-correction function according to claim 1, characterized in that, The clock circuit includes: the input terminal of the inverting MOS unit M1 is connected to the gate of PMOS transistor P5 and the gate of NMOS transistor N6, respectively, serving as the clock signal input terminal of the clock circuit; the output terminal of the inverting MOS unit M4 is connected to the gate of PMOS transistor P6 and the gate of NMOS transistor N5, respectively; the inverting MOS units M1 to M4 are connected in series; the source of PMOS transistor P5 is connected to the power supply VDD; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the drain of PMOS transistor P6 is connected to the input terminal of the inverting MOS unit M5 and the drain of NMOS transistor N5, respectively; and the NMOS transistor N6... The source of transistor P5 is connected to the drain of NMOS transistor N6, and the source of NMOS transistor N6 is grounded. The source of PMOS transistor P7 is connected to the power supply VDD. The gate of PMOS transistor P7 is connected to the gate of NMOS transistor N7, the gate of NMOS transistor N8, and the output of the reverse MOS unit M5, serving as the positive clock output of the clock circuit. The drain of PMOS transistor P7 is connected to the drain of NMOS transistor N7 and the input of the reverse MOS unit M5, serving as the negative clock output of the clock circuit. The source of NMOS transistor N7 is connected to the drain of NMOS transistor N8, and the source of NMOS transistor N8 is grounded.

3. The scan structure D flip-flop with soft error self-correction function according to claim 1, characterized in that, The data input buffer circuit consists of eight sets of series-connected inverted MOS units M6 to M13. The input terminal of the inverted MOS unit M6 serves as the input terminal of the data input buffer circuit, and the output terminal of the inverted MOS unit M13 serves as the output terminal of the data input buffer circuit.

4. The scan structure D flip-flop with soft error self-correction function according to claim 1, characterized in that, The scan control circuit includes: the input terminal of the inverting MOS unit M14 is connected to the gate of PMOS transistor P18 and the gate of NMOS transistor N21, respectively, serving as the scan input selection terminal of the scan control circuit; the output terminal of the inverting MOS unit M14 is connected to the gate of PMOS transistor P21 and the gate of NMOS transistor N20, respectively; the source of PMOS transistor P18 is connected to the power supply VDD; the drain of PMOS transistor P18 is connected to the source of PMOS transistor P19; the drain of PMOS transistor P19 is connected to the drain of NMOS transistor N19, the drain of PMOS transistor P21, and the input terminal of the inverting MOS unit M15, respectively; the source of NMOS transistor N19 is connected to the drain of NMOS transistor N20; and the NMOS transistor N20... The source of S-MOSFET N20 is grounded. The gate of PMOS transistor P19 is connected to the gate of NMOS transistor N19, serving as the input terminal of the scan control circuit and the output terminal of the data input buffer circuit. The source of PMOS transistor P20 is connected to the power supply VDD. The drain of PMOS transistor P20 is connected to the source of PMOS transistor P21. The drain of PMOS transistor P21 is connected to the drain of NMOS transistor N21. The source of NMOS transistor N21 is connected to the drain of NMOS transistor N22. The source of NMOS transistor N22 is grounded. The gate of PMOS transistor P20 is connected to the gate of NMOS transistor N22, serving as the scan input data terminal of the scan control circuit. The output terminal of the inverting MOS unit M15 serves as the signal output terminal of the scan control circuit.

5. The scan structure D flip-flop with soft error self-correction function according to claim 1, characterized in that, The master latch and slave latch have the same structure. The master latch includes: the source of PMOS transistor P23 is connected to power supply VDD; the drain of PMOS transistor P23 is connected to the source of PMOS transistor P24; the drain of PMOS transistor P24 is connected to the drain of NMOS transistor N24, the input terminal of the inverting MOS unit M16, and the drain of PMOS transistor P27; the source of NMOS transistor N24 is connected to the drain of NMOS transistor N25; the source of NMOS transistor N25 is grounded; the gate of PMOS transistor P23 is connected to the gate of NMOS transistor N25, serving as the signal input terminal of the master latch and connected to the signal output terminal of the scan control circuit; the gate of PMOS transistor P24 serves as the positive clock signal input terminal of the master latch and is connected to the positive clock output terminal of the clock circuit; the gate of NMOS transistor N24 serves as the negative clock signal input terminal of the master latch and is connected to the negative clock output terminal of the clock circuit. The clock output is connected. The source of PMOS transistor P26 is connected to power supply VDD. The drain of PMOS transistor P26 is connected to the source of PMOS transistor P27. The drain of PMOS transistor P27 is connected to the drain of NMOS transistor N27. The source of NMOS transistor N27 is connected to the drain of NMOS transistor N28. The source of NMOS transistor N28 is grounded. The gate of PMOS transistor P26 is connected to the gate of NMOS transistor N28 and the output of the inverting MOS unit M16. The gate of PMOS transistor P27 serves as the inverted clock signal input of the main latch and is connected to the inverted clock output of the clock circuit. The gate of NMOS transistor N27 serves as the positive clock signal input of the main latch and is connected to the positive clock output of the clock circuit. The input of the inverting MOS unit M16 serves as the first output of the main latch, and the output of the inverting MOS unit M16 serves as the second output of the main latch.

6. The scan structure D flip-flop with soft error self-correction function according to claim 1, characterized in that, The master latch error correction circuit and the slave latch error correction circuit have the same structure. The master latch error correction circuit includes: one end of resistor R1 is connected to the second output terminal of the master latch, the drain of PMOS transistor P35, and the drain of NMOS transistor N36, respectively; one end of resistor R1 serves as the output terminal of the master latch error correction circuit, and is connected to the source of PMOS transistor P35, the source of NMOS transistor N36, the drain of PMOS transistor P36, and the drain of NMOS transistor N37, respectively. The source of transistor 36 is connected to the source of NMOS transistor N37, the gate of PMOS transistor P37, and the gate of NMOS transistor N38, respectively. The gates of NMOS transistor N36 and PMOS transistor P36 are both connected to the first output terminal of the main latch error detection circuit. The gates of PMOS transistor P35 and NMOS transistor N37 are both connected to the second output terminal of the main latch error detection circuit. The source and drain of PMOS transistor P37 are both connected to the power supply VDD, and the source and drain of NMOS transistor N38 are both grounded.

7. The scan structure D flip-flop with soft error self-correction function according to claim 1, characterized in that, The output circuit includes: the input terminal of the inverting MOS unit M22 serves as the input terminal of the output circuit, and is connected to the input terminal of the inverting MOS unit M25 and the output terminal of the latch error correction circuit, respectively; the output terminal of the inverting MOS unit M22 is connected to the input terminal of the inverting MOS unit M23; the output terminal of the inverting MOS unit M23 is connected to the input terminal of the inverting MOS unit M24; the output terminal of the inverting MOS unit M24 serves as the inverted signal output terminal of the output circuit; the output terminal of the inverting MOS unit M25 is connected to the output terminal of the inverting MOS unit M26; and the output terminal of the inverting MOS unit M26 serves as the signal output terminal of the output circuit.

8. The scan-structure D flip-flop with soft error self-correction function according to any one of claims 2, 3, 4, 5, and 7, characterized in that, The reverse MOS unit includes a PMOS transistor and an NMOS transistor. The gates of the PMOS transistor and the NMOS transistor are connected as the input terminal of the reverse MOS unit, and the drains of the PMOS transistor and the NMOS transistor are connected as the output terminal of the reverse MOS unit. The source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is grounded.

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