A maximum peak detection circuit and its control method

Abstract

This invention belongs to the field of detection circuit technology, and relates to a maximum peak value detection circuit and its control method. The ADC and MCU in the detection circuit are electrically connected, and the input voltage V... in The diode D is connected to its anode, the positive input of voltage comparator P1 is connected to the cathode of diode D, and the negative input of voltage comparator P1 is connected to the voltage holding threshold V. hd The output of P1 sends a HOLD sampling capacitor hold signal to the MCU. Electronic switch Q1 is connected in parallel with sampling and holding capacitor C1. The collector of Q1 is connected to the cathode of diode D and the input of the ADC, and the emitter of Q1 is grounded. C2 is connected in parallel with electronic switch Q2. The collector of Q2 is connected to the emitter of Q3 and the signal processing circuit, and the emitter of Q2 is grounded. The signal processing circuit is connected to the MCU. The collector of Q3 is connected to the cathode of diode D, and the base of Q3 is a high-frequency clock pulse signal. The bases of both Q2 and Q1 are connected to the MCU. This invention provides accurate data acquisition and avoids data loss due to asynchronous acquisition.

Description

Technical Field

[0001] This invention belongs to the field of detection circuit technology, specifically relating to a maximum peak value detection circuit and its control method. Background Technology

[0002] To address the issue of maximum peak sampling circuits for aperiodic signals, during analog-to-digital conversion (ADC), since the sampling circuit and the ADC operate asynchronously, if the maximum peak occurs during the ADC's analog-to-digital conversion period, and the sampling capacitor of the maximum peak sampling circuit discharges due to the end of the hold time, the ADC will be unable to identify the maximum peak in this situation, resulting in data loss. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a maximum peak value detection circuit and its control method. The technical solution adopted by this invention is as follows:

[0004] A maximum peak detection circuit includes: a diode D, a sample-and-hold capacitor C1, an electronic switch Q1, a voltage comparator P1, an AD converter chip (ADC), and a microcontroller unit (MCU). The AD converter chip and the microcontroller unit (MCU) are electrically connected, and the input voltage is V. in The signal being acquired includes electronic switches Q3 and Q2, a sample-and-hold capacitor C2, and signal processing circuitry. The input voltage V... in The anode of diode D is connected to the diode, and the positive input of voltage comparator P1 is connected to the cathode of diode D. The input voltage at the negative input of voltage comparator P1 is the voltage holding threshold voltage V. hd The output of voltage comparator P1 outputs a sampling and holding signal (HOLD) to the microcontroller unit (MCU). Electronic switch Q1 is connected in parallel with sampling and holding capacitor C1. The collector of Q1 is connected to the cathode of diode D and the input of the ADC, and the emitter of Q1 is grounded. Sampling and holding capacitor C2 is connected in parallel with electronic switch Q2. The collector of Q2 is connected to the emitter of Q3 and the signal processing circuit, and the emitter of Q2 is grounded. The signal processing circuit is connected to the MCU. The collector of Q3 is connected to the cathode of diode D, and the base of Q3 is a high-frequency clock pulse signal. The bases of both Q2 and Q1 are connected to the MCU.

[0005] Preferably, the electronic switching transistors Q1, Q2, and Q3 are NPN transistors, and the sampling and holding capacitors C1 and C2 are mica capacitors or film capacitors.

[0006] A control method for a maximum peak detection circuit, using the aforementioned maximum peak detection circuit, includes the following steps:

[0007] Step 1: Initialize the control parameters. k: delay coefficient, 0 < k < 1, CNT = 0, DISC = 0;

[0008] Step 2: At time t0, the detection circuit detects whether V in > V hd . If yes, go to the next step. If no, loop and execute Step 2;

[0009] Step 3: At time t2, the detection circuit detects whether v out (k + 1)> v out (k), that is, the signal processing circuit detects a higher peak voltage. If yes, go to the next step. If no, go to Step 6;

[0010] Step 4: The MCU determines whether CNT> kCNT_MAX (0 <k <1, CNT_MAX is the maximum value of the counter). If yes, go to the next step. If no, go to Step 6;

[0011] Step 5: Set CNT to the specified value CNT_SET, CNT = CNT_SET, CNT_SET <kCNT_MAX; the counter counts from CNT_SET to CNT_MAX, and the time t rel required for this process should be at least greater than the conversion period t tf of one ADC;

[0012] Step 6: Continue to execute CNT increment by 1, CNT = CNT + 1;

[0013] Step 7: The MCU determines whether CNT = CNT_MAX. If yes, go to the next step. If no, go to Step 6;

[0014] Step 8: When CNT is equal to CNT_MAX, trigger DISC, turn on Q2 and Q1, discharge C1 and C2, and wait for the next charging signal.

[0015] Advantages of the present invention:

[0016] 1. The collected data is accurate and there will be no data loss due to the asynchronous acquisition method;

[0017] 2. The algorithm has strong adaptability. When replacing the AD conversion chip, only a small number of algorithm parameters need to be changed. Description of the Drawings

[0018] Figure 1 is a typical topology diagram of the existing maximum peak sampling circuit;

[0019] Figure 2 is a typical sampling timing schematic diagram of the existing maximum peak sampling circuit;

[0020] Figure 3 This is a novel topology diagram of the maximum peak sampling circuit in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the novel sampling timing of the maximum peak sampling circuit according to an embodiment of the present invention;

[0022] Figure 5 This is a logic flowchart of the control method for the maximum peak detection circuit in an embodiment of the present invention. Detailed Implementation

[0023] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0024] by Figure 1 , Figure 2 Taking this as an example, briefly describe the typical topology, typical sampling timing, and working mode of the existing maximum peak sampling circuit.

[0025] Figure 1 In the diagram, C1: Sample and hold capacitor;

[0026] D: Diode;

[0027] Q1: Electronic switching transistor;

[0028] P1: Voltage comparator;

[0029] ADC: AD conversion chip, that is, analog-to-digital converter;

[0030] MCU: Microcontroller Unit;

[0031] HOLD: The sampling capacitor holds the signal; Q1 is off when the signal is high.

[0032] DISC: Samples the capacitor discharge signal; Q1 is in the on state when it is high.

[0033] GND: 0 potential reference point;

[0034] Input voltage V in The signal being collected;

[0035] V hd The voltage holding threshold can be customized.

[0036] V out This represents the maximum peak voltage collected.

[0037] At time t0, the system detected V in >V hdWhen the MCU receives the HOLD signal, it sets the DISC discharge signal to low level, and the sample-and-hold capacitor C1 starts sampling the input voltage. At the same time, the counter CNT in the MCU starts counting. When the count reaches the maximum value of CNT_MAX, the MCU pulls the DISC discharge signal high, and the sample-and-hold capacitor C1 discharges, waiting for the next acquisition.

[0038] Figure 2 In the middle, t acq The data acquisition time of the ADC is determined by the ADC chip model;

[0039] t conv The data conversion time of an ADC is determined by the ADC chip model.

[0040] t hold Peak hold capacitor duration can be customized.

[0041] CNT: MCU internal counter (time) value, which can be customized;

[0042] CNT_MAX: The maximum value of the internal counter (time) of the MCU. CNT will automatically return to zero after reaching this value. It can be customized.

[0043] t0: The time when the input voltage reaches the voltage hold-on threshold;

[0044] t1: The moment when the input voltage reaches its peak value;

[0045] t2: The start time of the next pulse;

[0046] t3: The time when the next pulse reaches its peak value;

[0047] t4: Peak hold capacitor discharge time.

[0048] AD conversion chip in t acq Voltage information is collected from external circuits during the period, at t conv During this period, the connection to the external circuit is disconnected, and t acq The voltage information collected during this period is converted into digital values ​​and sent to the MCU. At time t3, the ADC is in state t. conv period, Figure 1 The acquisition circuit shown acquired data appearing at t. hold The maximum peak value during the period, such as in this t conv If the MCU counter counts to CNT_MAX, the sampling holding capacitor C1 will discharge. The ADC will fail to convert the maximum peak value into a digital value and send it to the MCU, resulting in the MCU receiving an incorrect maximum peak voltage.

[0049] like Figure 3The diagram shown is a novel topology diagram of the maximum peak sampling circuit according to an embodiment of the present invention.

[0050] Figure 3 In the diagram, C1 and C2 are the sample-and-hold capacitors.

[0051] Q1, Q2, Q3: Electronic switching transistors;

[0052] CNT_SET: Counter set signal;

[0053] Taking NPN transistors Q1, Q2, and Q3 as an example, the connection relationship of each component is briefly described. To ensure sampling accuracy, C1 and C2 should be mica capacitors or film capacitors (non-polarized) with low capacitance and high voltage rating as much as possible.

[0054] Input voltage V in The signal being acquired is input voltage V. in The diode D is connected to its anode; the positive input of voltage comparator P1 is connected to the cathode of diode D, and the negative input voltage is the voltage holding threshold (fixed voltage) V. hd The output terminal sends the sampling capacitor hold signal HOLD (active high) to the MCU; C1 is connected in parallel with Q1, the collector of Q1 is connected to the cathode of diode D and the input terminal of the ADC, and the emitter is grounded; C2 is connected in parallel with Q2, the collector of Q2 is connected to the emitter of Q3 and the signal processing circuit, and the emitter of Q2 is grounded; the signal processing circuit is connected to the MCU; the collector of Q3 is connected to the cathode of diode D, and the base of Q3 is a high-frequency clock pulse signal; the bases of Q2 and Q1 are both connected to the MCU and controlled by the DISC signal. When the HOLD signal is high, the DISC signal is low, and the voltage across C1 and C2 is the same as V. in When the MCU counter reaches CNT_MAX, DISC goes high, and C1 and C2 discharge. The signal processing circuit is existing technology, mainly composed of an operational amplifier and a voltage comparator. Its function is to compare the voltages on C1 and C2, amplify the comparison result, and determine whether to send the CNT_SET command to the MCU based on the amplified voltage difference.

[0055] like Figure 4 The diagram shown is a novel sampling timing diagram of the maximum peak sampling circuit according to an embodiment of the present invention.

[0056] Figure 4 In the middle, t tf : ADC single analog-to-digital conversion time; f tf It is the ADC analog-to-digital conversion frequency, and the two are reciprocals of each other.

[0057] t rel MCU counter delay duration; customizable.

[0058] t5: Moment when DISC is at high level after delay.

[0059] Take Figure 3 , Figure 4 as an example to illustrate this technical solution. At time t0, the system detects that V in >V hd . The MCU receives the HOLD signal and sets the DISC signal to low level. The sample and hold capacitors C1 and C2 start to sample the input voltage, and at the same time, the counter (CNT) in the MCU starts counting from 0. Q3 is an electronic switch driven by a clock pulse, and its switching frequency is much higher than the ADC analog-to-digital conversion frequency f tf . The voltage value of the sample and hold capacitor C2 is equal to the voltage value of C1 at the current moment (when Q3 is on) or the voltage value of C1 at the previous moment (when Q2 is off).

[0060] As Figure 5 shown, it is the logic flow chart of the control method of the maximum peak detection circuit in an embodiment of the present invention. Figure 5 In it, k: Delay coefficient, 0 < k < 1. By changing this value, the delay duration of the MCU counter can be changed.

[0061] At time t2, the signal processing circuit detects a higher peak voltage, that is, v out (k + 1)>v out (k). At the same time, the MCU judges whether CNT is greater than kCNT_MAX (0 < k < 1, CNT_MAX is the maximum value of the counter). If CNT > kCNT_MAX, CNT is set to a specified value (CNT_SET), and CNT_SET should be less than kCNT_MAX. The counter starts counting from CNT_SET to CNT_MAX, and the time t rel required for this process should be at least greater than the conversion period t tf of one ADC. Conversely, if CNT

Claims

1. A maximum peak detection circuit, comprising: Diode D, sample-and-hold capacitor C1, electronic switch Q1, voltage comparator P1, ADC chip, and microcontroller unit (MCU) are electrically connected, with input voltage V. in The signal to be acquired is characterized by further including electronic switching transistors Q3 and Q2, a sample-and-hold capacitor C2, and a signal processing circuit, with an input voltage V. in The anode of diode D is connected to the diode, and the positive input of voltage comparator P1 is connected to the cathode of diode D. The input voltage at the negative input of voltage comparator P1 is the voltage holding threshold voltage V. hd The output of voltage comparator P1 outputs a sampling and holding signal HOLD, which is sent to the microcontroller unit (MCU). Electronic switch Q1 is connected in parallel with sampling and holding capacitor C1. The collector of electronic switch Q1 is connected to the cathode of diode D and the input of the AD converter chip (ADC). The emitter of electronic switch Q1 is grounded. Sampling and holding capacitor C2 is connected in parallel with electronic switch Q2. The collector of electronic switch Q2 is connected to the emitter of electronic switch Q3 and the signal processing circuit. The emitter of electronic switch Q2 is grounded. The signal processing circuit is connected to the MCU. The collector of electronic switch Q3 is connected to the cathode of diode D. The base of electronic switch Q3 is a high-frequency clock pulse signal. The bases of both electronic switches Q2 and Q1 are connected to the MCU. The signal processing circuit receives the maximum peak voltage V acquired. out The voltage across the sample-and-hold capacitor C1 and the sample-and-hold capacitor C2 is compared, and the comparison result is amplified. Based on the amplified voltage difference, it is determined whether to send the CNT_SET command to the microcontroller unit (MCU).

2. The maximum peak detection circuit according to claim 1, characterized in that, Electronic switching transistors Q1, Q2, and Q3 are NPN transistors, and sample-and-hold capacitors C1 and C2 are mica capacitors or film capacitors.

3. A control method for a maximum peak detection circuit, characterized in that, The application of the maximum peak detection circuit as described in claim 1 includes the following steps: Step 1: Initialize control parameters, k: delay coefficient, 0 <k<1,CNT=0,DISC=0; Step 2, at time t0, the detection circuit checks whether V... in >V hd If yes, proceed to the next step; otherwise, repeat step 2. Step 3, at time t2, the detection circuit checks whether v out (k+1)>v out (k), if yes, proceed to the next step; if no, proceed to step 6; Step 4: The microcontroller unit (MCU) determines whether CNT > kCNT_MAX, where CNT_MAX is the maximum value of the counter. If yes, proceed to the next step; otherwise, proceed to step 6. Step 5: Set CNT to the specified value CNT_SET, CNT = CNT_SET, CNT_SET <kCNT_MAX; Step 6: Continue incrementing CNT by 1, CNT = CNT + 1; Step 7: The microcontroller unit (MCU) determines whether CNT = CNT_MAX. If yes, proceed to the next step; otherwise, proceed to step 6. Step 8: When CNT equals CNT_MAX, DISC is triggered, turning on electronic switches Q2 and Q1, discharging sample-and-hold capacitors C1 and C2, and waiting for the next charging signal.

4. The control method for a maximum peak detection circuit according to claim 3, characterized in that, In step 5, the counter counts from CNT_SET to CNT_MAX, and the time required for this process is t. rel It should be at least greater than the conversion period t of one ADC chip. tf ; t tf : ADC single-transformation time of the AD conversion chip; t rel The delay duration of the microcontroller unit (MCU) counter or timer.

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