An encapsulation method and an encapsulated body

Abstract

The present application discloses a packaging method and a package body. The processing method includes: obtaining a to-be-processed board; wherein, the to-be-processed board includes a plurality of separated pads; mounting a chip on one of the pads; welding a wire on the surface of the chip away from the pad; after pressing the insulating material with the copper substrate, the chip and the wire, grinding the insulating material to form a first insulating dielectric layer; forming a first blind hole in the pads surrounding the pad with the mounted chip; performing a full-board electroplating on the to-be-processed board to form a first connection post in the first blind hole and a first conductive circuit on the surface of the first insulating dielectric layer away from the copper substrate; wherein, the first conductive circuit covers the top of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate. The present application solves the problem that the aluminum pins of the chip cannot be directly processed in the PLFO process.

Description

Technical Field

[0001] The present application relates to the technical field of package processing, and particularly to a packaging method and a package. Background Art

[0002] With the development of 5G technology, the functions of electronic products are becoming more and more comprehensive, and the volume is getting smaller and smaller. As a result, the requirements for packages are getting higher and higher, driving the PCB industry to develop in the direction of high density, high integration, and multi-layer. Mosfet (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) are almost applied to all power industrial products, and power devices are developing towards high performance, fast speed, small volume, and multi-chip connection packaging.

[0003] In the prior art, the PLFO (Panel level Fan-out) is usually used to package chips. In the PLFO process, the chip is usually soldered to a bottom pad. If the interconnection between the chip and the substrate is to be realized, a small blind hole needs to be provided above one side of the chip away from the bottom pad, and a large blind hole needs to be provided on another bottom pad close to the chip, and copper is plated in the blind holes to achieve electrical interconnection through the blind hole interconnection.

[0004] However, if the material of the chip pins is aluminum, since the melting point of aluminum is relatively low and the chemical formation is relatively active, the PLFO process involves the problem of modifying the chip pins, that is, the aluminum pins need to be modified in advance to avoid damage to the aluminum pins caused by high temperature and corrosive liquids during the formation of the blind holes. Summary of the Invention

[0005] The main technical problem to be solved by the present application is to provide a packaging method and a package, which can solve the problem that the aluminum pins of the chip cannot be directly processed in the prior art.

[0006] To solve the above technical problems, the first technical solution adopted by this application is to provide a packaging method, including: obtaining a to-be-processed board; wherein, the to-be-processed board is a patterned copper substrate, and the copper substrate includes a plurality of separated pads; obtaining a chip and mounting the chip on one of the pads; welding a wire on the surface of the chip away from the pad; obtaining an insulating material, pressing the insulating material together with the copper substrate, the chip, and the wire, and then grinding the insulating material to form a first insulating dielectric layer; wherein, the first insulating dielectric layer is located around the wire and covers the surface of the copper substrate in contact with the chip and the surface of the chip away from the copper substrate; processing a first preset position of the first insulating dielectric layer until one surface of the copper substrate is exposed, so as to form a first blind hole on the pads around the pad with the mounted chip; performing full-panel electroplating on the to-be-processed board with the first blind hole formed thereon to form a first connection post in the first blind hole and a first conductive circuit on the surface of the first insulating dielectric layer away from the copper substrate; wherein, the first conductive circuit covers the top of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

[0007] Among them, the step of obtaining a chip and mounting the chip on one of the pads specifically includes: coating a conductive adhesive on one surface of the pad and mounting the chip on the conductive adhesive.

[0008] Among them, the step of welding a wire on the surface of the chip away from the pad specifically includes: welding the wire on the surface of the chip away from the pad by means of wire bonding.

[0009] Among them, the step of obtaining an insulating material, pressing the insulating material together with the copper substrate, the chip, and the wire, and then grinding the insulating material to form a first insulating dielectric layer specifically includes: obtaining an insulating material, pressing the insulating material together with the copper substrate, the chip, and the wire so that the insulating material covers the surface of the copper substrate in contact with the chip, the surface of the chip away from the copper substrate, and the top of the wire away from the chip; grinding the insulating material until the top of the wire away from the chip is exposed to form a first insulating dielectric layer; wherein, the first insulating dielectric layer is located around the wire and covers the surface of the copper substrate in contact with the chip and the surface of the chip away from the copper substrate.

[0010] Among them, before the step of performing full-panel electroplating on the to-be-processed board with the first blind hole formed thereon to form a first connection post in the first blind hole and a first conductive circuit on the surface of the first insulating dielectric layer away from the copper substrate, it further includes: forming a conductive seed layer on the surface of the first insulating dielectric layer away from the copper substrate and on the hole wall of the first blind hole by means of electroless copper plating.

[0011] Among them, the steps of performing full-panel electroplating on the to-be-processed board with the first blind hole formed therein to form the first connection post in the first blind hole and form the first conductive circuit on the surface of the first insulating dielectric layer away from the copper substrate specifically include: performing full-panel electroplating on the to-be-processed board with the first blind hole formed therein to form the first connection post in the first blind hole and form the first conductive layer on the surface of the first insulating dielectric layer away from the copper substrate; attaching the first dry film on the first conductive layer and exposing the second preset position on the first conductive layer; etching the first conductive layer to form the first conductive circuit on the first conductive layer; among them, the first conductive circuit covers the top of the side of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

[0012] Among them, after the step of etching the first conductive layer to form the first conductive circuit on the first conductive layer, it further includes: obtaining an insulating material, and laminating the insulating material with the surface of the first conductive circuit away from the first insulating dielectric layer and the surface of the first insulating dielectric layer away from the copper substrate to form the second insulating dielectric layer.

[0013] Among them, the insulating material includes one or more of epoxy resin type, phenolic resin type, polyimide type, BT type, ABF type, and ceramic matrix type.

[0014] To solve the above technical problems, the second technical solution adopted by the present application is to provide a package, including: a patterned copper substrate, the copper substrate includes a plurality of separated pads; a chip, the chip is disposed on one of the pads; a wire, the wire is disposed on the surface of the chip away from the copper substrate; a first insulating dielectric layer, the first insulating dielectric layer is located around the wire and covers the surface of the copper substrate in contact with the chip and the surface of the chip away from the copper substrate; a first blind hole, the first blind hole is disposed on the surrounding pads of the pad with the chip attached; a first connection post, the first connection post is disposed in the first blind hole; a first conductive circuit, the first conductive circuit covers the top of the side of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

[0015] Among them, the package further includes a second insulating dielectric layer, and the second insulating dielectric layer is disposed on the surface of the first conductive circuit away from the first insulating dielectric layer and the surface of the first insulating dielectric layer away from the copper substrate.

[0016] The beneficial effects of the present application are as follows: Different from the prior art, the present application provides a packaging method and a package. By welding the wire on the surface of the chip away from the pad, blind holes can be avoided on the chip pins, and since the wire bonding method does not require high temperature or electroplating, the chip pins do not need to be modified, thus solving the problem that the aluminum pins of the chip cannot be directly processed in the PLFO process. Further, since the wire is interconnected with the first blind hole through the first conductive line instead of through a wire arc, the increase in the overall height of the device caused by the wire arc is avoided, thereby realizing the miniaturization and thinness of the packaged device. Brief Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 is a schematic flowchart of an embodiment of the packaging method of the present application;

[0019] Figure 2 is a schematic structural diagram of a to-be-processed sheet obtained in S11 in one embodiment;

[0020] Figure 3 is a schematic structural diagram of a to-be-processed sheet obtained in S12 in one embodiment;

[0021] Figure 4 is a schematic structural diagram of a to-be-processed sheet obtained in S13 in one embodiment;

[0022] Figure 5 is a schematic structural diagram of a to-be-processed sheet obtained in S14 in one embodiment;

[0023] Figure 6 is a schematic structural diagram of a to-be-processed sheet obtained in S15 in one embodiment;

[0024] Figure 7 is Figure 1 a schematic flowchart of a specific embodiment in S16;

[0025] Figure 8 is a schematic structural diagram of a to-be-processed sheet obtained in S161 in one embodiment;

[0026] Figure 9 is a schematic structural diagram of a to-be-processed sheet obtained in S163 in one embodiment;

[0027] Figure 10It is a schematic structural diagram of an embodiment of the package of the present application. Specific Embodiment

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0029] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless clearly stated otherwise in the foregoing. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0030] It should be understood that the term "and / or" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0031] It should be understood that the term "comprising", "including" or any other variant used herein is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0032] In the prior art, the PLFO (Panel level Fan-out) is usually used to package chips. In the PLFO process, the chip is usually soldered on a bottom pad. If the interconnection between the chip and the substrate is to be realized, a small blind hole needs to be set above the side of the chip far from the bottom pad, and a large blind hole needs to be set on another bottom pad close to the chip, and copper is plated in the blind hole to realize electrical interconnection through the blind hole interconnection. However, if the material of the chip pins is aluminum, since the melting point of aluminum is relatively low and the chemical formation is relatively active, the PLFO process involves the problem of modifying the chip pins, that is, the aluminum pins need to be modified in advance to avoid damage to the aluminum pins caused by high temperature and corrosive liquid during the formation of the blind hole.

[0033] Based on the above situation, the present application provides a packaging method and a package, which can solve the problem that the aluminum pins of the chip in the prior art cannot be directly processed.

[0034] The present application will be described in detail below with reference to the drawings and embodiments.

[0035] Please refer to Figure 1 , Figure 1 which is a schematic flow chart of an embodiment of the packaging method of the present application.

[0036] As Figure 1 shown, in this embodiment, the method includes:

[0037] S11: Obtain a to-be-processed plate; wherein, the to-be-processed plate is a patterned copper substrate, and the copper substrate includes a plurality of separated pads.

[0038] In this embodiment, first, a complete copper substrate is obtained, and then the copper substrate is etched by chemical etching or physical etching to form a circuit pattern on the copper substrate, and the patterned copper substrate includes a plurality of separated pads. For the convenience of description, the copper substrate mentioned below refers to the patterned copper substrate.

[0039] Specifically, please refer to Figure 2 , Figure 2 which is a schematic structural diagram of an embodiment of the to-be-processed plate obtained in S11. As Figure 2 shown, the to-be-processed plate 100 includes separated first pads 10 and second pads 20.

[0040] In this embodiment, the edges of the first pads 10 and the second pads 20 are flat, but in actual etching, due to side etching, there are often some protrusions at the edges of the first pads 10 and the second pads 20.

[0041] S12: Obtain a chip and mount the chip on one of the pads.

[0042] In this embodiment, a conductive adhesive is coated on one surface of the pad, and the chip is mounted on the conductive adhesive.

[0043] Among them, the conductive adhesive can be substances such as solder paste and silver paste.

[0044] Specifically, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of an embodiment of the to-be-processed plate obtained in S12. As Figure 3 shown, the to-be-processed plate 200 includes separated first pads 10 and second pads 20. A chip 30, the chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11.

[0045] S13: Weld the wire on the surface of the chip on the side far from the pad.

[0046] In this embodiment, the wire is welded on the surface of the chip on the side far from the pad by means of wire bonding.

[0047] Specifically, wire bonding is a process that uses a thin metal wire and utilizes heat, pressure or ultrasonic energy to tightly bond the metal lead to the substrate pad, thereby realizing the electrical interconnection between the chip and the substrate and the information communication between chips. Under ideal control conditions, electron sharing or atomic interdiffusion occurs between the lead and the substrate, thereby achieving atomic-level bonding between the two metals.

[0048] According to different bonding conditions, bonding can be divided into thermocompression bonding, cold ultrasonic bonding and thermosonic bonding. According to different leads, it can be further divided into gold wire, copper wire or aluminum wire bonding, etc. Among them, cold ultrasonic bonding is often aluminum wire wedge bonding, and thermosonic bonding is often gold wire ball bonding. Because it uses both thermocompression and ultrasonic energy, it can achieve better bonding quality at a lower temperature.

[0049] It can be understood that different from the relatively high heat required for drilling blind holes in the prior art, this embodiment adopts the wire bonding method to wedge the wire into one side surface of the chip at a lower temperature, thereby avoiding the melting of the aluminum pins on the chip surface due to high temperature. And since the wire is a metal wire, there is no need for copper plating operation, which can also avoid the corrosion of the aluminum pins. Therefore, there is no need to modify the chip aluminum pins, solving the problem that the chip aluminum pins cannot be directly processed in the PLFO process.

[0050] Furthermore, due to the small wire diameter of the wire, when performing the wire bonding process, it can also be not restricted by problems such as the small process window for blind hole processing above the chip.

[0051] In other embodiments, when the surface material of the chip is copper, silver, nickel gold or nickel palladium gold, the wire can also be welded on the surface of the chip on the side far from the pad by means of wire bonding, and this application does not make any limitations in this regard.

[0052] Specifically, please refer to Figure 4 , Figure 4 is a schematic structural diagram of an embodiment of the to-be-processed sheet obtained in S13. As Figure 4 shown, the to-be-processed sheet 300 includes a separated first pad 10 and a second pad 20. The chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11. The wire 31 is disposed on the surface of the chip 30 on the side far from the first pad 10.

[0053] S14: Obtain an insulating material. After laminating the insulating material with a copper substrate, a chip, and a wire, grind the insulating material to form a first insulating dielectric layer; wherein, the first insulating dielectric layer is located around the wire and covers one surface of the copper substrate in contact with the chip and one surface of the chip away from the copper substrate.

[0054] In this embodiment, an insulating material is obtained, and the insulating material is laminated with a copper substrate, a chip, and a wire so that the insulating material covers one surface of the copper substrate in contact with the chip, one surface of the chip away from the copper substrate, and the top end of the wire away from the chip.

[0055] Further, grind the insulating material until the top end of the wire away from the chip is exposed to form a first insulating dielectric layer. It can be understood that the first insulating dielectric layer can encapsulate and protect the chip.

[0056] In this embodiment, the insulating material includes one or more of epoxy resin types, phenolic resin types, polyimide types, BT types, ABF types, and ceramic-based types, and the present application does not limit this.

[0057] Specifically, please refer to Figure 5 , Figure 5 which is a schematic structural diagram of an embodiment of the to-be-processed sheet obtained in S14. As Figure 5 shown, the to-be-processed sheet 400 includes a separated first pad 10 and second pad 20. A chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11. A wire 31 is disposed on a surface of the chip 30 away from the first pad 10. A first insulating dielectric layer 40 is located around the wire 31 and covers one surface of the first pad 10 in contact with the chip 30, one surface of the chip 30 away from the first pad 10, one surface of the second pad 20, and the separated area between the first pad 10 and the second pad 20.

[0058] S15: Process a first preset position of the first insulating dielectric layer until one surface of the copper substrate is exposed to form a first blind via on the surrounding pads of the pad with the chip mounted thereon.

[0059] In this embodiment, the surface of the first preset position of the first insulating dielectric layer is treated by chemical etching or physical etching to form a first blind via on the surrounding pads of the pad with the chip mounted thereon.

[0060] Among them, the first preset position includes the first blind via and the peripheral position of the via opening. In other embodiments, the first preset position may also only include the position of the first blind via, and the present application does not limit this.

[0061] Specifically, please refer to Figure 6 , Figure 6 which is a schematic structural diagram of an embodiment of the to-be-processed sheet obtained in S15. As Figure 6 shown, the to-be-processed sheet 500 includes a separated first pad 10 and a second pad 20. A chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11. A wire 31 is disposed on a surface of the chip 30 away from the first pad 10. A first insulating dielectric layer 40 is located around the wire 31 and covers a surface of the first pad 10 in contact with the chip 30, a surface of the chip 30 away from the first pad 10, a surface of the second pad 20, and a separated area between the first pad 10 and the second pad 20. A first blind hole 41 is disposed on the second pad 20.

[0062] S16: Perform full-panel electroplating on the to-be-processed sheet formed with the first blind hole to form a first connection column in the first blind hole and a first conductive circuit on a surface of the first insulating dielectric layer away from the copper substrate; wherein, the first conductive circuit covers a top of the wire away from the chip and the first connection column for realizing the interconnection between the chip and the copper substrate.

[0063] In this embodiment, before performing full-panel electroplating on the to-be-processed sheet, a conductive seed layer is formed on a surface of the first insulating dielectric layer away from the copper substrate and on a pore wall of the first blind hole by means of electroless copper plating.

[0064] In another embodiment, a conductive seed layer can also be formed on a surface of the first insulating dielectric layer away from the copper substrate and on a pore wall of the first blind hole by means of carbon adsorption such as black hole, black shadow or graphene oxide.

[0065] In yet another embodiment, a conductive seed layer can also be formed on a surface of the first insulating dielectric layer away from the copper substrate and on a pore wall of the first blind hole by means of coating with a conductive polymer.

[0066] Specifically, please refer to Figure 7 , Figure 7 which is Figure 1 a schematic flow diagram of a specific embodiment of S16 in Figure 7 As shown, in this embodiment, the steps of performing full-panel electroplating on the to-be-processed sheet formed with the first blind hole to form a first connection column in the first blind hole and a first conductive circuit on a surface of the first insulating dielectric layer away from the copper substrate; wherein, the first conductive circuit covers a top of the wire away from the chip and the first connection column for realizing the interconnection between the chip and the copper substrate specifically include:

[0067] S161: Electroplate the entire plate of the to-be-processed board with a first blind via formed thereon to form a first connection post in the first blind via and a first conductive layer on the surface of the first insulating dielectric layer away from the copper substrate.

[0068] Specifically, please refer to Figure 8 , Figure 8 which is a schematic structural diagram of an embodiment of the to-be-processed board obtained in S161. As Figure 8 shown, the to-be-processed board 600 includes a separated first pad 10 and a second pad 20. A chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11. A wire 31 is disposed on the surface of the chip 30 away from the first pad 10. A first insulating dielectric layer 40 is located around the wire 31 and covers the surface of the first pad 10 in contact with the chip 30, the surface of the chip 30 away from the first pad 10, the surface of the second pad 20, and the separated area between the first pad 10 and the second pad 20. A first blind via 41 is disposed on the second pad 20. A first connection post 42 is disposed in the first blind via 41. A first conductive layer 50 is disposed on the surface of the first insulating dielectric layer 40 away from the first pad 10 and covers the top of the wire 31 away from the chip 30 and the surface of the first connection post 42 away from the second pad 20.

[0069] S162: Attach a first dry film to the first conductive layer and expose a second preset position on the first conductive layer.

[0070] In this embodiment, the second preset position is the position on the to-be-processed board where conductive lines do not need to be fabricated.

[0071] Among them, the first dry film is an anti-etching photosensitive film. The anti-etching photosensitive film is a kind of high-molecular compound, which can produce a polymerization reaction (the reaction process of synthesizing polymers from monomers) after being irradiated by a specific light source to form a stable substance attached to the board surface, thereby achieving the function of blocking etching.

[0072] S163: Etch the first conductive layer to form a first conductive line on the first conductive layer; among them, the first conductive line covers the top of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

[0073] It can be understood that since the wire is interconnected with the first blind via through the first conductive line instead of through a wire arc, the increase in the overall height of the device caused by the wire arc is avoided, thereby realizing the miniaturization and thinness of the packaged device.

[0074] Understandably, the electrical interconnection of the chip is achieved through the first conductive line, and the heat dissipation of the chip can also be enhanced, thereby improving the heat dissipation effect of the overall device.

[0075] Specifically, please refer to Figure 9 , Figure 9 which is a schematic structural diagram of an embodiment of the to-be-processed sheet obtained in S163. As Figure 9 shown, the to-be-processed sheet 700 includes a separated first pad 10 and a second pad 20. A chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11. A wire 31 is disposed on a surface of the chip 30 away from the first pad 10. A first insulating dielectric layer 40 is located around the wire 31 and covers a surface of the first pad 10 in contact with the chip 30, a surface of the chip 30 away from the first pad 10, a surface of the second pad 20, and a separated area between the first pad 10 and the second pad 20. A first blind hole 41 is disposed on the second pad 20. A first connecting post 42 is disposed in the first blind hole 41. A first conductive line 51 is disposed on a surface of the first insulating dielectric layer 40 away from the first pad 10, and covers a top of the wire 31 away from the chip 30 and the first connecting post 42, for realizing the interconnection between the chip 30 and the second pad 20.

[0076] In this embodiment, in order to protect the first conductive line, a second insulating dielectric layer is further disposed on the first conductive line. Specifically, an insulating material is obtained, and the insulating material is pressed against a surface of the first conductive line away from the first insulating dielectric layer and a surface of the first insulating dielectric layer away from the copper substrate to form the second insulating dielectric layer.

[0077] Among them, the insulating material includes one or more of epoxy resin, phenolic resin, polyimide, BT, ABF, and ceramic matrix, and the present application does not limit this.

[0078] Different from the prior art, in this embodiment, by welding the wire on a surface of the chip away from the pad, blind holes can be avoided from being formed on the chip pins, and since the wire bonding method does not require a high temperature nor electroplating, the chip pins do not need to be modified, thus solving the problem that the chip aluminum pins in the PLFO process cannot be directly processed. Further, since the wire is interconnected with the first blind hole through the first conductive line instead of through a wire arc, the increase in the height of the overall device caused by the wire arc is avoided, thereby realizing the miniaturization and thinness of the packaged device.

[0079] Correspondingly, the present application provides a package.

[0080] Specifically, please refer to Figure 10 , Figure 10 which is a schematic structural diagram of an embodiment of the package of the present application.

[0081] As Figure 10 shown, the package 800 includes a separated first pad 10 and a second pad 20. A chip 30 is disposed on the first pad 10. Among them, the chip 30 is bonded to the first pad 10 through a conductive adhesive 11. A wire 31 is disposed on a surface of the chip 30 away from the first pad 10. A first insulating dielectric layer 40 is located around the wire 31 and covers a surface of the first pad 10 in contact with the chip 30, a surface of the chip 30 away from the first pad 10, a surface of the second pad 20, and a separated area between the first pad 10 and the second pad 20. A first blind hole 41 is disposed on the second pad 20. A first connection post 42 is disposed in the first blind hole 41. A first conductive line 51 is disposed on a surface of the first insulating dielectric layer 40 away from the first pad 10 and covers a top of the wire 31 away from the chip 30 and the first connection post 42 for realizing the interconnection between the chip 30 and the second pad 20. A second insulating dielectric layer 60 is disposed on a surface of the first conductive line 51 away from the first insulating dielectric layer 40 and on a surface of the first insulating dielectric layer 40 away from the first pad 10.

[0082] Different from the prior art, the package provided by this embodiment realizes electrical interconnection by wedging a wire above the chip, which can avoid forming blind holes on the chip pins. And since the wire bonding method does not require a high temperature nor electroplating, there is no need to modify the chip pins, thus solving the problem that the aluminum pins of the chip cannot be directly processed in the PLFO process. Further, since the wire is interconnected with the first blind hole through the first conductive line instead of through a wire arc, it avoids the wire arc from increasing the height of the overall device, thereby realizing the miniaturization and thinness of the packaged device.

[0083] The above are only embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A packaging method, characterized in that, Including: Obtaining a to-be-processed board; wherein, the to-be-processed board is a patterned copper substrate, and the copper substrate includes a plurality of separated pads; Obtaining a chip and mounting the chip on one of the pads; Welding a wire on a surface of the chip away from the pad, including: welding the wire on the surface of the chip away from the pad by using a wire bonding method; Obtaining an insulating material, laminating the insulating material with the copper substrate, the chip, and the wire, and then grinding the insulating material to form a first insulating dielectric layer; wherein, the first insulating dielectric layer is located around the wire and covers a surface of the copper substrate in contact with the chip and a surface of the chip away from the copper substrate; Processing a first preset position of the first insulating dielectric layer until a surface of the copper substrate is exposed, so as to form a first blind via in the pads around the pad on which the chip is mounted; Performing full-panel electroplating on the to-be-processed board having the first blind via, so as to form a first connection post in the first blind via and a first conductive circuit on a surface of the first insulating dielectric layer away from the copper substrate; wherein, the first conductive circuit covers a top of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

2. The encapsulation method according to claim 1, wherein The step of obtaining a chip and mounting the chip on one of the pads specifically includes: Coating a conductive adhesive on a surface of the pad and mounting the chip on the conductive adhesive.

3. The encapsulation method according to claim 1, characterized in that The step of obtaining an insulating material, laminating the insulating material with the copper substrate, the chip, and the wire, and then grinding the insulating material to form a first insulating dielectric layer specifically includes: Obtaining the insulating material, laminating the insulating material with the copper substrate, the chip, and the wire, so that the insulating material covers a surface of the copper substrate in contact with the chip, a surface of the chip away from the copper substrate, and a top end of the wire away from the chip; Grinding the insulating material until the top end of the wire away from the chip is exposed, so as to form the first insulating dielectric layer; wherein, the first insulating dielectric layer is located around the wire and covers a surface of the copper substrate in contact with the chip and a surface of the chip away from the copper substrate.

4. The encapsulation method according to claim 1, characterized in that, Before the step of performing full-panel electroplating on the to-be-processed board having the first blind via, so as to form a first connection post in the first blind via and a first conductive circuit on a surface of the first insulating dielectric layer away from the copper substrate, it further includes: Forming a conductive seed layer on a surface of the first insulating dielectric layer away from the copper substrate and on a pore wall of the first blind via by using electroless copper plating.

5. The encapsulation method according to claim 4, characterized in that The step of performing full-panel electroplating on the to-be-processed board having the first blind via, so as to form a first connection post in the first blind via and a first conductive circuit on a surface of the first insulating dielectric layer away from the copper substrate specifically includes: The entire plate of the to-be-processed sheet material formed with the first blind hole is electroplated to form the first connection post in the first blind hole and form a first conductive layer on the surface of the first insulating dielectric layer away from the copper substrate; Attach a first dry film on the first conductive layer and expose the second preset position on the first conductive layer; Etch the first conductive layer to form the first conductive circuit on the first conductive layer; wherein, the first conductive circuit covers the top of the side of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

6. The encapsulation method according to claim 5, wherein After the step of etching the first conductive layer to form the first conductive circuit on the first conductive layer, it further includes: Obtain the insulating material, and press the insulating material against the surface of the first conductive circuit away from the first insulating dielectric layer and the surface of the first insulating dielectric layer away from the copper substrate to form a second insulating dielectric layer.

7. The encapsulation method according to claim 6, characterized in that The insulating material includes one or more of epoxy resin type, phenolic resin type, polyimide type, BT type, ABF type, and ceramic matrix type.

8. An encapsulation body, characterized in that, It includes: A patterned copper substrate, the copper substrate includes a plurality of separated pads; A chip, the chip is disposed on one of the pads; A wire, the wire is disposed on the surface of the chip away from the copper substrate; the wire is welded to the surface of the chip by wire bonding; A first insulating dielectric layer, the first insulating dielectric layer is located around the wire and covers the surface of the copper substrate in contact with the chip and the surface of the chip away from the copper substrate; A first blind hole, the first blind hole is disposed on the surrounding pads of the pad with the chip attached; A first connection post, the first connection post is disposed in the first blind hole; A first conductive circuit, the first conductive circuit covers the top of the side of the wire away from the chip and the first connection post, and is used to realize the interconnection between the chip and the copper substrate.

9. The package according to claim 8, wherein, The package further includes a second insulating dielectric layer, the second insulating dielectric layer is disposed on the surface of the first conductive circuit away from the first insulating dielectric layer and the surface of the first insulating dielectric layer away from the copper substrate.

Images