Camera device and method for obtaining gain ratio in camera device

Abstract

The purpose of this invention is to reduce the time required for calibration between the gains of a level adjustment circuit. The level adjustment circuit adjusts the level of analog signals output to vertical signal lines corresponding to columns of a pixel array using either a first gain or a second gain that are different from each other. An analog-to-digital converter converts the level-adjusted analog signals into digital signals. A test signal generation unit generates a first test signal and a second test signal that are different from each other. A gain ratio acquisition unit simultaneously supplies the first test signal to one of the vertical signal lines and the second test signal to the other vertical signal line, thereby acquiring the gain ratio between the first gain and the second gain of the level adjustment circuit.

Description

Technical Field

[0001] This technology relates to imaging elements. More specifically, this technology relates to a calibration technique between gains in a level adjustment circuit within an imaging element. Background Technology

[0002] In recent years, to improve the noise of image readout circuits, adaptive gain control (AGC) has been used in level adjustment circuits to perform readout with high gain during low illumination and low gain during high illumination. When using AGC, to maintain signal linearity between high-gain and low-gain data, a process is performed in the digital circuitry of the later stage of the analog-to-digital converter (ADC) to repair high-gain data using the gain ratio between high and low gains. Because a gain ratio deviation between high and low gains occurs due to manufacturing variations during repair, and this deviation leads to step differences or gain linearity errors at the seams, it is necessary to calculate the actual gain ratio through calibration and thereby correct the gain ratio deviation. As a related technology, for example, as a technique to eliminate inconvenience caused by switching between exposures, a camera device that probabilistically changes the threshold has been proposed (e.g., see Patent Document 1).

[0003] List of cited references

[0004] Patent documents

[0005] Patent Document 1: Japanese Invention Patent Publication No. H04-172086 Summary of the Invention

[0006] The technical problem to be solved by the present invention

[0007] In the aforementioned conventional techniques, it is assumed that during the calibration of gains in the level adjustment circuit, low-light and high-light data for each gain are acquired sequentially, and the actual gain ratio is obtained. Therefore, there are issues with longer calibration times and longer waiting times before the camera data is read.

[0008] This technology was invented in view of the above situation, and its purpose is to reduce the amount of time required for calibration between gains in level adjustment circuits.

[0009] Solutions to technical problems

[0010] This technology was created to solve the aforementioned problems, and its first aspect is an imaging device and a gain ratio acquisition method for use in the imaging device. The imaging device includes: a level adjustment circuit configured to adjust the level of an analog signal output to vertical signal lines corresponding to columns of a pixel array using either a first gain or a second gain that are different from each other; an analog-to-digital converter configured to convert the level-adjusted analog signal into a digital signal; a test signal generation unit configured to generate a first test signal and a second test signal that are different from each other; and a gain ratio acquisition unit configured to simultaneously supply the first test signal to one of the vertical signal lines and the second test signal to another vertical signal line to obtain a gain ratio between the first gain and the second gain of the level adjustment circuit. Therefore, this invention provides the effect of obtaining a gain ratio by simultaneously supplying different test signals to one vertical signal line and another vertical signal line.

[0011] Furthermore, in the first aspect, the imaging device may further include: a gain ratio correction value generation unit configured to generate a gain ratio correction value based on the acquired gain ratio; and a correction unit configured to correct the digital signal according to the gain ratio correction value generated by the gain ratio correction value generation unit. Therefore, the present invention provides the effect of being able to correct digital signals based on the acquired gain ratio.

[0012] Furthermore, in the first aspect, the test signal generation unit can be configured to generate a potential for high illuminance data as the first test signal and a potential for generating low illuminance data as the second test signal. Therefore, the present invention provides the effect of generating potentials for both high illuminance and low illuminance data as test signals.

[0013] Furthermore, in the first aspect, one of the vertical signal lines can be a vertical signal line in an odd-numbered column, and the other vertical signal line can be a vertical signal line in an even-numbered column. Therefore, the present invention provides the effect of enabling the use of different test signals in adjacent columns.

[0014] Furthermore, in the first aspect, the gain ratio acquisition unit can be configured to acquire the gain ratio by simultaneously supplying the first test signal to one vertical signal line and the second test signal to the other vertical signal line, and then simultaneously supplying the second test signal to one vertical signal line and the first test signal to the other vertical signal line, respectively, for each gain of the level adjustment circuit set to 0dB, the first gain, and the second gain. Therefore, the present invention provides the effect of obtaining a gain ratio by supplying the first test signal and the second test signal to the one vertical signal line and the other vertical signal line in a manner that sequentially switches between the first test signal and the second test signal.

[0015] Furthermore, in the first aspect, the analog-to-digital converter may be configured for each of the plurality of vertical signal lines, and the gain ratio acquisition unit may be configured to simultaneously supply the first test signal to one vertical signal line and the second test signal to the other vertical signal line, and to acquire the gain ratio by sequentially selecting the first test signal and the second test signal supplied to any one of the one vertical signal line and the other vertical signal line, respectively, for each gain of the level adjustment circuit set to 0dB, the first gain, and the second gain. Therefore, the present invention provides the effect of acquiring the gain ratio by supplying the first test signal and the second test signal along the path from the one vertical signal line and the other vertical signal line to the analog-to-digital converter in a manner that sequentially switches between the first test signal and the second test signal.

[0016] Furthermore, in a first aspect, the imaging device may further include: a first sample-and-hold unit configured to hold an analog signal output to one of the vertical signal lines; and a second sample-and-hold unit configured to hold an analog signal output to the other vertical signal line; wherein the level adjustment circuit may be configured to sequentially perform the level adjustment on the output of either the first sample-and-hold unit or the second sample-and-hold unit; and the analog-to-digital converter may be configured to sequentially perform AD conversion on a plurality of outputs of the level adjustment circuit. Therefore, the present invention achieves the effect of obtaining a gain ratio by using the first sample-and-hold unit and the second sample-and-hold unit to supply analog signals to one vertical signal line and the other vertical signal line in a switching manner between the analog signals.

[0017] Furthermore, in the first aspect, each of the first and second sample-and-hold units may include two sample-and-hold circuits that operate alternately. Therefore, the present invention provides the effect of pipelined operation capable of simultaneously performing sampling and AD conversion operations.

[0018] Furthermore, in the first aspect, the level adjustment circuit may be an analog gain circuit configured to output a voltage signal obtained by applying the level adjustment to the analog signal, and the analog-to-digital converter may be a single-slope analog-to-digital converter configured to convert the voltage signal into the digital signal.

[0019] In addition, in the first aspect, the level adjustment circuit may be a voltage-to-current converter configured to output a current signal obtained by performing the level adjustment on the analog signal, and the analog-to-digital converter may be a current-input analog-to-digital converter configured to convert the current signal into the digital signal. Attached Figure Description

[0020] Figure 1 This is a diagram illustrating an overall structural example of a camera device according to a first embodiment of the present technology.

[0021] Figure 2 This is a diagram illustrating an example of the circuit configuration of each pixel column of the column signal processing circuit 100 according to the first embodiment of the present technology.

[0022] Figure 3 This is a diagram illustrating an example of a circuit configuration for gain ratio correction according to a first embodiment of the present technology.

[0023] Figure 4 This is a diagram illustrating a method for obtaining the gain ratio correction value during calibration according to a first embodiment of the present technology.

[0024] Figure 5 This is a diagram illustrating an example of the operation timing of calibration according to a first embodiment of the present technology.

[0025] Figure 6 This is a diagram illustrating an example of the operating timing of a camera device according to a first embodiment of the present technology.

[0026] Figure 7 This is a diagram illustrating an overall structural example of a camera device according to a second embodiment of the present technology.

[0027] Figure 8 This is a diagram illustrating a construction example of a column signal processing circuit 100 according to a second embodiment of the present technology.

[0028] Figure 9 This is a diagram illustrating the data flow of a column signal processing circuit 100 according to a second embodiment of the present technology.

[0029] Figure 10 This is a diagram illustrating an example of the operation timing for calibration according to a second embodiment of the present technology.

[0030] Figure 11 This is a diagram illustrating an example of the operating timing of a camera device according to a second embodiment of the present technology.

[0031] Figure 12 This is a diagram illustrating an overall structural example of a camera device according to a third embodiment of the present technology.

[0032] Figure 13 This is a diagram illustrating a construction example of a column signal processing circuit 100 according to a third embodiment of the present technology.

[0033] Figure 14 This is a diagram illustrating an example of the operating timing of a camera device according to a third embodiment of the present technology.

[0034] Figure 15 This is a diagram illustrating an overall structural example of a camera device according to a fourth embodiment of the present technology.

[0035] Figure 16 This is a diagram illustrating a construction example of a column signal processing circuit 100 according to a fourth embodiment of the present technology.

[0036] Figure 17 This is a diagram illustrating the data flow of a column signal processing circuit 100 according to a fourth embodiment of the present technology.

[0037] Figure 18 This is a diagram illustrating an example of the operating timing of a camera device according to a fourth embodiment of the present technology. Detailed Implementation

[0038] The following section will describe the patterns used to implement this technology (hereinafter referred to as implementation schemes). These will be described in the following order.

[0039] 1. First Implementation Scheme (Example of changing the test voltage in a time-division manner using a test voltage generation circuit)

[0040] 2. Second Implementation Scheme (Example of switching test voltage on the path to the AD converter)

[0041] 3. Third Implementation Scheme (assuming an example of a current-input type AD converter according to the first implementation scheme)

[0042] 4. Fourth Implementation Scheme (assuming an example of a current-input type AD converter according to the second implementation scheme)

[0043] <1. First Implementation Plan>

[0044] [Camera device]

[0045] Figure 1 This is a diagram illustrating an overall structural example of a camera device according to a first embodiment of the present technology.

[0046] The camera device consists of a pixel array 10 and a peripheral circuit section. The peripheral circuit section includes a vertical drive circuit 20, a horizontal drive circuit 30, a column signal processing circuit 100, and an output circuit 60.

[0047] The pixel array 10 is a two-dimensional array of pixels 11, each including a photoelectric conversion unit. Each pixel 11 has, for example, a photodiode serving as a photoelectric conversion unit and multiple pixel transistors. In this case, for example, the multiple pixel transistors can be composed of three types of transistors: a transmission transistor, a reset transistor, and an amplification transistor.

[0048] The vertical driving circuit 20 drives the pixels 11 row by row. For example, the vertical driving circuit 20 is composed of a shift register. The vertical driving circuit 20 selects a pixel driving line and supplies pulses to the selected pixel driving line for driving the pixel 11. Therefore, the vertical driving circuit 20 sequentially performs a selection scan on each pixel 11 in the pixel array 10 row by row in the vertical direction, and provides a pixel signal based on the signal charge generated corresponding to the amount of light received by the photoelectric conversion unit of each pixel 11 to the column signal processing circuit 100 through the vertical signal line (VSL) 19.

[0049] The horizontal drive circuit 30 drives the column signal processing circuit 100 column by column. For example, the horizontal drive circuit 30 is composed of a shift register. The horizontal drive circuit 30 sequentially selects each of the column signal processing circuits 100 by sequentially outputting horizontal scan pulses, and outputs the pixel signals from each of the column signal processing circuits 100 to the horizontal signal line 59 via switch 31.

[0050] In addition, the peripheral circuitry includes a control circuit (not shown). The control circuit is configured to control the imaging device as a whole, receiving an input clock and data for indicating operating modes, and outputting data such as internal information of the imaging device. Specifically, the control circuit generates clock signals and control signals as operating references for the vertical drive circuit 20, column signal processing circuit 100, and horizontal drive circuit 30, based on the vertical synchronization signal, horizontal synchronization signal, and master clock. Furthermore, the control circuit inputs these signals to the vertical drive circuit 20, column signal processing circuit 100, and horizontal drive circuit 30, etc.

[0051] For the signal output from pixel 11 in a row, column signal processing circuit 100 performs signal processing such as noise reduction for each pixel column. For example, column signal processing circuit 100 performs signal processing such as: correlated double sampling (CDS) to remove the fixed-pattern noise inherent in pixel 11; signal amplification; and analog-to-digital conversion.

[0052] The column signal processing circuit 100 includes a load MOS (load metal-oxide-semiconductor) 140, an analog gain circuit (AG) 160, and an analog-to-digital converter (ADC) 190, each corresponding to a pixel column. The load MOS (LM) 140 is a MOS transistor connected to each vertical signal line 19 and functions as a current source 141. The analog gain circuit (AG) 160 is a circuit that adjusts the level of the analog signal input from the load MOS 140 by a predetermined gain. The ADC (Analog to Digital Converter) 190 is a circuit that converts the voltage signal, i.e., the analog signal, from the analog gain circuit 160 into a digital signal. It should be noted that the analog gain circuit 160 is an example of the level adjustment circuit described in the claims.

[0053] The output circuit 60 performs signal processing on the signals from each pixel column sequentially supplied via the horizontal signal line 59 from the column signal processing circuit 100, and outputs the processed signal. In doing so, the output circuit 60 buffers the signal from the column signal processing circuit 100. Furthermore, the output circuit 60 can perform black level adjustment, column difference correction, and various types of digital signal processing on the signal from the column signal processing circuit 100.

[0054] In the analog gain circuit 160, gain calibration must be performed to correct the gain ratio deviation between high and low gains. For this purpose, the imaging device includes a test voltage generation circuit and outputs a test voltage. Each vertical signal line 19 is provided with a selector 134, and the selector 134 is configured to select either a pixel signal from the vertical signal line 19 or a test voltage from the test voltage generation circuit based on a control signal from the input switching control circuit 133, and supply either the pixel signal or the test voltage to the load MOS 140.

[0055] The test voltage generation circuit includes a resistor 111, a current source 112, a selector 113, and a voltage control register 114. Current from the current source 112 flows into the series-connected resistors 111, and the potential at each terminal is input to the input terminal of the selector 113. The voltage control register 114 is connected to the selection signal terminal of the selector 113, and the selector 113 outputs a voltage signal from its output terminal to signal lines 121 and 122 according to the value of the voltage control register 114. In other words, by changing the setting value of the voltage control register 114, the voltage signal output to signal lines 121 and 122 can be switched. It should be noted that the resistor 111, current source 112, and selector 113 are one example of the test signal generation unit described in the claims. Furthermore, the voltage control register 114, input switching control circuit 133, and selector 134 are one example of the gain ratio acquisition unit described in the claims.

[0056] Output buffers 131 and 132 are connected to signal lines 121 and 122, respectively, on the output side of selector 113. The output of one output buffer 131 corresponds to the vertical signal line 19 of the odd-numbered columns, and the output of the other output buffer 132 corresponds to the vertical signal line 19 of the even-numbered columns. Therefore, a configuration is achieved that allows supplying different voltage signals to the odd-numbered and even-numbered columns. Although the outputs of output buffers 131 and 132 can be short-circuited by switch 139, thereby allowing the same voltage signal to be supplied to the odd-numbered and even-numbered columns, in this embodiment, switch 139 is used in the open state.

[0057] Using the above configuration, by applying a potential VH of high illuminance data to signal line 121 and a potential VL of low illuminance data to signal line 122, the potential VH of high illuminance data is output to the odd-numbered column and the potential VL of low illuminance data is output to the even-numbered column. Furthermore, by applying a potential VL of low illuminance data to signal line 121 and a potential VH of high illuminance data to signal line 122, the potential VL of low illuminance data is output to the odd-numbered column and the potential VH of high illuminance data is output to the even-numbered column.

[0058] [Column Signal Processing Circuit]

[0059] Figure 2 This is a diagram illustrating an example of the circuit configuration of each pixel column of the column signal processing circuit 100 according to the first embodiment of the present technology.

[0060] As described above, the column signal processing circuit 100 includes, for each pixel column: a load MOS 140, an analog gain circuit 160, and an AD converter 190. In the first embodiment, a single-slope analog-to-digital converter is assumed to be used as the AD converter 190.

[0061] In addition, an AGC comparator 170 is provided to perform adaptive gain control (AGC) in the analog gain circuit 160. The AGC comparator 170 includes a comparator 172, a flip-flop 173, and a selector 174.

[0062] Comparator 172 compares the input voltage value with the AGC threshold to determine whether the input voltage value is low or high illumination. The analog gain circuit 160, upon receiving the determination result, uses high gain (HG) when it is determined to be low illumination and low gain (LG) when it is determined to be high illumination.

[0063] Flip-flop 173 is used to hold the determination result of comparator 172. In other words, flip-flop 173 holds the determination from the previous determination result regarding whether the input voltage value is under low or high illumination.

[0064] Selector 174 selects a manually set value or a value held in flip-flop 173 based on the selection signal (“Manual Setting EN”), and supplies the selected value to analog gain circuit 160. Under normal data signal conditions, the value held in flip-flop 173 will be supplied to analog gain circuit 160, while when performing gain calibration, the manually set value will be used, which will be explained later.

[0065] The analog gain circuit 160 includes an analog gain amplifier 161. The analog gain amplifier 161 amplifies the analog data signal input from the load MOS 140 based on the gain signal (high gain or low gain) input from the AGC comparator 170.

[0066] The AD converter 190 includes a ramp (RAMP) signal generation circuit 191, a comparator 192, and a counter 194.

[0067] The ramp signal generation circuit 191 generates a ramp signal that will be compared with the input signal. The ramp signal is a signal whose level monotonically increases or decreases over time. The ramp signal generation circuit 191 is, for example, constructed from a digital-to-analog converter (DAC).

[0068] Comparator 192 compares the input signal with a ramp signal from ramp signal generation circuit 191 to determine the magnitude relationship between the two signals. Counter 194 counts the time until their magnitude relationship reverses based on the determination result of comparator 192. Therefore, the input signal, which is an analog signal, can be converted into a digital signal.

[0069] [Gain Ratio Correction]

[0070] Figure 3 This is a diagram illustrating an example of a circuit configuration for gain ratio correction according to a first embodiment of the present technology.

[0071] As described above, selector 134 selects either the pixel signal from pixel 11 or the test voltage from test voltage generation circuit 110. Furthermore, although partially omitted in the previous figure, the output signal already output from output circuit 60 undergoes gain ratio correction by the signal processing unit in a later stage. The signal processing unit includes switch 310, correction value calculation circuit 320, and correction circuit 330.

[0072] The correction value calculation circuit 320 calculates a correction value through calibration and holds the calculated correction value. The correction value calculation circuit 320 includes a gain ratio correction value calculation circuit 321 and a correction memory 322. As will be described later, the gain ratio correction value calculation circuit 321 calculates a correction value for gain ratio correction through calibration. The correction memory 322 stores the calculation result of the gain ratio correction value calculation circuit 321 as a gain ratio correction value 324. The correction value calculation circuit 320 is an example of the gain ratio correction value generation unit described in the claims.

[0073] The correction circuit 330 uses the correction value calculated by the correction value calculation circuit 320 to correct the gain ratio. The correction circuit 330 includes a row buffer 331 and a multiplier 332. The row buffer 331 is a buffer that holds the output signal already output from the output circuit 60 for each row. The multiplier 332 multiplies the signal held in the row buffer 331 with the gain ratio correction value 324 stored in the correction memory 322, thereby correcting the gain ratio. The correction circuit 330 is an example of a correction unit as described in the claims.

[0074] Switch 310 is a switch that distributes the output signal already output from output circuit 60 to correction value calculation circuit 320 or correction circuit 330. During calibration, switch 310 outputs the test voltage from test voltage generation circuit 110 to correction value calculation circuit 320, and during pixel data readout, switch 310 outputs the pixel signal from pixel 11 to correction circuit 330. Therefore, gain ratio correction is performed during pixel data readout using the correction value calculated during calibration.

[0075] [calibration]

[0076] Figure 4 This is a diagram illustrating a method for obtaining the gain ratio correction value during calibration according to a first embodiment of the present technology.

[0077] In this graph, the horizontal axis represents analog values, and the vertical axis represents digital codes. As described above, in the analog gain circuit 160, gain control based on the AGC function is performed by switching between high and low gain. During calibration, the AGC function of the analog gain circuit 160 is turned off, and the analog gain is manually controlled. For each gain, the digital values ​​obtained after A / D conversion of the input analog low-light data and analog high-light data are acquired. In doing so, the digital values ​​of the low-light data and the high-light data are similarly acquired for the 0dB gain that will be used as a reference. For example, 12dB is assumed to be low gain, and 24dB is assumed to be high gain.

[0078] Furthermore, for each gain, the row average (average of all columns) of the illuminance difference between the low-illuminance data and the high-illuminance data is calculated. The row average UD0 of the illuminance difference at 0 dB is expressed as the difference between the average UH of the high-illuminance data and the average UL of the low-illuminance data.

[0079] UD0 = (UH – UL)

[0080] In addition, the row average UD of the illuminance difference at low gain LG The average UH expressed as high illumination data LG Average UL of low illumination data LG The difference between them is equal to the measured gain ratio G' of the low gain relative to the 0dB gain used as a reference. LG The product obtained by multiplying by UD0.

[0081] UD LG =UH LG -UL LG =G' LG ×(UH-UL)

[0082] Similarly, the row average UD of the illuminance difference at high gain is...HG The average UH expressed as high illumination data HG Average UL of low illumination data HG The difference between them is equal to the measured gain ratio G' of the high gain relative to the 0dB gain used as a reference. HG The product obtained by multiplying by UD0.

[0083] UD HG =UH HG -UL HG =G' HG ×(UH-UL)

[0084] Based on the ratio of the average illuminance difference obtained as described above, the correction value C for low gain is calculated. LG and the correction value C used for high gain HG Here, we assume that the ideal gain ratio for a low gain relative to a baseline 0dB gain is G. LG And assuming that the ideal gain ratio for a high gain relative to a 0dB gain as a reference is G HG .

[0085] C LG =(UD0 / UD) LG )×G LG =(G LG / G' LG )

[0086] C HG =(UD LG / UD HG )×C LG

[0087] =(G' LG / G' HG )×(G LG / G' LG )=(G LG / G' HG )

[0088] The correction value C used for low gain can be adjusted. LG and the correction value C used for high gain HG The gain ratio deviation between low and high gain is corrected by multiplying the measured data. Additionally, correspondingly, a correction of the high gain data based on the low gain data is also performed.

[0089] [operate]

[0090] Figure 5 This is a diagram illustrating an example of the operation timing of calibration according to a first embodiment of the present technology.

[0091] Before reading out the data, AGC calibration of the analog gain circuit 160 is performed within one horizontal detection cycle (1XHS). During calibration, for a total of three gains—in addition to the low and high gains of the analog gain circuit 160, including the 0dB gain as a reference—the potential VH of the high-illuminance data and the potential VL of the low-illuminance data are used as test voltages. In this process, according to the above configuration, by performing parallel operation using different voltage signals as test voltages in odd and even sequences, the data acquisition time can be shortened.

[0092] Furthermore, if the relationship between the illuminance data potential and the AD converter 190 is fixed, there is a risk of deterioration in calibration accuracy due to manufacturing differences in the circuit. Therefore, the connection between the test voltage generation circuit 110 and the vertical signal line 19 is switched in a time-division manner. In other words, the following operation is repeatedly performed: after outputting the potential VH of high illuminance data to an odd-numbered column and the potential VL of low illuminance data to an even-numbered column, the potential VL of low illuminance data is output to an odd-numbered column and the potential VH of high illuminance data is output to an even-numbered column. Therefore, information about high illuminance data and low illuminance data can be obtained in a balanced manner for each gain.

[0093] Figure 6 This is a diagram illustrating an example of the operating timing of a camera device according to a first embodiment of the present technology.

[0094] A pixel reset is performed before the data signal is read out. In other words, in pixel 11, the charge is reset, and a reset-based settling time is ensured for the voltage value of the vertical signal line 19 to stabilize (set up). At this time, a reset-based settling time is also performed in a similar manner in the AGC comparator 170.

[0095] After the reset stabilizes, the AD converter 190 performs the AD conversion of the reset signal. During this process, gain adjustment is performed in the analog gain circuit 160 based on both high and low gain.

[0096] Next, in pixel 11, the charge obtained from the exposure is transmitted as a data signal, and a time is ensured for the voltage value of the vertical signal line 19 to stabilize based on the data signal. At this time, the input voltage value and the AGC threshold are compared by comparator 172 in AGC comparator 170, and the comparison result is stored in trigger 173.

[0097] During the next A / D conversion, when pixel data is read out, the value held in trigger 173 is selected by selector 174, and the gain of analog gain circuit 160 is set based on the comparison result of this selected value and AGC threshold. In other words, gain adjustment is performed by analog gain circuit 160 in a manner that uses high gain in low illumination and low gain in high illumination, and A / D conversion is performed by A / D converter 190.

[0098] On the other hand, during calibration, the comparison result with the AGC threshold is not used, and selector 174 selects a manual setting value. In other words, high gain is set for high gain calibration and low gain is set for low gain calibration.

[0099] As described above, according to the first embodiment of this technology, during calibration according to AGC, by performing parallel operations using different voltage signals as test voltages in the odd and even columns, the time for acquiring test data can be shortened. Furthermore, switching the voltage signal between the odd and even columns in a time-division manner can prevent degradation of calibration accuracy.

[0100] <2. Second Implementation Plan>

[0101] In the first embodiment described above, the degradation of calibration accuracy is prevented by switching the test signal between odd and even columns in a time-division manner. In contrast, in the second embodiment, a technique for preventing the degradation of calibration accuracy without switching the test signal will be described. This technique is based on the provision of multiple groups consisting of analog gain circuits and multiple sample-and-hold circuits sharing the analog gain circuits, and pipelined operation is performed in each of these groups.

[0102] [Camera device]

[0103] Figure 7 This is a diagram illustrating an overall structural example of a camera device according to a second embodiment of the present technology.

[0104] The overall structure of the camera device according to the second embodiment is basically similar to that of the first embodiment described above. However, in this example, four pixel columns share one AD converter 190, and two pixel columns share one analog gain circuit 160. In other words, two analog gain circuits 160 are connected to one AD converter 190. Furthermore, for each pixel column, a sample-and-hold unit (S / H) 150 is connected between the load MOS 140 and the analog gain circuit 160.

[0105] In other words, this example employs the following construction: for one AD converter 190, two groups are provided, each consisting of an analog gain circuit 160 and two sample-and-hold sections 150 sharing the analog gain circuit 160. Furthermore, as described later, each sample-and-hold section 150 further includes two sample-and-hold circuits. In this second embodiment, a single-slope analog-to-digital converter is assumed to be the AD converter 190, in a manner similar to the first embodiment described above.

[0106] [Column Signal Processing Circuit]

[0107] Figure 8 This is a diagram illustrating a construction example of a column signal processing circuit 100 according to a second embodiment of the present technology.

[0108] As described above, in this example, two analog gain circuits 160 are connected to one AD converter 190, and furthermore, two sample-and-hold units 150 are connected to each analog gain circuit 160. In this figure, the four sample-and-hold units 150 connected to one AD converter 190 are designated as SH#0 to SH#3.

[0109] Each sample-and-hold unit 150 includes two sample-and-hold circuits (S / H) 151 and 152, a comparator (AGC Comp) 172, and a flip-flop (AGC FF) 173. Sample-and-hold circuits 151 and 152 are holding circuits that operate alternately in a relative timing sequence using switches located at the input and output. For convenience, sample-and-hold circuit 151 is designated as the foreground (F) and sample-and-hold circuit 152 as the background (B). The comparator 172 and flip-flop 173 are similar to the comparator and flip-flop in the AGC comparator 170 described in the first embodiment above.

[0110] The analog gain circuit 160 includes an analog gain amplifier 161 in a manner similar to that described in the first embodiment above. A data signal from either of the two sample-and-hold units 150 is input using a switch provided on the data signal input side of the analog gain amplifier 161. Furthermore, the output of the selector 174 is connected to the gain input side of the analog gain amplifier 161. The selector 174 is the same as the selector in the AGC comparator 170 described in the first embodiment above. However, a gain signal from either of the two sample-and-hold units 150 is input using a switch provided on the input side of the selector 174.

[0111] The AD converter 190 is the same as the AD converter in the first embodiment described above, including a ramp signal generation circuit 191, a comparator 192 and a counter 194, and is used to convert the analog input signal into a digital signal and then output the converted digital signal.

[0112] Figure 9 This is a diagram illustrating the data flow of a column signal processing circuit 100 according to a second embodiment of the present technology.

[0113] As described above, in each sample-and-hold unit 150, one sample-and-hold circuit 151 is considered to be in the foreground (F), and the other sample-and-hold circuit 152 is considered to be in the background (B), and it is assumed that these two sample-and-hold circuits operate alternately. In other words, while the data held in one of the two sample-and-hold circuits is undergoing an A / D conversion, the other sample-and-hold circuit simultaneously samples the next data signal in parallel. Conversely, while one of the two sample-and-hold circuits is sampling a data signal, the data held in the other sample-and-hold circuit undergoes an A / D conversion.

[0114] In these operations, the AD conversion is performed in a time-division manner by sharing the AD converter 190 and the two analog gain circuits 160. In other words, using one AD converter 190, four analog signals from four sample-and-hold units 150 undergo AD conversion in one horizontal detection cycle, divided into four stages #0 to #3.

[0115] [operate]

[0116] Figure 10 This is a diagram illustrating an example of the operation timing for calibration according to a second embodiment of the present technology.

[0117] As described above, in this second embodiment, four analog signals from the four sample-and-hold units 150 undergo AD conversion in one horizontal detection cycle by being divided into four stages #0 to #3. During calibration, the potential VH of high-illuminance data is supplied to the odd-numbered columns, while the potential VL of low-illuminance data is supplied to the even-numbered columns. Furthermore, AD conversion of the potential VH of high-illuminance data is performed in stages #0 and #1, and AD conversion of the potential VL of low-illuminance data is performed in stages #2 and #3.

[0118] In this way, by performing A / D conversion on the potential VH of high-illuminance data and the potential VL of low-illuminance data in stages during calibration, the data of both potential VH and potential VL can be acquired in a time-division manner for each gain within a single A / D converter 190. In other words, since potential VH and potential VL are supplied to the A / D converter 190 sequentially in each stage, the data acquisition time can be shortened without having to switch the test voltage between odd and even columns as in the first embodiment described above.

[0119] Figure 11 This is a diagram illustrating an example of the operating timing of a camera device according to a second embodiment of the present technology.

[0120] A pixel reset is performed before the data signal is read out. In other words, in pixel 11, the charge is reset, and a time is ensured for the voltage value of the vertical signal line 19 to stabilize based on the reset. In this case, it is assumed that the reset signal will be held in the four sample-and-hold circuits 151 of the four sample-and-hold units 150. At this time, reset-based stabilization is also performed in a similar manner in the AGC comparator 170.

[0121] In the next cycle, for the reset signal held by the four sample-and-hold circuits 151, AD conversion is performed in the AD converter 190 by dividing it into four stages #0 to #3. In other words, the signal from SH#0 is converted at stage #0, the signal from SH#2 at stage #1, the signal from SH#1 at stage #2, and the signal from SH#3 at stage #3. This readout order is used to avoid conflicts in the analog gain circuit 160.

[0122] During the AD conversion, although the gain is selected based on the comparison result of the AGC comparator 170 when reading out pixel data, since this determination has not been performed before the AD conversion time of the reset signal, the gain adjustment is performed in the analog gain circuit 160 based on both high gain and low gain.

[0123] In parallel with the AD conversion of the reset signal, in pixel 11, the charge obtained from exposure is transmitted as a data signal, and a time is ensured for the voltage value of the vertical signal line 19 to stabilize based on the data signal. In this case, it is assumed that the data signal is held in the four sample-and-hold circuits 152 of the four sample-and-hold sections 150. At this time, the comparison between the input voltage value and the AGC threshold is performed by the comparator 172, and the comparison result is held in the trigger 173.

[0124] In the next cycle, for the data signal held by the four sample-and-hold circuits 152, AD conversion is performed in the AD converter 190 by dividing it into four stages #0 to #3. In other words, the signal from SH#0 is converted at stage #0, the signal from SH#2 is converted at stage #1, the signal from SH#1 is converted at stage #2, and the signal from SH#3 is converted at stage #3.

[0125] During AD conversion, the gain is selected based on the comparison result of AGC comparator 170 when reading out pixel data. On the other hand, during calibration, the comparison result with the AGC threshold is not used, and selector 174 selects a manually set value. In other words, a high gain is set for high-gain calibration, and a low gain is set for low-gain calibration.

[0126] As described above, according to the second embodiment of this technology, the potential VH of high illuminance data and the potential VL of low illuminance data are converted by AD in stages, so there is no need to switch the test voltage during calibration, thereby shortening the time for acquiring test data.

[0127] <3. Third Implementation Plan>

[0128] Although a single-slope analog-to-digital converter is assumed to be the AD converter 190 in the first embodiment described above, in this third embodiment, a current-input analog-to-digital converter is assumed to be the AD converter 190. Specific examples of current-input analog-to-digital converters include Δ-Σ (delta-sigma) type AD converters.

[0129] [Camera device]

[0130] Figure 12 This is a diagram illustrating an overall structural example of a camera device according to a third embodiment of the present technology.

[0131] The overall structure of the camera device according to the third embodiment is basically similar to that of the first embodiment described above. However, since it is based on the premise of using a current-input type analog-to-digital converter as the AD converter 190, this camera device includes a dual sample-and-hold unit (DUAL S / H) 250 and a voltage-to-current converter (V2I) 260 instead of an analog gain circuit 160.

[0132] The dual sample-and-hold unit 250 holds the reset signal and the data signal of the vertical signal line 19 as voltages respectively.

[0133] The voltage-to-current converter 260 converts the voltage difference (potential difference) between the reset signal and the data signal held in the dual sample-and-hold unit 250 into a current. In the voltage-to-current converter 260, analog correlated double sampling (analog CDS) is performed using the potential difference between the reset signal and the data signal held in the dual sample-and-hold unit 250. Therefore, the fixed-pattern noise inherent in pixel 11 can be removed.

[0134] In the voltage-to-current converter 260, level adjustment is performed with a predetermined gain when the potential difference is converted into current. Therefore, similar to the analog gain circuit 160 of the first and second embodiments described above, calibration between high and low gains must be performed to correct the gain ratio deviation between high and low gains. Therefore, the imaging device according to the third embodiment also includes a test voltage generation circuit for outputting a test voltage. It should be noted that the voltage-to-current converter 260 is an example of the level adjustment circuit described in the claims.

[0135] The calibration timing of the camera device according to the third embodiment is similar to that of the first embodiment described above. In other words, for a total of three gains—in addition to the low and high gains of the voltage-to-current converter 260, including a reference 0dB gain—the potential VH of the high-illuminance data and the potential VL of the low-illuminance data will be used as test voltages. In this process, by performing parallel operations using different voltage signals as test voltages in odd and even sequences, the time for acquiring test data can be shortened.

[0136] [Column Signal Processing Circuit]

[0137] Figure 13 This is a diagram illustrating a construction example of a column signal processing circuit 100 according to a third embodiment of the present technology.

[0138] As described above, in this example, it is assumed that the current-input analog-to-digital converter is used as the AD converter 190, and the camera device includes a dual sample-and-hold unit 250 and a voltage-to-current converter 260. The dual sample-and-hold unit 250 includes a reset signal sample-and-hold unit (RESET S / H) 280-1, a data signal sample-and-hold unit (DATA S / H) 280-2, and an AGC comparator 270.

[0139] Both the reset signal sampling and holding unit 280-1 and the data signal sampling and holding unit 280-2 are configured as switched capacitors, and each includes a sampling capacitor 281, a comparator 282, and switches 283 to 286.

[0140] The reset signal sampling and holding unit 280-1 holds the reset signal. During the reset period (t1), switches 283 and 284 are turned on. At this time, the difference "Vin(t1)-Vref" between the voltage Vin(t1) during the reset period and the reference potential Vref is applied to the sampling capacitor 281, and its voltage is held. Then, when switches 285 and 286 are turned on, the voltage of the reset signal is applied to the voltage-current converter 260.

[0141] The data signal sampling and holding unit 280-2 holds the data signal. During the data sampling period (t2), switches 283 and 284 are turned on. At this time, the difference "Vin(t2)-Vref" between the voltage Vin(t2) during the reset period and the reference potential Vref is applied to the sampling capacitor 281, and its voltage is held. Then, when switches 285 and 286 are turned on, the voltage of the data signal is supplied to the voltage-current converter 260.

[0142] The AGC comparator 270 is a switched-capacitor type comparator for performing adaptive gain control (AGC), and includes a sampling capacitor 271, a comparator 272, switches 273, switches 274, a flip-flop 275, and a selector 276.

[0143] During the reset period (t1), switches 273 and 274 are turned on, and charges are accumulated in the sampling capacitor 271. In addition, during the data sampling period (t2), switch 273 is turned on, but switch 274 is turned off. Therefore, the potential difference (Vin(t1)-Vin(t2)) between the voltage Vin(t1) during the reset period (t1) and the voltage Vin(t2) during the data sampling period (t2) is held in the sampling capacitor 271. Then, this potential difference is compared with the threshold value Vagc. For example, when "Vin(t1)-Vin(t2)>Vagc", "1 (high illuminance)" is generated as the determination result, and when "Vin(t1)-Vin(t2)<Vagc", "0 (low illuminance)" is generated as the determination result, and this determination result is held in the flip-flop 275.

[0144] The selector 276 selects a manual setting value or the value held in the flip-flop 275 according to the selection signal ("manual setting EN"), and supplies the selected value to the voltage-current converter 260. For a normal data signal, the value held in the flip-flop 275 will be supplied to the voltage-current converter 260, and when performing calibration between gains, the manual setting value will be used, as described below.

[0145] The voltage-to-current converter 260 includes a current source 261, transistors 262 and 264, and a variable resistor 263. When switches 285 and 286 of the reset signal sample-and-hold unit 280-1 are turned on, a reset signal voltage is applied between the gate and source of transistor 262. Furthermore, when switches 285 and 286 of the data signal sample-and-hold unit 280-2 are turned on, a data signal voltage is applied between the gate and source of transistor 264.

[0146] A variable resistor 263 is positioned on the path from the current source 261 to the A / D converter 190, and based on the resistance value of the variable resistor 263, a current corresponding to the potential difference between the voltage of the reset signal and the voltage of the data signal is supplied to the A / D converter 190. The control signal for the variable resistor 263 is supplied from the AGC comparator 270. For example, a low-gain (LG) control signal is supplied to the variable resistor 263 in the "1 (high illumination)" case, but a high-gain (HG) control signal is supplied to the variable resistor 263 in the "0 (low illumination)" case, and the resistance value corresponding to the control signal is selected.

[0147] [operate]

[0148] Figure 14 This is a diagram illustrating an example of the operating timing of a camera device according to a third embodiment of the present technology.

[0149] A pixel reset is performed before reading the data signal. In other words, in pixel 11, the charge is reset, and a reset-based stabilization time is ensured for the voltage value of the vertical signal line 19. A similar reset-based stabilization time is also performed in the AGC comparator 270.

[0150] Next, in pixel 11, the charge obtained from the exposure is transmitted as a data signal, and a time is ensured for the voltage value of the vertical signal line 19 to stabilize based on the data signal. At this time, the input voltage value and the AGC threshold are compared by comparator 272 of AGC comparator 270, and the comparison result is held by trigger 275.

[0151] Next, the voltage-to-current converter 260 converts the potential difference between the reset signal and the data signal into current. During this process, in the voltage-to-current converter 260, gain adjustment is performed based on either high gain or low gain according to the comparison result of the AGC comparator 270. In other words, high gain is used in low-light conditions but low gain is used in high-light conditions; gain adjustment is performed by the voltage-to-current converter 260, and AD conversion is performed by the AD converter 190.

[0152] On the other hand, during calibration, the comparison result with the AGC threshold is not used, and selector 276 selects a manual setting value. In other words, high gain is set for high gain calibration and low gain is set for low gain calibration.

[0153] As described above, according to the third embodiment of this technology, when a current-input type analog-to-digital converter is used as the AD converter 190, a technique similar to that of the first embodiment of the assumed single-slope analog-to-digital converter can also be used.

[0154] <4. Fourth Implementation Plan>

[0155] Although a single-slope analog-to-digital converter is assumed to be used as AD converter 190 in the second embodiment described above, in this fourth embodiment, a current-input type analog-to-digital converter is assumed to be used as AD converter 190.

[0156] [Camera device]

[0157] Figure 15 This is a diagram illustrating an overall structural example of a camera device according to a fourth embodiment of the present technology.

[0158] The overall structure of the camera device according to this fourth embodiment is basically similar to that of the second embodiment described above. However, since this fourth embodiment assumes the use of a current-input type analog-to-digital converter as the AD converter 190, the camera device, in a manner similar to the third embodiment, does not include an analog gain circuit 160 but instead includes a dual sample-and-hold unit (DS / H) 250 and a voltage-to-current converter (V2I) 260.

[0159] Furthermore, in this example, four pixel columns share one AD converter 190, and two pixel columns share one voltage-to-current converter 260. In other words, two voltage-to-current converters 260 are connected to one AD converter 190. Additionally, between the load MOS 140 and the voltage-to-current converter 260 of each pixel column, two dual sample-and-hold units 250 are connected corresponding to one load MOS 140.

[0160] In other words, this example adopts the following construction: for an AD converter 190, there are two groups consisting of a voltage-to-current converter 260 and four dual sample-and-hold units 250 sharing the voltage-to-current converter 260.

[0161] The calibration operation sequence of the camera device according to the fourth embodiment is similar to that of the second embodiment described above. In other words, in one horizontal detection cycle, four analog signals from the four dual sample-and-hold units 250 are converted to analog signals by being divided into four stages #0 to #3. During calibration, the potential VH of high illumination data is supplied to the odd-numbered columns, while the potential VL of low illumination data is supplied to the even-numbered columns. Furthermore, the conversion of the potential VH of high illumination data is performed in stages #0 and #1, and the conversion of the potential VL of low illumination data is performed in stages #2 and #3. Therefore, since the potential VH and potential VL are supplied to the analog-to-digital converter 190 sequentially in each stage, the time for acquiring test data can be shortened without having to switch the test voltage between the odd and even columns as in the first and third embodiments described above.

[0162] [Column Signal Processing Circuit]

[0163] Figure 16 This is a diagram illustrating a construction example of a column signal processing circuit 100 according to a fourth embodiment of the present technology.

[0164] As described above, in this example, two voltage-to-current converters (V2I) 260 are connected to one analog-to-digital converter (ADC) 190. Furthermore, each voltage-to-current converter 260 is connected to four dual sample-and-hold units (DUAL S / H) 250. In this figure, the eight dual sample-and-hold units 250 connected to the ADC 190 are divided into a front-end (F) and a back-end (B) in a manner similar to the second embodiment, and are designated as DUAL S / H#0-F, #0-B, #1-F, #1-B, #2-F, #2-B, #3-F, and #3-B. The other components of the dual sample-and-hold units 250 are the same as those in the third embodiment described above.

[0165] Figure 17 This is a diagram illustrating the data flow of a column signal processing circuit 100 according to a fourth embodiment of the present technology.

[0166] As described above, the double sample-and-hold unit 250 is divided into a front-end (F) and a back-end (B), and is assumed to operate alternately. In other words, while data held in one of the two double sample-and-hold units 250 is undergoing A / D conversion, the other double sample-and-hold unit 250 simultaneously samples the next data in parallel. Conversely, while one of the two double sample-and-hold units 250 is sampling data, data held in the other double sample-and-hold unit 250 undergoes A / D conversion.

[0167] In these operations, the AD conversion is performed in a time-division manner by sharing the AD converter 190 and the two voltage-to-current converters 260. In other words, using one AD converter 190, the four analog signals from the four dual sample-and-hold units 250 are divided into four stages #0 to #3 to perform AD conversion in one horizontal detection cycle.

[0168] [operate]

[0169] Figure 18 This is a diagram illustrating an example of the operating timing of a camera device according to a fourth embodiment of the present technology.

[0170] A pixel reset is performed before the data signal is read out. In other words, in pixel 11, the charge is reset, and a time is ensured for the voltage value of the vertical signal line 19 to stabilize based on the reset. In this case, it is assumed that the reset signal is held by four dual sample-and-hold units 250. At this time, reset-based stabilization is also performed in a similar manner in the AGC comparator 270.

[0171] Furthermore, sufficient time is allocated for the data signal to stabilize. In this case, it is assumed that the data signal is held by four double sample-and-hold units 250. At this time, the stabilization of the data signal is also performed in a similar manner in the AGC comparator 270, and the data signal is compared with a threshold.

[0172] In the next cycle, using the reset signal and data signal held in the four dual sample-and-hold units 250 respectively, and the comparison result in the AGC comparator 270, gain adjustment based on either low gain or high gain is performed in the voltage-to-current converter 260. Furthermore, AD conversion is performed in the AD converter 190 in a manner divided into four stages #0 to #3. In other words, signals from dual S / H#0-F are converted in stage #0, signals from dual S / H#2-F are converted in stage #1, signals from dual S / H#1-F are converted in stage #2, and signals from dual S / H#3-F are converted in stage #3. This readout order is used to avoid collisions in the voltage-to-current converter 260.

[0173] During this cycle, in parallel with the AD conversion based on the reset signal and data signal held in the four dual sample-and-hold units 250 respectively, pixel reset, pixel stabilization, and data signal stabilization are re-executed in the other four dual sample-and-hold units 250. At this time, data signal stabilization is also performed in a similar manner in the AGC comparator 270, and the data signal is compared with a threshold.

[0174] In the next cycle, using the reset signal and data signal held in the four dual sample-and-hold units 250 respectively in the previous cycle, and using the comparison result in the AGC comparator 270, analog gain adjustment based on either low gain or high gain is performed in the voltage-to-current converter 260. Furthermore, AD conversion is performed in the AD converter 190 in a manner divided into four stages #0 to #3. In other words, signals from dual S / H#0-B are converted in stage #0, signals from dual S / H#2-B are converted in stage #1, signals from dual S / H#1-B are converted in stage #2, and signals from dual S / H#3-B are converted in stage #3. Thereafter, similar processing is repeated by alternately reversing the roles of the foreground and background.

[0175] As described above, according to the fourth embodiment of this technology, when a current-input type analog-to-digital converter is used as the AD converter 190, a technique similar to that of the second embodiment of the assumed single-slope analog-to-digital converter can also be used.

[0176] It should be noted that the above embodiments illustrate examples for implementing this technology, and the matters in each embodiment correspond to the specific matters of the invention within the scope of the claims. Similarly, the specific matters of the invention within the scope of the claims correspond to matters with the same names in the embodiments of this technology. However, this technology is not limited to each embodiment, and can be implemented by applying various modifications to the embodiments without departing from the spirit of this technology.

[0177] Furthermore, the effects described in this specification are merely examples and are not intended to be limiting; other effects may be achieved.

[0178] This technology can also have the following technical solutions.

[0179] (1) A camera device, comprising:

[0180] The level adjustment circuit is configured to perform level adjustment on the analog signals output to the vertical signal lines corresponding to each column of the pixel array by using either a first gain or a second gain that are different from each other.

[0181] An analog-to-digital converter is configured to convert the analog signal, after the level adjustment has been applied, into a digital signal;

[0182] The test signal generation unit is configured to generate a first test signal and a second test signal that are different from each other; and

[0183] A gain ratio acquisition unit is configured to simultaneously supply the first test signal to one of the vertical signal lines and the second test signal to the other vertical signal line to acquire the gain ratio between the first gain and the second gain of the level adjustment circuit.

[0184] (2) The camera device according to (1) further includes:

[0185] A gain ratio correction value generation unit is configured to generate a gain ratio correction value based on the acquired gain ratio; and

[0186] The correction unit is configured to correct the digital signal based on the gain ratio correction value generated by the gain ratio correction value generation unit.

[0187] (3) The camera device according to (1) or (2), wherein,

[0188] The test signal generation unit is configured to generate a potential for high illumination data as the first test signal and a potential for low illumination data as the second test signal.

[0189] (4) The camera device according to any one of (1) to (3), wherein,

[0190] The vertical signal line is an odd-numbered vertical signal line, and

[0191] The other vertical signal line is a vertical signal line in an even-numbered column.

[0192] (5) The camera device according to any one of (1) to (3), wherein,

[0193] The gain ratio acquisition unit is configured to acquire the gain ratio by simultaneously supplying the first test signal to one vertical signal line and the second test signal to the other vertical signal line for each gain of the level adjustment circuit that is respectively set to 0dB, the first gain, and the second gain.

[0194] (6) The camera device according to any one of (1) to (5), wherein,

[0195] The analog-to-digital converter is configured for each of the plurality of vertical signal lines, and

[0196] The gain ratio acquisition unit is configured to simultaneously supply the first test signal to one vertical signal line and the second test signal to the other vertical signal line, and to acquire the gain ratio by sequentially selecting the first test signal and the second test signal supplied to either the one vertical signal line or the other vertical signal line for each gain of the level adjustment circuit that is respectively set to 0dB, the first gain, and the second gain.

[0197] (7) The camera device according to (6) further includes:

[0198] A first sample-and-hold section is configured to hold the analog signal output to said vertical signal line; and

[0199] The second sample-and-hold section is configured to hold the analog signal output to the other vertical signal line.

[0200] The level adjustment circuit is configured to sequentially perform level adjustment on the output of either the first sample-and-hold section or the second sample-and-hold section, and

[0201] The analog-to-digital converter is configured to sequentially perform AD conversion on the multiple outputs of the level adjustment circuit.

[0202] (8) The camera device according to (7), wherein,

[0203] Each of the first sample-and-hold section and the second sample-and-hold section includes two sample-and-hold circuits that operate alternately.

[0204] (9) The camera device according to any one of (1) to (5), wherein,

[0205] The level adjustment circuit is an analog gain circuit, configured to output a voltage signal obtained by applying the level adjustment to the analog signal.

[0206] The analog-to-digital converter is a single-slope analog-to-digital converter.

[0207] (10) The camera device according to any one of (1) to (4) or (6) to (8), wherein,

[0208] The level adjustment circuit is a voltage-to-current converter, configured to output a current signal obtained by applying the level adjustment to the analog signal.

[0209] The analog-to-digital converter is a current-input analog-to-digital converter, which is configured to convert the current signal into the digital signal.

[0210] (11) A method for obtaining the gain ratio in a camera device.

[0211] The imaging device includes: a level adjustment circuit that performs level adjustment on analog signals output to vertical signal lines corresponding to columns of a pixel array using either a first gain or a second gain that are different from each other; an analog-to-digital converter that converts the level-adjusted analog signals into digital signals; and a test signal generation unit that generates first and second test signals that are different from each other.

[0212] The camera device simultaneously performs the following steps:

[0213] The steps of supplying the first test signal to one of the vertical signal lines to obtain the gain ratio between the first gain and the second gain of the level adjustment circuit; and

[0214] The step of supplying the second test signal to another of the vertical signal lines to obtain the gain ratio between the first gain and the second gain of the level adjustment circuit.

[0215] List of reference numerals

[0216] 10: Pixel Array

[0217] 11: pixels

[0218] 19: Vertical Signal Line (VSL)

[0219] 20: Vertical drive circuit

[0220] 30: Horizontal drive circuit

[0221] 31: Switch

[0222] 59: Horizontal signal line

[0223] 60: Output Circuit

[0224] 100: Column signal processing circuit

[0225] 110: Test voltage generation circuit

[0226] 111: Resistor

[0227] 112: Current source

[0228] 113: Selector

[0229] 114: Voltage Control Register

[0230] 131, 132: Output buffers

[0231] 133: Input switching control circuit

[0232] 134: Selector

[0233] 139: Switch

[0234] 141: Current Source

[0235] 150: Sampling and Holding Section

[0236] 151, 152: Sample and Hold Circuit

[0237] 160: Analog Gain Circuit

[0238] 161: Analog Gain Amplifier

[0239] 170: AGC (Adaptive Gain Control) Comparator

[0240] 172: Comparator

[0241] 173: Trigger

[0242] 174: Selector

[0243] 190: A / D (Analog-to-Digital) Converter

[0244] 191: Ramp Signal Generation Circuit

[0245] 192: Comparator

[0246] 194: Counter

[0247] 250: Dual sampling and holding section

[0248] 260: Voltage-to-current converter (V2I)

[0249] 310: Switch

[0250] 320: Correction value calculation circuit

[0251] 321: Gain Ratio Correction Value Calculation Circuit

[0252] 322: Correction Memory

[0253] 324: Gain ratio correction value

[0254] 330: Correction circuit

[0255] 331: Line buffer

[0256] 332: Multiplier

Claims

1. A camera device, comprising: The level adjustment circuit is configured to perform level adjustment on the analog signals output to the vertical signal lines corresponding to each column of the pixel array by using either a first gain or a second gain that are different from each other. An analog-to-digital converter is configured to convert the analog signal, after the level adjustment has been applied, into a digital signal; The test signal generation unit is configured to generate a first test signal and a second test signal that are different from each other. as well as A gain ratio acquisition unit is configured to simultaneously supply the first test signal to one of the vertical signal lines and the second test signal to the other vertical signal line to acquire the gain ratio between the first gain and the second gain of the level adjustment circuit.

2. The camera device according to claim 1, further comprising: A gain ratio correction value generation unit is configured to generate a gain ratio correction value based on the acquired gain ratio; and The correction unit is configured to correct the digital signal based on the gain ratio correction value generated by the gain ratio correction value generation unit.

3. The camera device according to claim 1, wherein, The test signal generation unit is configured to generate a potential for high illumination data as the first test signal and a potential for low illumination data as the second test signal.

4. The camera device according to claim 1, wherein, The vertical signal line is an odd-numbered vertical signal line, and The other vertical signal line is a vertical signal line in an even-numbered column.

5. The camera device according to claim 1, wherein, The gain ratio acquisition unit is configured to acquire the gain ratio by simultaneously supplying the first test signal to one vertical signal line and the second test signal to the other vertical signal line for each gain of the level adjustment circuit that is respectively set to 0dB, the first gain, and the second gain.

6. The camera device according to claim 1, wherein, The analog-to-digital converter is configured for each of the plurality of vertical signal lines, and The gain ratio acquisition unit is configured to simultaneously supply the first test signal to one vertical signal line and the second test signal to the other vertical signal line, and to acquire the gain ratio by sequentially selecting the first test signal and the second test signal supplied to either the one vertical signal line or the other vertical signal line for each gain of the level adjustment circuit that is respectively set to 0dB, the first gain, and the second gain.

7. The camera device according to claim 6, further comprising: The first sample-and-hold section is configured to hold the analog signal output to the vertical signal line; and The second sample-and-hold section is configured to hold the analog signal output to the other vertical signal line. The level adjustment circuit is configured to sequentially perform level adjustment on the output of either the first sample-and-hold section or the second sample-and-hold section, and The analog-to-digital converter is configured to sequentially perform AD conversion on the multiple outputs of the level adjustment circuit.

8. The camera device according to claim 7, wherein, Each of the first sample-and-hold section and the second sample-and-hold section includes two sample-and-hold circuits that operate alternately.

9. The camera device according to any one of claims 1 to 8, wherein, The level adjustment circuit is an analog gain circuit, configured to output a voltage signal obtained by applying the level adjustment to the analog signal. The analog-to-digital converter is a single-slope analog-to-digital converter, which is configured to convert the voltage signal into the digital signal.

10. The camera device according to any one of claims 1 to 8, wherein, The level adjustment circuit is a voltage-to-current converter, configured to output a current signal obtained by applying the level adjustment to the analog signal, and The analog-to-digital converter is a current-input analog-to-digital converter, which is configured to convert the current signal into the digital signal.

11. A method for obtaining the gain ratio in a camera device, wherein, The imaging device includes: a level adjustment circuit that performs level adjustment on analog signals output to vertical signal lines corresponding to columns of a pixel array using either a first gain or a second gain that are different from each other; an analog-to-digital converter that converts the level-adjusted analog signals into digital signals; and a test signal generation unit that generates first and second test signals that are different from each other. The camera device simultaneously performs the following steps: The steps of supplying the first test signal to one of the vertical signal lines to obtain the gain ratio between the first gain and the second gain of the level adjustment circuit; and The step of supplying the second test signal to another of the vertical signal lines to obtain the gain ratio between the first gain and the second gain of the level adjustment circuit.

Images