A MEMS chip low-stress porous array packaging structure and a packaging method

Abstract

The application discloses a kind of MEMS chip low stress porous array package structure and packaging method, the method includes the processing of porous array structure silicon substrate;The processing of porous array structure silicon substrate includes the following steps: preparation single crystal silicon wafer, bottom isolation cavity is carved, top etching porous array structure, etching scribe groove, scribe single silicon substrate along scribe groove, the silicon substrate bottom etching isolation cavity of the present application, so that the step is generated between the lower surface of silicon substrate and the bottom surface of porous array structure, fixed on the bottom surface of package tube shell by annular adhesive, both mechanical fixation and reduce the bonding stress of silicon substrate.The step can avoid the bottom surface of silicon substrate to be glued too much and overflow, resulting in sticking with the bottom surface of porous array structure, and by setting porous array structure, so that product can release the stress between package tube shell and silicon substrate while providing sufficient strength for MEMS chip and silicon substrate.

Description

Technical Field

[0001] This invention belongs to the field of MEMS chip packaging technology, specifically relating to a low-stress porous array packaging structure and packaging method for MEMS chips. Background Technology

[0002] Surface mount technology (SMT) is a crucial step in MEMS device-level packaging. Its primary function is to provide mechanical support for the device's sensitive structures, ensuring that external vibrations and shocks do not damage moving and functional components. It also affects the device's thermal conductivity. Common SMT methods include soldering and adhesive bonding. Compared to soldering, adhesive bonding offers advantages such as lower cost, lower stress, lower operating temperature, and simpler and more flexible processes, making it widely used in MEMS SMT manufacturing.

[0003] Traditional silicon-based stacked MEMS chip packaging structures typically consist of a package shell, a substrate, adhesive, a MEMS chip, and an ASIC chip, as shown in the cross-sectional view below. Figure 1 As shown, the substrate is bonded to the casing using adhesive, the MEMS chip is bonded to the center of the upper surface of the silicon substrate, and the ASIC chip is bonded to the center of the upper surface of the MEMS chip. This packaging method has significant drawbacks in practical applications: the adhesive cures at high temperatures, and upon returning to room temperature, thermal mismatch occurs due to differences in the thermal expansion coefficients of the various packaging materials, leading to residual stress within the chip. MEMS devices are extremely small and require high measurement accuracy, making them particularly sensitive to residual stress caused by packaging. After temperature changes or long-term storage, the residual stress inside the device changes with temperature and time, resulting in performance variations and issues with temperature and long-term stability. Therefore, high-precision and high-performance MEMS devices require addressing the two challenges of temperature rise and thermal stress in MEMS chip packaging.

[0004] MEMS packaging is an evolution of microelectronic packaging processes and technologies. It is a necessary process for MEMS devices to go through from chip to final product. Due to the small size, high measurement accuracy, and complexity and special nature of application environments of MEMS devices, in addition to meeting basic requirements such as power distribution, signal distribution, heat dissipation channels, mechanical support, and environmental protection, reducing or isolating packaging stress is also an important consideration in MEMS device packaging.

[0005] Mechanical stress introduced by packaging is due to the difference in Young's modulus and the mismatch in thermal expansion coefficients between the chip, surface mount material, substrate, and package shell. Temperature changes will introduce thermal stress between various parts of the device. The introduction of thermal stress will cause abnormal deformation of the stress-sensitive MEMS structure, thereby affecting the performance parameters of MEMS devices such as resolution, sensitivity and stability. In severe cases, it will lead to device failure.

[0006] To reduce or isolate the packaging stress of MEMS devices, researchers at home and abroad have proposed a variety of solutions. The methods commonly used to reduce or isolate the packaging stress of MEMS devices are as follows: (1) Using point bonding or surface bonding to reduce the contact area between the MEMS chip and the package shell. The disadvantage is that the connection strength between the chip and the shell is low and the resistance to mechanical shock is weak. Moreover, it is difficult to ensure the uniformity of the deformation of the MEMS chip. (2) Using soft glue with low hardness as adhesive. The disadvantage is that the soft glue itself is easy to deform and has weak resistance to mechanical shock. (3) Stress isolation between the MEMS chip and the shell is achieved by inserting an elastic packaging substrate between the package shell and the MEMS chip. The disadvantage is that the substrate cost is high, the packaging process is complex, the resistance to mechanical shock is weak, low-frequency resonance is easy to occur, and signal delay may also occur. Summary of the Invention

[0007] The purpose of this invention is to provide a low-stress porous array packaging structure and packaging method for MEMS chips, so as to solve the technical problems of stress isolation between MEMS chips and packaging shells, and the impact of packaging stress on MEMS structure chips.

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] In a first aspect, the present invention provides a low-stress porous array packaging structure for MEMS chips, including a packaging shell and a silicon substrate, wherein the bottom outer periphery of the silicon substrate is adhesively bonded to the inner bottom upper surface of the packaging shell.

[0010] An isolation cavity is provided between the silicon substrate and the packaging shell. The bottom surface of the silicon substrate surrounding the isolation cavity is bonded to the packaging shell. The height of the isolation cavity is greater than the height of the adhesive layer between the silicon substrate and the packaging shell. By providing an isolation cavity at the bottom of the silicon substrate, the contact area is reduced, thereby reducing the packaging stress between the silicon substrate and the packaging shell.

[0011] The silicon substrate is provided with a porous array structure, which extends downward through the silicon substrate to connect the isolation cavity with the external space.

[0012] The above technical solution achieves a flexible connection between the MEMS chip bonding area on the silicon substrate and its surroundings through a porous array structure. The isolation cavity etched on the bottom surface of the silicon substrate not only reduces the packaging stress between the silicon substrate and the packaged casing by decreasing the contact area, but also creates a height difference between the bottom bonding surface of the silicon substrate and the bottom surface of the porous array structure. This prevents excessive adhesive overflow from the bottom surface of the silicon substrate from causing adhesion to the bottom surface of the porous array structure. By fully utilizing the thickness of the adhesive itself and the height of the isolation cavity on the bottom surface of the silicon substrate, the porous array structure and the MEMS chip bonding area on the silicon substrate are suspended above the packaged casing.

[0013] Optionally, a MEMS chip is glued to the top of the silicon substrate, and an ASIC chip is glued to the top of the MEMS chip. This design allows the MEMS chip to be suspended and not in direct contact with the packaging shell.

[0014] Optionally, the vertical projection of the porous array structure onto the package shell is located between the MEMS chip boundary projection and the edge of the isolation cavity. This isolates the mechanical stress transmitted from the package shell to the MEMS chip via the silicon substrate, while ensuring that the isolation system does not introduce other external interference factors that affect the performance of the MEMS chip, thereby achieving stress isolation between the package shell and the MEMS chip.

[0015] Optionally, the porous array structure is arranged in a ring in the silicon substrate surrounding the adhesive portion of the MEMS chip.

[0016] Optionally, the porous array structure is a honeycomb porous array structure, which is composed of a number of flat hexagonal through holes arranged in a row;

[0017] The porous array structure is set around the adhesive area of ​​the MEMS chip, and in each porous array structure, the length direction of the cross-section of the flat hexagonal through hole is parallel to the side of the MEMS chip.

[0018] In a second aspect, the present invention also provides a packaging method for the low-stress porous array packaging structure of the MEMS chip described in the first aspect, comprising the following steps:

[0019] (1) Fabrication of silicon substrates with porous array structures;

[0020] (2) Use adhesive to bond the MEMS chip to the center of the upper surface of the silicon substrate, and bond the ASIC chip to the center of the upper surface of the MEMS chip.

[0021] (3) Connect the pad of the MEMS chip and the pad of the ASIC chip with gold wire bonding to realize electrical signal interconnection;

[0022] (4) Use gold wire bonding to connect the Pad of the ASIC chip to the bonding area inside the package cavity to realize the interconnection of signals between the device and the outside.

[0023] (5) Adhere the silicon substrate to the packaging shell.

[0024] Optionally, the processing of the silicon substrate with the porous array structure includes the following steps:

[0025] a) Prepare single-crystal silicon wafers;

[0026] b) An isolation cavity is obtained by etching the bottom of the single-crystal silicon wafer;

[0027] c) Etch the outer periphery of the area where the MEMS chip is bonded on the single-crystal silicon wafer to obtain a porous array structure;

[0028] d) Etch and scribing grooves on the single-crystal silicon wafer according to the size requirements of the silicon substrate;

[0029] e) Dicing along the dicing groove to form a single silicon substrate.

[0030] Optionally, the structural stiffness of the honeycomb porous array structure can be adjusted by regulating the side length, included angle, and hole wall thickness of the flat hexagonal through-hole units in the honeycomb porous array structure, thereby providing sufficient stiffness for the MEMS chip bonding area.

[0031] Optionally, the porous array structure is a honeycomb porous array structure, which is composed of several flat hexagonal through holes arranged in layers; the porous array structure is respectively arranged around the adhesive area of ​​the MEMS chip, and in each porous array structure, the length direction of the cross-section of the flat hexagonal through hole is parallel to the side of the MEMS chip.

[0032] The stiffness adjustment method of the honeycomb porous array structure (61) includes: adjusting the structural parameters of the flat hexagonal through holes of the porous array structure (6) according to the following formula to change the structural stiffness k. x To achieve the structural stiffness requirement k:

[0033]

[0034] The length direction of the cross-section of the flat hexagonal through-hole is taken as the Y-axis, the direction perpendicular to the Y-axis and parallel to the cross-section of the flat hexagonal through-hole is taken as the X-axis, and the height direction of the flat hexagonal through-hole element is taken as the Z-axis; where k x F represents the equivalent stiffness of the flat hexagonal through-hole element along the X-axis. x The force acting on the flat hexagonal through-hole unit in the X-axis direction is represented by δ, which is the component of the encapsulation force in the X-axis direction. x E represents the equivalent strain along the X-axis on the hypotenuse of a single hole. m Let θ represent the Young's modulus of the material, θ be the angle between the hypotenuse of the single hole and the X-axis, and a, h, and t represent the hypotenuse length, single hole width, and hole wall thickness of the flat hexagonal through-hole unit, respectively; and we have:

[0035] F x =σ x ah, σ x This represents the stress in the X-axis direction experienced by a single hole, where l represents the length of the straight side; δ represents the deflection of the hypotenuse. I represents the moment of inertia of the flat hexagonal through-hole section.

[0036] By adjusting the structural stiffness, the product can provide sufficient strength to the MEMS chip and silicon substrate, while also releasing the stress between the package and the silicon substrate.

[0037] Optionally, the structural stiffness requirement k is determined according to the following formula:

[0038]

[0039] In the formula, m i c i k i and x i Let be the mass, damping coefficient, equivalent stiffness, and displacement of the i-th layer of flat hexagonal through-holes, respectively. x i The second and first differentials; m mass For the mass of the MEMS chip bonding area on the silicon substrate and the mass of the MEMS chip bonded thereon, a shock This refers to impact acceleration.

[0040] Beneficial effects

[0041] The present invention relates to a low-stress porous array packaging structure and method for MEMS chips. By etching an isolation cavity at the bottom of the silicon substrate, the contact area between the MEMS chip and the package shell is reduced, thereby reducing thermal stress and preventing abnormal deformation of the stress-sensitive MEMS structure. Simultaneously, the smaller bonding area achieves both mechanical fixation and reduces the bonding stress on the silicon substrate. Combined with the design of the porous array structure and the strength design method of the through-hole units, the present invention can provide sufficient strength for both the MEMS chip and the silicon substrate while simultaneously releasing stress between the package shell and the silicon substrate. Furthermore, the isolation cavity at the bottom of the silicon substrate also prevents adhesion to the bottom surface of the porous array structure due to excessive adhesive overflow from the bottom surface of the silicon substrate. Attached Figure Description

[0042] Figure 1 This is a traditional silicon substrate-based stacked MEMS chip packaging structure;

[0043] Figure 2 This is a cross-sectional view of the honeycomb array structure based on the present invention;

[0044] Figure 3 This is a top view of the silicon substrate based on the honeycomb array structure of the present invention;

[0045] Figure 4 This is a top view of the MEMS chip package based on a honeycomb array structure on a silicon substrate according to the present invention;

[0046] Figure 5 This is a schematic diagram of the honeycomb structure of the present invention;

[0047] Figure 6 The diagram shown is a simplified model of the honeycomb array structure of the present invention.

[0048] Figure 7 This is a diagram illustrating the fabrication steps of a silicon substrate based on a porous array, as described in the invention.

[0049] Figure 8 A schematic diagram of a silicon substrate based on a porous array structure according to the invention;

[0050] Figure 9 This is a schematic diagram of a silicon substrate based on a porous array structure.

[0051] In the figure: 1-package shell, 2-silicon substrate, 3-isolation cavity, 4-MEMS chip, 5-ASIC chip, 6-porous array structure, 61-honeycomb array structure, 7-adhesive, 8-gold wire bonding lead, 9-pad point of MEMS chip, 10-pad point of ASIC chip, 11-bonding area of ​​package shell. Detailed Implementation

[0052] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0053] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0054] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0055] Example 1

[0056] like Figure 2 , 4 As shown in Figures 8 and 9, this embodiment provides a low-stress porous array packaging structure for MEMS chips, characterized in that it includes a packaging shell 1 and a silicon substrate 2, with the bottom outer periphery of the silicon substrate 2 adhered to the inner bottom upper surface of the packaging shell 1.

[0057] refer to Figure 2 As shown, in this embodiment, an isolation cavity 3 is provided between the silicon substrate 2 and the packaging shell 1. The bottom surface of the silicon substrate 2 surrounding the isolation cavity 3 is bonded to the packaging shell 1. The height of the isolation cavity 3 is greater than the height of the adhesive layer between the silicon substrate 2 and the packaging shell 1. The silicon substrate 2 is provided with a porous array structure 6. The porous array structure 6 penetrates the silicon substrate 2 downward to connect the isolation cavity 3 with the external space.

[0058] The bottom of the silicon substrate 2 is etched with an isolation cavity 3, creating a step between the bottom of the silicon substrate 2 and the bottom surface of the porous array structure 6. It is then fixed to the bottom surface of the packaging shell 1 with annular adhesive. This small bonding area achieves mechanical fixation while reducing the adhesive stress on the silicon substrate 2. The step formation prevents excessive adhesive overflow from the bottom surface of the silicon substrate 2, which could lead to adhesion between it and the bottom surface of the porous array structure 6.

[0059] refer to Figure 2 As shown, a MEMS chip 4 is glued to the top of the silicon substrate 2, and an ASIC chip 5 is glued to the top of the MEMS chip 4, so that the MEMS chip 4 is in a suspended state and does not directly contact the packaging shell 1.

[0060] refer to Figure 2 As shown, the vertical projection of the porous array structure 6 onto the package shell 1 is located between the boundary projection of the MEMS chip 4 and the edge of the isolation cavity 3. The porous array structure 6 is arranged in a ring in the silicon substrate 2 on the outer periphery of the adhesive part of the MEMS chip 4.

[0061] The MEMS chip 4 is suspended and does not directly contact the package 1. The mechanical stress transmitted from the package 1 to the MEMS chip 4 is isolated by the silicon substrate 2. At the same time, the isolation system does not introduce other external interference factors that affect the performance of the MEMS chip 4, thus achieving stress isolation between the package 1 and the MEMS chip 4.

[0062] One embodiment, referenced Figure 4 As shown, the porous array structure 6 is a honeycomb porous array structure 61, which is composed of several flat hexagonal through holes. Porous array structures 6 are respectively set around the adhesive area of ​​MEMS chip 4. In each porous array structure 6, the length direction of the cross-section of the flat hexagonal through hole is parallel to the side of MEMS chip 4.

[0063] One embodiment, referenced Figure 8 As shown, the porous array structure 6 can also be formed by arranging or interleaving several elliptical through-hole units in a layered or staggered manner. The outer side of the elliptical array structure is attached to the bottom of the silicon substrate 2 and the adhesive area of ​​the packaging shell 1, and the inner side is attached to the top of the silicon substrate 2 and the adhesive area of ​​the MEMS chip 4.

[0064] One embodiment, referenced Figure 9 As shown, the porous array structure 6 can also be composed of several rings to form a circular array structure. The outer side of the circular array structure is attached to the bottom of the silicon substrate 2 and the adhesive area of ​​the packaging shell 1, and the inner side is attached to the top of the silicon substrate 2 and the adhesive area of ​​the MEMS chip 4.

[0065] When designing the porous array structure 6, a reasonable structural stiffness is selected. It can be designed as an array structure of other shapes such as flat hexagon, ellipse, polygon, etc. The array form can be a honeycomb array or a rectangular array, or it can be designed as a multi-ring structure. This allows the porous array structure 6 to effectively release the packaging stress between the package shell 1 and the silicon substrate 2 while meeting the requirements of the maximum allowable stress of the material.

[0066] The MEMS chip packaging structure of this embodiment has the advantages of simple structure, few processing steps, few special process requirements, and easy operation. It can achieve stress isolation between MEMS chip and packaging shell, and reduce the impact of packaging stress on MEMS chip structure.

[0067] Example 2

[0068] This embodiment describes a packaging method for the low-stress porous array packaging structure of MEMS chip 4 described in Embodiment 1, including the following steps:

[0069] (1) Fabrication of a silicon substrate 2 with a porous array structure 6;

[0070] (2) The MEMS chip 4 is bonded to the center of the upper surface of the silicon substrate 2 using adhesive, and the ASIC chip 5 is bonded to the center of the upper surface of the MEMS chip 4.

[0071] (3) Use gold wire 8 to bond the Pad9 of the MEMS chip to the Pad10 of the ASIC chip to realize electrical signal interconnection;

[0072] (4) Use gold wire 8 to bond the Pad10 of the ASIC chip to the bonding area 11 inside the package 1 to realize the interconnection of signals between the inside and outside of the device.

[0073] (5) Adhere the silicon substrate 2 to the encapsulation housing 1.

[0074] refer to Figure 7 As shown, the fabrication of the silicon substrate 2 with the porous array structure 6 includes the following steps:

[0075] a) Prepare single-crystal silicon wafers;

[0076] b) The bottom of the single-crystal silicon wafer is etched to obtain the isolation cavity 3;

[0077] c) Etch the outer periphery of the MEMS chip 4 part on the single crystal silicon wafer to obtain a porous array structure 6;

[0078] d) Etch and scribing grooves on the single-crystal silicon wafer according to the size requirements of silicon substrate 2;

[0079] e) Dicing along the dicing groove to form a single silicon substrate 2.

[0080] The silicon substrate 2 is first etched with an isolation cavity 3 on the bottom surface of a single crystal silicon wafer using a micro-etching process, and then a porous array structure 6 is processed on the top surface. After processing, it is diced to form a single silicon substrate 2.

[0081] refer to Figure 3 and Figure 5 As shown, by adjusting the side length, included angle, and hole wall thickness of the flat hexagonal through-hole unit in the honeycomb porous array structure 61, the structural stiffness of the honeycomb porous array structure 61 is adjusted, providing sufficient stiffness for the MEMS chip 4 bonding area. That is, the honeycomb porous array structure 61 can effectively release the packaging stress between the packaging shell 1 and the silicon substrate 2 while meeting the requirements of the maximum allowable stress of the material.

[0082] refer to Figure 2 , 3 As shown in Figures 4 and 5, taking a honeycomb-shaped porous array structure 61 as an example, the adjustment of the strength of the porous array structure is explained. Figure 4The honeycomb-shaped porous array structure is composed of several flat hexagonal through holes arranged in layers; porous array structures 6 are respectively set around the adhesive area of ​​MEMS chip 4, and in each porous array structure 6, the length direction of the cross-section of the flat hexagonal through hole is parallel to the side of MEMS chip 4.

[0083] refer to Figure 5 The length direction of the cross-section of the single flat hexagonal through-hole is taken as the Y-axis, the direction perpendicular to the Y-axis and parallel to the cross-section of the flat hexagonal through-hole is taken as the X-axis, and the height direction of the flat hexagonal through-hole unit is taken as the Z-axis. The single-cell honeycomb structure exhibits low stiffness in its sensitive X-direction, while its stiffness is high in its non-sensitive Y-direction and Z-direction. Therefore, Figure 5 The silicon substrate with a honeycomb array structure designed based on this shape has low stiffness in its XOY plane, but high stiffness in the Z direction perpendicular to the plane. The tensile or compressive micro-deformation of the in-plane porous honeycomb array structure can effectively release the in-plane packaging stress from the package housing and the silicon substrate. The bending deformation of the honeycomb cell sidewalls can release the Z-direction packaging stress from the package housing and the silicon substrate. Simultaneously, it provides sufficient stiffness to the MEMS chip bonding area in the vertical direction, enabling effective external environment sensing without reducing the intensity of the MEMS chip's external environment sensing due to the quasi-suspended long-beam structure of the silicon substrate.

[0084] The reasoning process for adjusting the stiffness of the honeycomb porous array structure 61 is as follows.

[0085] Taking the hypotenuse AB of the honeycomb array structure 61 as the object, since the honeycomb unit is subjected to the X-axis stress σ x This causes beam AB to undergo elastic deformation. Assuming the Young's modulus of the structural material is Em, the side length of the AB surface of the hole is a, the width is h, and the thickness is t, and θ is the angle between the AB surface and the X-axis, then the bending moment M on the AB surface is calculated as follows:

[0086]

[0087] The deflection δ of side AB is calculated as follows:

[0088]

[0089] in, I represents the moment of inertia of the flat hexagonal through-hole section; F x =σ x ah, F x This represents the force acting on the flat hexagonal through-hole unit in the X-axis direction, i.e., the component of the encapsulation force in the X-axis direction;

[0090] Calculate the equivalent strain ε in the X-axis direction produced by surface AB. x for:

[0091]

[0092] According to the definition of stiffness, the equivalent stiffness along the X-axis of a single honeycomb structure can be simplified as follows:

[0093]

[0094] As shown above, once the structural parameters of a single hole are determined, its stiffness can be determined. Therefore, in practical applications, the structural parameters of the single hole can be adjusted according to the stiffness requirements to ensure that the stiffness meets the requirements. The side length a, wall thickness t, and bending angle θ of the single hole structural parameters can be comprehensively designed in conjunction with the sensor's accuracy, resonant frequency, actual usage environment, and impact resistance requirements to achieve a stress isolation structure design that meets the actual usage environment and needs.

[0095] Combination Figure 6 Through analysis of the porous array structure within the silicon substrate, the relationship between elastic deformation and structural stiffness can be simplified as follows:

[0096]

[0097] In the above formulas, m i c i k i and x i Let be the mass, damping coefficient, equivalent stiffness, and displacement of the i-th layer of flat hexagonal through-holes, respectively. x i The second and first differentials; m mass For the mass of the MEMS chip bonding area on the silicon substrate and the mass of the MEMS chip bonded thereon, a shock This refers to impact acceleration.

[0098] From equation (5), we can see that the displacement x i The equivalent stiffness of the cellular structure is directly related to the environmental parameters of the porous array structure. When the environmental parameters of the porous array structure can be determined, the stiffness requirements of each single-hole unit in the porous array structure can be determined accordingly. Then, according to Equation (4), by adjusting the wall thickness, wall length and structural angle of the structure, the structural stiffness of each single-hole unit can be changed to meet the corresponding stiffness requirements. This realizes the stiffness adjustment of the porous array structure under different packaging environmental parameters for the low-stress porous array packaging structure of MEMS chips.

[0099] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A MEMS chip low-stress porous array package structure, characterized by: The package includes a package shell (1) and a silicon substrate (2). The bottom outer periphery of the silicon substrate (2) is glued to the bottom upper surface of the package shell (1). A MEMS chip (4) is glued to the top of the silicon substrate (2), and an ASIC chip (5) is glued to the top of the MEMS chip (4). An isolation cavity (3) is provided between the silicon substrate (2) and the packaging shell (1). The bottom surface of the silicon substrate (2) surrounding the isolation cavity (3) is bonded to the packaging shell (1). The height of the isolation cavity (3) is greater than the height of the adhesive layer between the silicon substrate (2) and the packaging shell (1), so that a step is generated between the bottom of the silicon substrate (2) and the bottom surface of the porous array structure (6). The silicon substrate (2) is provided with a porous array structure (6), which extends downward through the silicon substrate (2) to connect the isolation cavity (3) with the external space; The vertical projection of the porous array structure (6) onto the package shell (1) is located between the boundary projection of the MEMS chip (4) and the edge of the isolation cavity (3); The porous array structure (6) is a honeycomb porous array structure (61), which is composed of several flat hexagonal through holes. The porous array structure (6) is set around the adhesive area of ​​the MEMS chip (4). In each porous array structure (6), the length direction of the cross-section of the flat hexagonal through hole is parallel to the side of the MEMS chip (4). By adjusting the structural parameters of the flat hexagonal through holes of the porous array structure (6) to change the structural stiffness , so as to meet the structural stiffness requirement ; the structural stiffness requirement of the porous array structure is determined according to the following formula: ， wherein, , , and are the mass, damping coefficient, equivalent stiffness and displacement of the first layer flat hexagonal via, respectively; , are the second order differential and first order differential of , respectively; are the mass of the MEMS chip die attach area of the silicon substrate and the MEMS chip attached thereto, and is the impact acceleration.

2. The low-stress porous array packaging structure for MEMS chips according to claim 1, characterized in that: The method for adjusting the rigidity of the honeycomb porous array structure (61) comprises adjusting the structural parameters of the flat hexagonal through holes of the porous array structure (6) according to the following formula to change the structural rigidity , so as to meet the requirement of structural rigidity . ， The length direction of the cross-section of the flat hexagonal through-hole is taken as the Y-axis direction, the direction perpendicular to the Y-axis and parallel to the cross-section of the flat hexagonal through-hole is taken as the X-axis direction, and the height direction of the flat hexagonal through-hole element is taken as the Z-axis direction; where, This represents the equivalent stiffness of the flat hexagonal through-hole element along the X-axis. This represents the force acting on the flat hexagonal through-hole unit in the X-axis direction, which is the component of the encapsulation force in the X-axis direction. This indicates the equivalent strain along the X-axis on the hypotenuse of a single hole. This indicates the Young's modulus of the material. The angle between the hypotenuse of the single hole and the X-axis direction. , , Let these represent the hypotenuse length, single hole width, and hole wall thickness of the flat hexagonal through-hole unit, respectively; and we have: , This represents the stress in the X-axis direction experienced by a single hole, where l represents the length of the straight side; , This represents the deflection of the hypotenuse. , This represents the moment of inertia of a flat hexagonal through-hole section.

3. A packaging method for a low-stress porous array packaging structure for MEMS chips as described in claim 1 or 2, characterized in that: Includes the following steps: (1) Fabrication of a silicon substrate (2) with a porous array structure; (2) The MEMS chip (4) is bonded to the center of the upper surface of the silicon substrate (2) using adhesive, and the ASIC chip (5) is bonded to the center of the upper surface of the MEMS chip (4); (3) Use gold wire (8) to bond the Pad (9) of the MEMS chip to the Pad (10) of the ASIC chip to realize electrical signal interconnection; (4) Use gold wire (8) to bond the Pad (10) of the ASIC chip to the bonding area (11) inside the package (1) to realize the interconnection of signals between the inside and outside of the device; (5) Adhere the silicon substrate (2) into the packaging shell (1).

4. The packaging method according to claim 3, characterized in that: The processing of the silicon substrate (2) with the porous array structure includes the following steps: a) Prepare single-crystal silicon wafers; b) The bottom of the single-crystal silicon wafer is etched to obtain the isolation cavity (3); c) Etch the outer periphery of the area where the MEMS chip (4) is bonded on the single-crystal silicon wafer to obtain a porous array structure (6); d) Etch grooves on the single-crystal silicon wafer according to the size requirements of the silicon substrate (2); e) Dicing along the dicing groove to form a single silicon substrate (2).

5. The packaging method according to claim 3, characterized in that: Before step c), the side length, included angle and hole wall thickness of the flat hexagonal through-hole unit in the honeycomb porous array structure (61) are calculated to adjust the structural stiffness of the honeycomb porous array structure and provide sufficient stiffness for the MEMS chip (4) bonding area. Step c) Based on the calculated side length, included angle and hole wall thickness of the flat hexagonal through hole unit, etch to obtain a porous array structure (6).

Images