SPAD control circuit, SPAD array and laser ranging device

Abstract

The present invention discloses a SPAD control circuit, a SPAD array and a laser ranging device, which relate to the field of circuit design, and include a first current source, a second current source, a capacitor and a first inverting unit. After the SPAD is triggered by a photon to generate an avalanche current, based on the characteristic that the voltage at both ends of the capacitor cannot change suddenly, the voltage of the SPAD cathode and the voltage of the second end of the capacitor both rapidly decrease, and the output end of the SPAD control circuit outputs a high level, which is the start time of the dead time. At the same time, the second current source charges the second end of the capacitor, and when the voltage at the second end of the capacitor reaches the flip voltage of the first inverting unit, the output end of the first inverting unit, that is, the output end of the SPAD control circuit, outputs a low level, which is the end time of the dead time. The present invention can provide a dead time for the SPAD and does not need to set a complex level shifting circuit between the SPAD and the first inverting unit, which can reduce the chip area.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, and in particular to a SPAD control circuit, a SPAD array and a laser ranging device. Background Art

[0002] The laser ranging device usually includes a SPAD (Single Photo Avalanche Diode) and a control circuit. After the SPAD detects a photon, an avalanche current is generated. In order for the SPAD to perform the next photon detection normally, the control circuit needs to quench the avalanche current. The time for quenching the avalanche current is called the dead time. The control circuit is usually composed of an analog circuit and a digital circuit, but the operating voltage of the analog circuit is usually higher than the operating voltage of the digital circuit. When the analog circuit transmits voltage to the digital circuit, digital components such as MOS tubes in the digital circuit may be damaged due to excessive voltage. Therefore, it is necessary to set a level shift circuit for converting high voltage to low voltage between the analog circuit and the digital circuit in the control circuit. The structure of the level shift circuit in the prior art is relatively complex, and the chip area occupied is relatively large, which is not conducive to the miniaturization of the chip. Summary of the invention

[0003] The object of the present invention is to provide a SPAD control circuit, a SPAD array and a laser ranging device, which can provide a dead time for the SPAD and do not need to set up a complex level shift circuit, thereby reducing the chip area.

[0004] In order to solve the above technical problems, the present invention provides a SPAD control circuit, comprising a first current source, a second current source, a capacitor and a first inverting unit;

[0005] An input end of the first current source is connected to a first power supply, and an input end of the second current source is connected to a second power supply, wherein an output voltage of the first power supply is higher than an output voltage of the second power supply;

[0006] The output end of the first current source is respectively connected to the first end of the capacitor and the cathode of the SPAD, the anode of the SPAD is connected to a third power supply, wherein the third power supply is used to provide a negative voltage for reverse breakdown for the SPAD, the second end of the capacitor is respectively connected to the output end of the second current source and the input end of the first inverting unit, the output end of the first inverting unit is the output end of the SPAD control circuit, and the power supply end of the first inverting unit is connected to the second power supply.

[0007] Preferably, the first inverting unit is a Schmitt trigger;

[0008] The input end of the Schmitt trigger serves as the input end of the first inverting unit, and the output end of the Schmitt trigger serves as the output end of the first inverting unit.

[0009] Preferably, the first current source is a first MOS transistor, and the second current source is a second MOS transistor;

[0010] The control end of the first MOS transistor is connected to the first bias voltage, the input end of the first MOS transistor is the input end of the first current source, and the output end of the first MOS transistor is the output end of the first current source;

[0011] The control end of the second MOS tube is connected to the second bias voltage, the input end of the second MOS tube is the input end of the second current source, and the output end of the second MOS tube is the output end of the second current source.

[0012] Preferably, a third MOS tube is further included, which is used to pull down the voltage of the cathode of the SPAD after the SPAD is triggered by photons and generates an avalanche current, so that the SPAD is out of the avalanche state;

[0013] The input end of the third MOS tube is connected to the cathode of the SPAD, the output end of the third MOS tube is grounded, and the control end of the third MOS tube is connected to the output end of the first inverting unit.

[0014] Preferably, it also includes:

[0015] The charging circuit connected to the cathode of the SPAD is used to quickly charge the SPAD after the SPAD is triggered by a photon and generates an avalanche current, so that the SPAD is triggered when a photon is input next time.

[0016] Preferably, the charging circuit includes a fourth MOS tube, a second inverting unit, a NOR gate, a delay unit and a third inverting unit;

[0017] The input end of the third inverting unit is connected to the output end of the first inverting unit, the output end of the third inverting unit is connected to the input end of the delay unit, the output end of the delay unit is connected to the first input end of the NOR gate, and the second input end of the NOR gate is connected to the output end of the first inverting unit;

[0018] The output end of the NOR gate is connected to the input end of the second inverting unit, the output end of the second inverting unit is connected to the control end of the fourth MOS tube, the input end of the fourth MOS tube is connected to the first power supply, the output end of the fourth MOS tube is connected to the cathode of the SPAD, the power supply end of the second inverting unit is connected to the first power supply, and the power supply end of the NOR gate, the power supply end of the delay unit and the power supply end of the third inverting unit are all connected to the second power supply.

[0019] Preferably, the second inverting unit includes NMOS and PMOS, and the third inverting unit is a NOT gate;

[0020] The gate of the NMOS is connected to the gate of the PMOS, and the common end of the connections is used as the input end of the second inverting unit; the drain of the NMOS is connected to the drain of the PMOS, and the common end of the connections is used as the output end of the second inverting unit; the source of the PMOS is connected to the first power supply, and the source of the NMOS is grounded;

[0021] The input end of the NOT gate serves as the input end of the third inverting unit, and the output end of the NOT gate serves as the output end of the third inverting unit.

[0022] In order to solve the above technical problem, the present invention also provides a SPAD array, comprising N of the above SPAD control circuits, and N SPADs, wherein N is a positive integer;

[0023] The output ends of the first current sources in the N SPAD control circuits are respectively connected to the cathodes of the N SPADs in a one-to-one correspondence, and the anodes of the N SPADs are connected to a third power supply, wherein the third power supply is used to provide a negative voltage for reverse breakdown for the SPADs.

[0024] In order to solve the above technical problem, the present invention also provides a laser ranging device, including the above SPAD array.

[0025] In summary, the present invention provides a SPAD control circuit, a SPAD array and a laser ranging device, comprising a first current source, a second current source, a capacitor and a first inverting unit. The output end of the first current source is connected to the cathode of the SPAD, the output end of the second current source is connected to the input end of the first inverting unit, and a capacitor is arranged between the output end of the first current source and the output end of the second current source. Therefore, when the SPAD is triggered by a photon to generate an avalanche current, based on the characteristic that the voltage across the capacitor cannot change suddenly, the voltage of the cathode of the SPAD becomes low, and the voltage of the input end of the first inverting unit also rapidly decreases, and the voltage of the output end of the SPAD control circuit becomes a high level, which is the start time of the dead time. At the same time, the second current source charges the second end of the capacitor. When the voltage of the second end of the capacitor reaches the flip voltage of the first inverting unit, the first inverting unit outputs a low level, and the voltage of the output end of the SPAD control circuit becomes a low level, which is the end time of the dead time. Therefore, the dead time can be provided normally for the SPAD and there is no need to set a complex level shifting circuit between the SPAD and the first inverting unit, thereby reducing the chip area and facilitating chip miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic diagram of the structure of a SPAD control circuit provided by the present invention;

[0028] Figure 2 A schematic diagram of the structure of another SPAD control circuit provided by the present invention;

[0029] Figure 3 A schematic diagram of the structure of another SPAD control circuit provided by the present invention;

[0030] Figure 4 A schematic diagram of the structure of another SPAD control circuit provided by the present invention;

[0031] Figure 5 A schematic diagram of the circuit structure of a Schmitt trigger provided in this application. DETAILED DESCRIPTION

[0032] The core of the present invention is to provide a SPAD control circuit, a SPAD array and a laser ranging device, which can provide dead time for the SPAD and do not need to set up a complex level shift circuit, thereby reducing the chip area.

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a SPAD control circuit provided by the present invention, the SPAD control circuit includes a first current source I1, a second current source I2, a capacitor C1 and a first inverting unit INV1;

[0035] An input end of the first current source I1 is connected to a first power supply, and an input end of the second current source I2 is connected to a second power supply, wherein an output voltage of the first power supply is higher than an output voltage of the second power supply;

[0036] The output end of the first current source I1 is respectively connected to the first end of the capacitor C1 and the cathode of the SPAD, the anode of the SPAD is connected to the third power supply, wherein the third power supply is used to provide a negative voltage for reverse breakdown for the SPAD, the second end of the capacitor C1 is respectively connected to the output end of the second current source I2 and the input end of the first inverting unit INV1, the output end of the first inverting unit INV1 is the output end of the SPAD control circuit, and the power supply end of the first inverting unit INV1 is connected to the second power supply.

[0037] The SPAD control circuit usually includes both analog circuits and digital circuits, but the operating voltage of the analog circuit is usually higher than that of the digital circuit. For example, the operating voltage of the analog circuit is 3.3V, and the operating voltage of the digital circuit is 1.1V. Therefore, an additional level shifting circuit needs to be set between the analog circuit and the digital circuit. However, the level shifting circuits in the prior art are generally more complicated and occupy a larger chip area.

[0038] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a SPAD control circuit provided by the present invention, Figure 1The SPAD node in represents the cathode of SPAD, the Holdoff node is the second end of the capacitor, that is, the input end of the first inverting unit INV1, the SPAD_Out node represents the output end of the SPAD control circuit, VCC represents the first power supply, VDD represents the second power supply, and -VOP represents the third power supply. In order to solve the above technical problems, the present application provides a SPAD control circuit. The analog device in the SPAD control circuit in the present application refers to SPAD, and the digital device refers to the first inverting unit INV1. The present application sets a capacitor C1 between the cathode of SPAD and the input end of the first inverting unit INV1. On the one hand, the capacitor C1 has the characteristic that the voltage at both ends cannot change suddenly, so it can realize the function of the level shift circuit for voltage conversion between SPAD and the first inverting unit INV1; on the other hand, the volume of the capacitor C1 is relatively small, which can reduce the chip area occupied by the level shift circuit, and is more conducive to realizing chip miniaturization.

[0039] It should be noted that, in the present application, the first current source I1 is used to power the analog device, i.e., the SPAD, and the second current source I2 is used to power the digital device, i.e., the first inverting unit INV1, so that the consistency of the gain of the SPAD array can be increased. In addition, considering that the operating voltage of the SPAD is higher than the operating voltage of the first inverting unit INV1, the output voltage of the first power supply powering the first current source I1 connected to the SPAD is higher than the output voltage of the second power supply powering the second current source I2 connected to the first inverting unit INV1. For example, the output voltage of the first power supply is 3.3V, and the output voltage of the second power supply is 1.1V.

[0040] At the same time, the SPAD control circuit in the present application can realize the basic function of providing dead time for SPAD. Specifically, when the SPAD is triggered by photons to generate avalanche current, the cathode voltage of the SPAD and the voltage of the first end of the capacitor C1 drop. At the same time, since the voltage across the capacitor C1 cannot change suddenly, the voltage of the second end of the capacitor C1 and the input end of the first inverting unit INV1 drops. The first inverting unit INV1 inverts the input end and outputs a high level. This is the start time of the dead time provided by the SPAD control circuit. Due to the action of the second current source I2, the voltage of the second end of the capacitor C1 and the voltage of the input end of the first inverting unit INV1 will gradually rise. When the voltage of the input end of the first inverting unit INV1 rises to the flip voltage of the first inverting unit INV1, the first inverting unit INV1 outputs a low level. This is the end time of the dead time provided by the SPAD control circuit.

[0041] It can be seen that the SPAD control circuit provided in the present application can reduce the area occupied by the level shifting circuit between the analog circuit and the digital circuit when the chip area is limited, and at the same time can meet the requirement of providing dead time for the SPAD.

[0042] In addition, the output voltage of the third power supply connected to the cathode of the SPAD in the present application is a negative voltage. In fact, the output voltage of the third power supply connected to the cathode of the SPAD can also be a positive voltage. However, when the output voltage of the third power supply is a positive voltage, the circuit structure of the SPAD control circuit should also be adjusted accordingly. Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of another SPAD control circuit provided by the present invention, wherein the SPAD node represents the cathode of the SPAD, the Holdoff node is the second end of the capacitor, i.e., the input end of the first inverting unit INV1, the SPAD_Out node represents the output end of the SPAD control circuit, VCC represents the first power supply, VDD represents the second power supply, and +VOP represents the third power supply. Specifically, the cathode of the SPAD is connected to the output end of the third power supply whose output voltage is a positive voltage, the anode of the SPAD is connected to the input end of the first current source I1 and the first end of the capacitor C1, the second end of the capacitor C1 is connected to the input end of the first inverting unit INV1, the output end of the first current source I1 and the output end of the second current source I2 are both grounded, and the output end of the first inverting unit INV1 is the output end of the SPAD control circuit.

[0043] In summary, the SPAD control circuit provided by the present invention includes a first current source I1, a second current source I2, a capacitor C1 and a first inverting unit INV1. After the SPAD is triggered by a photon to generate an avalanche current, based on the characteristic that the voltage across the capacitor C1 cannot change suddenly, the voltage of the SPAD cathode and the voltage of the second end of the capacitor C1 both rapidly decrease, and the output end of the SPAD control circuit outputs a high level, which is the start time of the dead time. At the same time, the second current source I2 charges the second end of the capacitor C1. When the voltage at the second end of the capacitor C1 reaches the flip voltage of the first inverting unit INV1, the output end of the first inverting unit INV1, that is, the output end of the SPAD control circuit, outputs a low level, which is the end time of the dead time. The present invention can provide a dead time for SPAD and does not require a complex level shifting circuit to be set between the SPAD and the first inverting unit INV1, which can reduce the chip area.

[0044] Based on the above embodiments:

[0045] As a preferred embodiment, the first inverting unit INV1 is a Schmitt trigger;

[0046] The input end of the Schmitt trigger serves as the input end of the first inverting unit INV1 , and the output end of the Schmitt trigger serves as the output end of the first inverting unit INV1 .

[0047] Taking into account that in the process of the SPAD control circuit providing dead time, when the voltage at the input end of the first inverting unit INV1 gradually rises due to the action of the second current source I2, the input voltage of the first inverting unit INV1 usually jitters, and the problem of false flipping may occur when the flipping voltage at the falling edge of the first inverting unit INV1 is relatively large.

[0048] Therefore, in this application, a Schmitt trigger is selected as the first inverting unit INV1, please refer to Figure 5 , Figure 5 A schematic diagram of the circuit structure of a Schmitt trigger provided in this application, Figure 5 Where Vin is the input voltage of the Schmitt trigger, Vout is the output voltage of the Schmitt trigger, VDD is the second power supply, GND is the ground terminal, PM5 is PMOS, and NM3, NM6 and NM7 are all NMOS. The flip voltage of the falling edge of the Schmitt trigger is relatively low, so it is not easy to cause the problem of false flipping due to the jitter of the voltage at the input terminal of the first inverting unit INV1. In addition, as a digital circuit, the power supply terminal of the Schmitt trigger is connected to the second power supply.

[0049] For example, the flip voltage of the rising edge of the Schmitt trigger is set to 0.8V, and the flip voltage of the falling edge is set to 0.4V. When the voltage at the input end of the first inverting unit INV1 fluctuates to 0.5V, the flip voltage is set relatively low and therefore there is no problem of false flipping. When the second current source I2 charges the voltage at the input end of the first inverting unit INV1 to 0.8V, the output voltage of the first inverting unit INV1 becomes a high level, thereby ensuring the reliability of the SPAD control circuit.

[0050] As a preferred embodiment, the first current source I1 is a first MOS transistor M1, and the second current source I2 is a second MOS transistor M2;

[0051] The control end of the first MOS transistor M1 is connected to the first bias voltage, the input end of the first MOS transistor M1 is the input end of the first current source I1, and the output end of the first MOS transistor M1 is the output end of the first current source I1;

[0052] The control end of the second MOS tube M2 is connected to the second bias voltage, the input end of the second MOS tube M2 is the input end of the second current source I2, and the output end of the second MOS tube M2 is the output end of the second current source I2.

[0053] Please refer to Figure 3 , Figure 3 A structural schematic diagram of another SPAD control circuit provided by the present invention, VCC represents a first power supply, VDD represents a second power supply, -VOP represents a third power supply, in this embodiment, -VOP is -28V, the SPAD node represents the cathode of the SPAD, the Holdoff node is the second end of the capacitor, that is, the input end of the first inverting unit INV1, the SPAD_Out node represents the output end of the SPAD control circuit, BIAS1 represents a first bias voltage, and BIAS2 represents a second bias voltage.

[0054] In this embodiment, a MOS tube is selected as a current source for powering the SPAD and the first inverting unit INV1. Specifically, the first current source I1 is a first MOS tube M1, and the control end of the first MOS tube M1 is connected to the first bias voltage. The current of the first MOS tube M1 can be controlled by adjusting the level of the first bias voltage, that is, the current charging the SPAD can be controlled. The input end of the first MOS tube M1 is the input end of the first current source I1 connected to the output end of the first power supply, and the output end of the first MOS tube M1 is the output end of the first current source I1 connected to the cathode of the SPAD.

[0055] The second current source I2 is a second MOS tube M2, and the control end of the second MOS tube M2 is connected to the second bias voltage. The current of the second MOS tube M2 can be controlled by adjusting the second bias voltage, that is, the current for holdoff charging can be controlled. The input end of the second MOS tube M2 is the input end of the second current source I2 connected to the output end of the second power supply, and the output end of the second MOS tube M2 is the output end of the second current source I2 connected to the input end of the first inverting unit INV1, that is, the holdoff node.

[0056] In addition, in this embodiment, the first MOS transistor M1 may be a PMOS, and the second MOS transistor M2 may be a PMOS.

[0057] As a preferred embodiment, it further includes a third MOS tube M3, which is used to pull down the voltage of the cathode of the SPAD after the SPAD is triggered by photons and generates an avalanche current, so that the SPAD can leave the avalanche state;

[0058] An input end of the third MOS tube M3 is connected to the cathode of the SPAD, an output end of the third MOS tube M3 is grounded, and a control end of the third MOS tube M3 is connected to the output end of the first inverting unit INV1.

[0059] Please refer to Figure 4 , Figure 4A structural schematic diagram of another SPAD control circuit provided by the present invention, VCC represents a first power supply, VDD represents a second power supply, a SPAD node represents a cathode of the SPAD, a Holdoff node is a second end of the capacitor, i.e., an input end of a first inverting unit INV1, a SPAD_Out node represents an output end of the SPAD control circuit, BIAS1 represents a first bias voltage, and BIAS2 represents a second bias voltage.

[0060] Considering that when the SPAD is triggered by the current photon, an avalanche current will be generated, and the SPAD can only perform the next photon detection normally after the avalanche current is quenched, in order to shorten the time of quenching the avalanche current, in the present application, the third MOS tube M3 connected to the cathode of the SPAD, the control end of the third MOS tube M3 is connected to the output end of the first inverting unit INV1, and the output end of the third MOS tube M3 is grounded. After adding the third MOS tube M3, the voltage of the cathode of the SPAD is forced to be quickly pulled down, so that the SPAD quickly leaves the avalanche state, thereby avoiding damage to the SPAD and ensuring the reliability of the SPAD control circuit.

[0061] At the same time, since the third MOS tube M3 forces the voltage of the cathode of the SPAD to be pulled down so that the potential of the first end of the capacitor C1 remains at a low level, the second current source I2 continues to charge the capacitor C1 so that the potential of the second end of the capacitor C1, that is, the potential of the input end of the first inverting unit INV1, rises slowly, and thus the time that the SPAD control circuit outputs a high level is increased.

[0062] As a preferred embodiment, it also includes:

[0063] The charging circuit connected to the cathode of the SPAD is used to quickly charge the SPAD after the SPAD is triggered by a photon and generates an avalanche current, so that the SPAD can be triggered in time when there is a photon input next time.

[0064] Considering that the SPAD needs to operate at a breakdown voltage when using it for photon detection, in order to enable the SPAD to perform the next photon detection normally after being triggered by a photon, in this embodiment, a charging circuit is used to quickly charge the SPAD after the SPAD is triggered by a photon and generates an avalanche current, thereby preparing for the next photon detection by the SPAD, and further ensuring the accuracy and reliability of photon detection.

[0065] As a preferred embodiment, the charging circuit includes a fourth MOS tube M4, a second inverting unit I2, a NOR gate I4, a delay unit I5 and a third inverting unit I3;

[0066] The input end of the third inverting unit I3 is connected to the output end of the first inverting unit INV1, the output end of the third inverting unit I3 is connected to the input end of the delay unit I5, the output end of the delay unit I5 is connected to the first input end of the NOR gate I4, and the second input end of the NOR gate I4 is connected to the output end of the first inverting unit INV1;

[0067] The output end of the NOR gate I4 is connected to the input end of the second inverting unit I2, the output end of the second inverting unit I2 is connected to the control end of the fourth MOS tube M4, the input end of the fourth MOS tube M4 is connected to the first power supply, the output end of the fourth MOS tube M4 is connected to the cathode of the SPAD, the power supply end of the second inverting unit I2 is connected to the first power supply, and the power supply end of the NOR gate I4, the power supply end of the delay unit I5 and the power supply end of the third inverting unit I3 are all connected to the second power supply.

[0068] Please refer to Figure 4 , Figure 4 A schematic structural diagram of another SPAD control circuit provided by the present invention.

[0069] In this embodiment, the charging circuit for charging the SPAD after the SPAD is triggered by photons to generate an avalanche current includes a fourth MOS tube M4, a second inverting unit I2, an NOR gate I4, a delay unit I5, and a third inverting unit I3. The third inverting unit I3 is connected to the output end of the first inverting unit INV1, that is, the output end of the SPAD control circuit, one input end of the NOR gate I4 is the signal after the level of the output end of the SPAD control circuit is flipped and delayed, and the other input end of the NOR gate I4 is directly the level of the output end of the SPAD control circuit, and the output end of the NOR gate I4 is connected to the input end of the second inverting unit I2. The specific structure of the second inverting unit I2 is not particularly limited in this application, and then the output end of the second inverting unit I2 is connected to the control end of the fourth MOS gate to control whether to pull up the potential of the cathode of the SPAD, that is, whether to charge the SPAD.

[0070] In addition, the NOR gate I4, the delay unit I5 and the third inverting unit I3 in this embodiment are all digital devices, so the power supply end of the NOR gate I4, the power supply end of the delay unit I5 and the power supply end of the third inverting unit I3 are all connected to the second power supply.

[0071] As a preferred embodiment, the second inverting unit I2 includes NMOS and PMOS, and the third inverting unit I3 is a NOT gate;

[0072] The gate of the NMOS is connected to the gate of the PMOS and the common end of the connections is used as the input end of the second inverting unit I2, the drain of the NMOS is connected to the drain of the PMOS and the common end of the connections is used as the output end of the second inverting unit I2, the source of the PMOS is connected to the first power supply, and the source of the NMOS is grounded;

[0073] The input end of the NOT gate serves as the input end of the third inverting unit I3, and the output end of the NOT gate serves as the output end of the third inverting unit I3.

[0074] The inverting unit usually has a variety of implementation structures. In this embodiment, the second inverting unit I2 is composed of NMOS and PMOS, and the third inverting unit I3 is a NOT gate. Specifically, the gate of the NMOS in the second inverting unit I2 is connected to the gate of the PMOS and the common end of the connection is used as the input end of the second inverting unit I2, the drain of the NMOS is connected to the drain of the PMOS and the common end of the connection is used as the output end of the second inverting unit I2, the source of the PMOS is connected to the first power supply as the power supply end of the second inverting unit I2, and the source of the NMOS is grounded. The input end of the NOT gate is used as the input end of the third inverting unit I3, and the output end of the NOT gate is used as the output end of the third inverting unit I3. Further optimize the circuit structure of the SPAD control circuit, better realize the control function of the SPAD, and ensure the accuracy and reliability of photon detection.

[0075] In order to solve the above technical problem, the present invention also provides a SPAD array, comprising N of the above SPAD control circuits, and N SPADs, wherein N is a positive integer;

[0076] The output ends of the first current sources I1 in the N SPAD control circuits are respectively connected to the cathodes of the N SPADs in a one-to-one correspondence, and the anodes of the N SPADs are connected to the third power supply, wherein the third power supply is used to provide a negative voltage for reverse breakdown for the SPADs.

[0077] For the relevant introduction of a SPAD array provided by the present invention, please refer to the above-mentioned embodiment of the SPAD control circuit, and this application will not go into details here.

[0078] In order to solve the above technical problem, the present invention also provides a laser ranging device, including the above SPAD array.

[0079] For the relevant introduction of a laser ranging device provided by the present invention, please refer to the above-mentioned embodiment of the SPAD control circuit, and this application will not go into details here.

[0080] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0081] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0082] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SPAD control circuit, characterized in that: It includes a first current source, a second current source, a capacitor and a first inverting unit; An input end of the first current source is connected to a first power supply, and an input end of the second current source is connected to a second power supply, wherein an output voltage of the first power supply is higher than an output voltage of the second power supply; The output end of the first current source is respectively connected to the first end of the capacitor and the cathode of the SPAD, the anode of the SPAD is connected to the third power supply, the second end of the capacitor is respectively connected to the output end of the second current source and the input end of the first inverting unit, the power supply end of the first inverting unit is connected to the second power supply, the output end of the first inverting unit is the output end of the SPAD control circuit, wherein the third power supply is used to provide a negative voltage for reverse breakdown for the SPAD; When the SPAD is triggered by photons to generate avalanche current, the cathode voltage of the SPAD and the voltage of the first end of the capacitor drop, and the voltage of the second end of the capacitor and the input end of the first inverting unit drop, and the first inverting unit inverts the input end and outputs a high level; the second current source charges the second end of the capacitor, and when the voltage of the second end of the capacitor reaches the flipping voltage of the first inverting unit, the first inverting unit outputs a low level.

2. The SPAD control circuit according to claim 1, characterized in that: The first inverting unit is a Schmitt trigger; The input end of the Schmitt trigger serves as the input end of the first inverting unit, and the output end of the Schmitt trigger serves as the output end of the first inverting unit.

3. The SPAD control circuit according to claim 1, characterized in that: The first current source is a first MOS transistor, and the second current source is a second MOS transistor; The control end of the first MOS transistor is connected to the first bias voltage, the input end of the first MOS transistor is the input end of the first current source, and the output end of the first MOS transistor is the output end of the first current source; The control end of the second MOS tube is connected to the second bias voltage, the input end of the second MOS tube is the input end of the second current source, and the output end of the second MOS tube is the output end of the second current source.

4. The SPAD control circuit according to claim 1, characterized in that: Also includes: A third MOS tube is used to pull down the voltage of the cathode of the SPAD after the SPAD is triggered by photons and generates an avalanche current, so that the SPAD is out of the avalanche state; The input end of the third MOS tube is connected to the cathode of the SPAD, the output end of the third MOS tube is grounded, and the control end of the third MOS tube is connected to the output end of the first inverting unit.

5. The SPAD control circuit according to any one of claims 1 to 4, characterized in that: Also includes: The charging circuit connected to the cathode of the SPAD is used to quickly charge the SPAD after the SPAD is triggered by a photon and generates an avalanche current, so that the SPAD is triggered when a photon is input next time.

6. The SPAD control circuit according to claim 5, characterized in that: The charging circuit includes a fourth MOS tube, a second inverting unit, a NOR gate, a delay unit and a third inverting unit; The input end of the third inverting unit is connected to the output end of the first inverting unit, the output end of the third inverting unit is connected to the input end of the delay unit, the output end of the delay unit is connected to the first input end of the NOR gate, and the second input end of the NOR gate is connected to the output end of the first inverting unit; The output end of the NOR gate is connected to the input end of the second inverting unit, the output end of the second inverting unit is connected to the control end of the fourth MOS tube, the input end of the fourth MOS tube is connected to the first power supply, the output end of the fourth MOS tube is connected to the cathode of the SPAD, the power supply end of the second inverting unit is connected to the first power supply, and the power supply end of the NOR gate, the power supply end of the delay unit and the power supply end of the third inverting unit are all connected to the second power supply.

7. The SPAD control circuit according to claim 6, characterized in that: The second inverting unit includes NMOS and PMOS, and the third inverting unit is a NOT gate; The gate of the NMOS is connected to the gate of the PMOS, and the common end of the connections is used as the input end of the second inverting unit; the drain of the NMOS is connected to the drain of the PMOS, and the common end of the connections is used as the output end of the second inverting unit; the source of the PMOS is connected to the first power supply, and the source of the NMOS is grounded; The input end of the NOT gate serves as the input end of the third inverting unit, and the output end of the NOT gate serves as the output end of the third inverting unit.

8. A SPAD array, characterized in that: A method comprising: comprising N SPAD control circuits according to any one of claims 1 to 7, and further comprising N SPADs, wherein N is a positive integer; The output ends of the first current sources in the N SPAD control circuits are respectively connected to the cathodes of the N SPADs in a one-to-one correspondence, and the anodes of the N SPADs are connected to a third power supply, wherein the third power supply is used to provide a negative voltage for reverse breakdown for the SPADs.

9. A laser distance measuring device, characterized in that: Comprising the SPAD array as claimed in claim 8.

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