A synchronous signal generating circuit and a synchronous signal generating module

Abstract

The present application discloses a synchronization signal generating circuit and a synchronization signal generating module, which belong to the field of electronic circuit counting and can be applied to autonomous driving scenarios. The signal generating circuit includes a DC source and a switch module, the positive pole of the DC source is connected to the first end of the switch module, the negative pole of the DC source and the third end of the switch module are both grounded, the control end of the switch module inputs the initial synchronization signal, and the second end of the switch module outputs the first target synchronization signal. Under the control of the initial synchronization signal, the switch module can output the DC voltage output by the DC source, or output a low level. Since the high level of the first target synchronization signal is the DC voltage output by the DC source, the DC voltage is certain, so there is no need to consider the level standard of the input initial synchronization signal, and the output first target synchronization signal and the highest level standard that can be supported by the signal receiving end can be matched, thereby improving the compatibility between devices.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a synchronization signal generating circuit and a synchronization signal generating module. Background Art

[0002] With the development of self-assisted driving and high-level autonomous driving technologies, various types of sensors, such as ultrasonic radar, millimeter-wave radar, lidar, visible light camera, and inertial navigation and other related devices have become core equipment for vehicles to obtain information such as location, environment, roads, and obstacles.

[0003] The information obtained from sensors generally needs to be sent to the domain controller for processing and decision-making. One of the prerequisites for accurate decision-making is that the operation or action of all sensors needs to be based on some kind of precise synchronization signal as a benchmark.

[0004] The industry generally uses a pulse-per-second signal (PPS) as a synchronization signal. This signal is a digital square wave signal. The signal receiving end will sample at the rising or falling edge of the synchronization signal. Since the level standard of the PPS emitted by the signal transmitting end may be different from the highest level standard supported by the signal receiving end, the compatibility between devices is reduced. Summary of the invention

[0005] The present application provides a synchronization signal generating circuit and module, which are used to solve the problem of poor compatibility between a device that sends a synchronization signal and a device that receives the synchronization signal.

[0006] In a first aspect, the present application provides a synchronization signal generating circuit, comprising: a DC source and a switch module;

[0007] The positive electrode of the DC source is connected to the first end of the switch module, and the negative electrode of the DC source is grounded; the second end of the switch module is used to output the first target synchronization signal, the control end of the switch module is used to input the initial synchronization signal, and the third end of the switch module is grounded;

[0008] The switch module is used to, under the control of the initial synchronization signal, connect the path between the DC source and the second end of the switch module to output the DC voltage output by the DC source, and disconnect the path between the DC source and the second end of the switch module to output a low level.

[0009] The synchronization signal generating circuit provided by the present application includes a DC source and a switch module, wherein the positive pole of the DC source is connected to the first end of the switch module, the negative pole of the DC source is grounded, the second end of the switch module is used to output a first target synchronization signal, the control end of the switch module is used to input an initial synchronization signal, and the third end of the switch module is grounded. The switch module can, under the control of the initial synchronization signal, conduct the path between the DC source and the second end of the switch module to output a DC voltage output by the DC source, or, under the control of the initial synchronization signal, disconnect the path between the DC source and the second end of the switch module to output a low level. The DC voltage and the low level output by the switch module constitute the first target synchronization signal. Since the high level of the first target synchronization signal is the DC voltage output by the DC source, the DC voltage is constant for the same DC source, so there is no need to consider the level standard of the input initial synchronization signal, and the output first target synchronization signal and the highest level standard that can be supported by the signal receiving end can be matched, thereby improving the compatibility between devices.

[0010] In a possible implementation, the switch module includes a first switch unit and a second switch unit;

[0011] The control end of the first switch unit is used to input the initial synchronization signal, the first end of the first switch unit is connected to the control end of the second switch unit, the second end of the first switch unit is grounded, the first end of the second switch unit is connected to the positive electrode of the DC source, and the second end of the second switch unit is used to output the first target synchronization signal;

[0012] The first switch unit is used to conduct the path between the first end of the first switch unit and the second end of the first switch unit when the initial synchronization signal is at a high level, and to disconnect the path between the first end of the first switch unit and the second end of the first switch unit when the initial synchronization signal is at a low level;

[0013] The second switch unit is used to turn on the path between the first end of the first switch unit and the second end of the second switch unit to output the DC voltage when the path between the first end of the first switch unit and the second end of the first switch unit is turned on, and to turn off the path between the first end of the second switch unit and the second end of the second switch unit to output the low level when the path between the first end of the first switch unit and the second end of the first switch unit is turned off.

[0014] By adopting the above solution, the on and off of the first switch unit and the second switch unit are controlled by the initial synchronization signal so that they output different voltage values ​​to meet the requirements of the target synchronization signal.

[0015] In a possible implementation, the first switch unit includes a first voltage-dividing resistor, a second voltage-dividing resistor and a first switch tube;

[0016] The first end of the first voltage-dividing resistor serves as the control end of the first switch unit, and the second end of the first voltage-dividing resistor is connected to the control end of the first switch tube and the first end of the second voltage-dividing resistor;

[0017] The second end of the second voltage-dividing resistor is grounded;

[0018] The first end of the first switch tube serves as the first end of the first switch unit, and the second end of the first switch tube is grounded.

[0019] With the above solution, the first voltage-dividing resistor and the second voltage-dividing resistor divide the initial synchronization signal to control the on-off of the first switch tube through the divided signal to meet the on-off requirement of the second switch unit.

[0020] In a possible implementation, the second switch unit includes a third voltage-dividing resistor, a fourth voltage-dividing resistor, a pull-down resistor, and a second switch tube;

[0021] The first end of the third voltage-dividing resistor serves as the control end of the second switch unit, and the second end of the third voltage-dividing resistor is connected to the first end of the fourth voltage-dividing resistor and the control end of the second switch tube;

[0022] The second end of the fourth voltage-dividing resistor is connected to the positive electrode of the DC source and the first end of the second switch tube;

[0023] The second end of the second switch tube is connected to the first end of the pull-down resistor to serve as the second end of the second switch unit;

[0024] The second end of the pull-down resistor is grounded.

[0025] By adopting the above scheme, the third voltage-dividing resistor and the fourth voltage-dividing resistor divide the voltage of the first end of the second switch unit to control the on and off of the second switch tube through the divided signal, and under the action of the pull-down resistor, meet the conditions for outputting the target synchronization signal.

[0026] In a possible implementation, the switch module further includes a diode;

[0027] The anode of the diode is connected to the positive electrode of the DC source, and the cathode of the diode is connected to the first end of the second switch unit.

[0028] With the above solution, the diode is used as an anti-reverse diode to ensure that the current of the input initial synchronization signal will not flow into the current source through the PN junction formed by the control end and the first end of the first switch tube.

[0029] In a possible implementation, the switch module further includes a capacitor;

[0030] The capacitor is connected in parallel with the third voltage-dividing resistor.

[0031] By adopting the above scheme, the capacitor is used as an acceleration capacitor to control the second switch tube to turn on or off. According to the principle that the voltage across the capacitor cannot change suddenly, when the potential at the first end (collector) of the first switch tube changes, the potential at the control end (base) of the second switch tube will rise or fall rapidly, so that the second switch tube has the ability to turn on or off faster.

[0032] In a possible implementation, the circuit further includes an anti-static diode;

[0033] The cathode of the anti-static diode is connected to the control end of the switch module, and the anode of the anti-static diode is grounded.

[0034] By adopting the above scheme, the anti-static diode can protect the subsequent circuit to prevent static electricity and large current impact from damaging the subsequent circuit.

[0035] In a possible implementation, an adjustment module is also included;

[0036] The control end of the adjustment module is connected to the second end of the switch module, and the input end of the adjustment module is connected to the positive electrode of the DC source;

[0037] The adjustment module is used to compare the first target synchronization signal with a threshold, and output the DC voltage or the low-level signal according to the comparison result to generate at least one second target synchronization signal.

[0038] By adopting the above scheme, the adjustment module can directly output a DC voltage, and use the directly output DC voltage as the high level of the target synchronization signal, thereby avoiding the voltage drop problem caused by the DC voltage output by the DC source after passing through the second switching tube, and improving the accuracy of the second target synchronization signal.

[0039] In a possible implementation, the adjustment module includes at least one tri-state buffer;

[0040] For each three-state buffer, the control end of the three-state buffer is connected to the second end of the switch module, the power supply end of the three-state buffer serves as the input end of the adjustment module, the enable end of the three-state buffer is grounded, and the output end of the three-state buffer is used to output the second target synchronization signal.

[0041] By adopting the above scheme, a three-state buffer is used to output a DC voltage, which can suppress the noise and glitches of the DC voltage, thereby improving the accuracy of the second target synchronization signal. In addition, multiple three-state buffers can output multiple second target synchronization signals, which can be applicable to devices that use multiple synchronization signals, thereby improving the flexibility of the synchronization signal generating circuit.

[0042] In a second aspect, the present application provides a synchronization signal generating module, comprising a synchronization signal generating circuit as described in any one of the first aspects.

[0043] For the technical effects that may be achieved by the synchronization signal generating module disclosed in the second aspect, please refer to the technical effects that may be achieved by the first aspect or various possible solutions in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the structure of a synchronization signal generating circuit provided in an embodiment of the present application;

[0046] Figure 3 A circuit diagram of another synchronization signal generating circuit provided in an embodiment of the present application;

[0047] Figure 4 A circuit diagram of another synchronization signal generating circuit provided in an embodiment of the present application;

[0048] Figure 5 A circuit diagram of another synchronization signal generating circuit provided in an embodiment of the present application;

[0049] Figure 6 A circuit diagram of another synchronization signal generating circuit provided in an embodiment of the present application;

[0050] Figure 7 A circuit diagram of another synchronization signal generating circuit provided in an embodiment of the present application;

[0051] Figure 8 A circuit diagram of another synchronization signal generating circuit provided in an embodiment of the present application;

[0052] Fig. 9 A waveform diagram of an initial synchronization signal provided in an embodiment of the present application;

[0053] Fig.10 A waveform diagram of a second target synchronization signal provided in an embodiment of the present application;

[0054] Fig.11A waveform diagram of the delay of the rising edge of a second target synchronization signal and the rising edge of an initial synchronization signal provided in an embodiment of the present application;

[0055] Fig.12 A waveform diagram of the delay of the falling edge of a second target synchronization signal and the falling edge of an initial synchronization signal provided in an embodiment of the present application;

[0056] Fig.13 A waveform diagram of another initial synchronization signal provided in an embodiment of the present application;

[0057] Fig.14 A waveform diagram of another second target synchronization signal provided in an embodiment of the present application;

[0058] Fig.15 A waveform diagram of the delay of the rising edge of another second target synchronization signal and the rising edge of the initial synchronization signal provided in an embodiment of the present application;

[0059] Fig.16 A waveform diagram of the delay of the falling edge of another second target synchronization signal and the falling edge of the initial synchronization signal provided in an embodiment of the present application;

[0060] Fig.17 A waveform diagram of another initial synchronization signal provided in an embodiment of the present application;

[0061] Fig.18 A waveform diagram of another second target synchronization signal provided in an embodiment of the present application;

[0062] Fig.19 A waveform diagram of the delay of the rising edge of another second target synchronization signal and the rising edge of the initial synchronization signal provided in an embodiment of the present application;

[0063] Fig. 20 A waveform diagram of the delay of the falling edge of another second target synchronization signal and the falling edge of the initial synchronization signal provided in an embodiment of the present application;

[0064] Fig.21 A waveform diagram of another initial synchronization signal provided in an embodiment of the present application;

[0065] Fig. 22 A waveform diagram of another second target synchronization signal provided in an embodiment of the present application;

[0066] Fig.23 A waveform diagram of the delay of the rising edge of another second target synchronization signal and the rising edge of the initial synchronization signal provided in an embodiment of the present application;

[0067] Fig.24 Another waveform diagram of the delay of the falling edge of the second target synchronization signal and the falling edge of the initial synchronization signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0069] In assisted driving and high-level autonomous driving technologies, PPS is generally used as a synchronization signal. The signal transmitter sends the synchronization signal to the signal receiver, and the signal receiver samples the rising or falling edge of the synchronization signal. The level standard of the synchronization signal transmitted by the signal transmitter may be 1.8V, 3.3V, 5V or 12V, and the highest level standard supported by the signal receiver may be 1.8V, 3.3V, 5V or 12V. If the level standard of the synchronization signal transmitted by the signal transmitter is different from the highest level standard supported by the signal receiver, the signal transmitter and the signal receiver cannot adapt, thereby reducing the compatibility between devices.

[0070] In view of the above problems, the present application provides a synchronization signal generating circuit to improve the compatibility between devices.

[0071] First reference Figure 1 , which is a schematic diagram of an application scenario of an embodiment of the present application. A signal transmitting end 11 is connected to a signal receiving end 12 in communication, wherein the signal transmitting end can generate a PPS and send the PPS to the receiving end, and the signal receiving end uses the PPS as a synchronization signal.

[0072] In the embodiment of the present application, the signal transmitting end 11 may be a GPS module, and the signal receiving end 12 may be a domain controller, a camera, a sensor and other equipment. The signal transmitting end 11 may also be a domain controller, and the signal receiving end 12 may be a camera, a sensor and other equipment.

[0073] The following describes the data transmission method provided by the exemplary embodiment of the present application in combination with the application scenario described above and with reference to the accompanying drawings. It should be noted that the above application scenario is only shown to facilitate understanding of the spirit and principles of the present application, and the implementation of the present application is not limited in this respect.

[0074] like Figure 2 As shown, a synchronization signal generating circuit provided in an embodiment of the present application is applied to a signal receiving end, and includes a direct current source DC and a switch module 10;

[0075] The positive electrode of the DC source DC is connected to the first end of the switch module 10, and the negative electrode of the DC source DC is grounded; the second end of the switch module 10 is used to output the first target synchronization signal, the control end of the switch module 10 is used to input the initial synchronization signal, and the third end of the switch module 10 is grounded;

[0076] The switch module 10 is used to, under the control of the initial synchronization signal, connect the path between the DC source DC and the second end of the switch module 10 to output the DC voltage output by the DC source DC, and disconnect the path between the DC source DC and the second end of the switch module 10 to output a low level.

[0077] In the embodiment of the present application, the positive electrode of the DC source DC is connected to the first end of the switch module 10, the negative electrode of the DC source DC is grounded, the second end of the switch module 10 is used to output the first target synchronization signal, the control end of the switch module 10 is used to input the initial synchronization signal, and the third end of the switch module 10 is grounded. Under the control of the initial synchronization signal, the switch module 10 can conduct the path between the DC source DC and the second end of the switch module 10 to output the DC voltage output by the DC source DC, or under the control of the initial synchronization signal, disconnect the path between the DC source DC and the second end of the switch module 10 to output a low level. The DC voltage and the low level output by the switch module 10 constitute the first target synchronization signal. Since the high level of the first target synchronization signal is the DC voltage output by the DC source DC, for the same DC source DC, the DC voltage is constant, so there is no need to consider the level standard of the input initial synchronization signal, and the output first target synchronization signal and the highest level standard that can be supported by the signal receiving end can be matched, thereby improving the compatibility between devices.

[0078] It should be noted that the initial synchronization signal in the embodiment of the present application may be a PPS, and the level standard in the embodiment of the present application is the high level of the initial synchronization signal.

[0079] The synchronization signal generating circuit provided in the embodiment of the present application is applied to the signal receiving end, and the DC voltage output by the current source DC in the synchronization signal generating circuit can be selected according to the highest level standard supported by the high signal receiving end. For example, if the highest level standard supported by the signal receiving end is 3.3V, then the DC voltage output by the DC source DC selected in the synchronization signal generating circuit in the signal receiving end is 3.3V.

[0080] In the specific implementation, Figure 3 As shown, the switch module 10 may include a first switch unit 101 and a second switch unit 102;

[0081] The control end of the first switch unit 101 is used to input an initial synchronization signal, the first end of the first switch unit 101 is connected to the control end of the second switch unit 102, and the second end of the first switch unit 101 is grounded; the first end of the second switch unit 102 is connected to the positive pole of the direct current source DC, and the second end of the second switch unit 102 is used to output a first target synchronization signal.

[0082] The first switch unit 101 is used to conduct the path between the first end of the first switch unit 101 and the second end of the first switch unit 101 when the initial synchronization signal is at a high level, and to disconnect the path between the first end of the first switch unit 101 and the second end of the first switch unit 101 when the initial synchronization signal is at a low level;

[0083] The second switch unit 102 is used to connect the path between the first end of the second switch unit 102 and the second end of the second switch unit 102 when the path between the first end of the first switch unit 101 and the second end of the first switch unit 101 is connected, that is, to connect the path between the DC source DC and the second end of the second switch unit 102 to output a DC voltage, and to disconnect the path between the first end of the second switch unit 102 and the second end of the second switch unit 102 when the path between the first end of the first switch unit 101 and the second end of the first switch unit 101 is disconnected, that is, to disconnect the path between the first end of the second switch unit 102 and the second end of the second switch unit 102 to output a low level.

[0084] Reference Figure 3 When the path between the first end of the first switch unit 101 and the second end of the first switch unit 101 is turned on, the second end of the first switch unit 101 outputs a low level to control the first end of the second switch unit 102 and the second end of the second switch unit 102 to be turned on, so that the second end of the second switch unit 102 outputs the DC voltage output by the DC power supply DC; when the first end of the first switch unit 101 and the second end of the first switch unit 101 are disconnected, the second end of the first switch unit 101 outputs a high level to control the first end of the second switch unit 102 and the second end of the second switch unit 102 to be disconnected, so that the second end of the second switch unit 102 outputs a low level.

[0085] The DC voltage and the low level outputted from the second end of the second switch unit 102 constitute a first target synchronization signal. Since the initial synchronization signal is PPS, the first target synchronization signal is a square wave signal.

[0086] Specifically, Figure 4As shown, the first switch unit 101 may include a first voltage-dividing resistor R1, a second voltage-dividing resistor R2 and a first switch tube Q1. The first end of the first voltage-dividing resistor R1 serves as the control end of the first switch unit 101 and is used to input an initial synchronization signal Signal In. The second end of the first voltage-dividing resistor R1 is connected to the control end of the first switch tube Q1 and the first end of the second voltage-dividing resistor R2. The second end of the second voltage-dividing resistor R2 is grounded. The first end of the first switch tube Q1 serves as the first end of the first switch unit 101, and the second end of the first switch tube Q1 is grounded.

[0087] like Figure 4 As shown, the second switch unit 102 may include a third voltage-dividing resistor R3, a fourth voltage-dividing resistor R4, a pull-down resistor R5 and a second switch tube Q2. Specifically, the first end of the third voltage-dividing resistor R3 serves as the control end of the second switch unit 102, the second end of the third voltage-dividing resistor R3 is connected to the first end of the fourth voltage-dividing resistor R4 and the control end of the second switch tube Q2, the second end of the fourth voltage-dividing resistor R4 is connected to the positive electrode of the DC source DC and the first end of the second switch tube Q2, the second end of the second switch tube Q2 is connected to the first end of the pull-down resistor R5 as the second end of the second switch unit 102, and the second end of the pull-down resistor R5 is grounded.

[0088] To facilitate understanding, the embodiments of the present application are described below with examples.

[0089] like Figure 4 As shown, when the input initial synchronization signal is at a high level, the initial synchronization signal passes through the voltage-dividing network formed by the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and is input to the control end of the first switch tube Q1. The first switch tube Q1 can be an NPN-type triode, and its conduction threshold is about 0.7V. The resistance values ​​of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 can be set in advance to reasonably divide the voltage so that the voltage obtained after the voltage division by the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 meets the conduction condition of the first switch tube Q1, so that the first switch tube Q1 is turned on.

[0090] After the first switch tube Q1 is turned on, the potential of its first end, that is, the potential of the first end of the first switch unit 101, is pulled down to close to 0V, that is, approximately the ground level. At this time, the voltage-dividing network formed by the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4 pulls down the potential of the control end of the second switch tube Q2. The second switch tube Q2 can be a PNP-type triode, and its turn-on threshold is about -0.7V. The resistance values ​​of the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4 can be set in advance to reasonably divide the voltage, so that the third voltage-dividing resistor R3 and the fourth voltage-dividing resistor R4 divide the voltage to make the second switch tube Q2 turned on. After the second switch tube Q2 is turned on, the DC voltage of the current source DC is output through the second switch tube Q2 as the high level of the first target synchronization signal Signal Out.

[0091] When the input initial synchronization signal is at a low level or there is no signal input, the second voltage-dividing resistor R2 acts as a pull-down resistor for the control end of the first switch tube Q1. Since the first switch tube Q1 is turned on at a high level, the first switch tube Q1 is disconnected at this time. At this time, the control end input to the second switch tube Q2 is at a high level, and the second switch tube Q2 is disconnected. At this time, the DC voltage of the current source DC cannot be transmitted backward through the second switch tube Q2, and the second switch tube Q2 outputs a low level, which serves as the low level of the first target synchronization signal Signal Out.

[0092] In the specific implementation, Figure 5 As shown, the switch module 10 may further include a diode D2, the anode of the diode D2 is connected to the positive electrode of the DC source DC, and the cathode of the diode D2 is connected to the first end of the second switch unit 102. The diode D2 is used as an anti-reverse diode to ensure that the current of the input initial synchronization signal will not be injected into the current source DC through the PN junction formed by the control end and the first end of the first switch tube Q1.

[0093] The switch module 10 may further include a capacitor C1 connected in parallel with the third voltage-dividing resistor R3 , wherein a first end of the capacitor C1 is connected to a first end of the first switch tube Q1 , and a second end of the capacitor C1 is connected to a control end of the second switch tube Q2 .

[0094] Capacitor C1 serves as an acceleration capacitor for controlling the second switch tube Q2 to turn on or off. According to the principle that the voltage across the capacitor cannot change suddenly, when the potential of the first end (collector) of the first switch tube Q1 changes, the potential of the control end (base) of the second switch tube Q2 will increase or decrease rapidly, so that the second switch tube Q2 has the ability to turn on or off faster.

[0095] The synchronization signal generating circuit provided in the embodiment of the present application may further include a protection module 103, such as Figure 6 As shown, the protection module 103 protects the subsequent circuit to prevent static electricity and high current shock from damaging the subsequent circuit.

[0096] Specifically, the protection module 103 may include an anti-static diode D1 , a cathode of the anti-static diode D1 is connected to the control end of the switch module 10 , and an anode of the anti-static diode D1 is grounded.

[0097] like Figure 7 and Figure 8 As shown, the synchronization signal generating circuit provided in the embodiment of the present application may further include an adjustment module 104, such as Figure 7 and Figure 8As shown, the control end of the adjustment module 104 is connected to the second end of the switch module 10, and the input end of the adjustment module 104 is connected to the positive electrode of the current source DC. The adjustment module 104 is used to compare the first target synchronization signal output by the switch module 10 with the threshold, and output the DC voltage or low level of the DC source DC according to the comparison result to generate at least one second target synchronization signal.

[0098] like Figure 6 As shown, to generate a second target synchronization signal, such as Figure 7 As shown, n second target synchronization signals are generated, where n is a positive integer greater than 1.

[0099] Specifically, when the first target synchronization signal output by the switch module 10 is a high level, the adjustment module 104 compares the high level with the threshold, and if the high level is greater than the threshold, the DC voltage of the DC source DC is output; when the first target synchronization signal output by the switch module 10 is a low level, the adjustment module 10 compares the low level with the threshold, and if the low level is less than the threshold, the adjustment module 10 outputs a low level.

[0100] Reference Figure 7 and Figure 8 , the adjustment module 10 may include at least one tri-state buffer, Figure 7 Includes a three-state buffer U1, Figure 7 The circuit includes n three-state buffers U1~Un.

[0101] For each three-state buffer, the control end of the three-state buffer is connected to the second end of the switch module 10 for inputting the first target synchronization signal, the power supply end of the three-state buffer serves as the input end of the adjustment module 104 and is connected to the positive pole of the DC source DC, the enable end of the three-state buffer is grounded, and the output end of the three-state buffer is used to output the second target synchronization signal.

[0102] The three-state buffer itself will set a threshold, and the input first target synchronization signal will be compared with the threshold. If the first target synchronization signal is greater than or equal to the threshold, the three-state buffer outputs the voltage at the power supply end of the three-state buffer, that is, the DC voltage output by the DC source DC; if the first target synchronization signal is less than the threshold, the three-state buffer outputs a low level.

[0103] When the second switch tube Q2 is turned on, the first target synchronization signal is at a high level. At this time, the control end of the three-state buffer inputs the high level, and the high level is greater than the threshold value. Therefore, the three-state buffer outputs the DC voltage of the DC source DC, that is, the high level of the second target synchronization signal; when the second switch tube Q2 is turned off, the first target synchronization signal is at a low level. At this time, the control end of the three-state buffer inputs a low level, and the low level is less than the threshold value. Therefore, the three-state buffer outputs a low level, that is, the low level of the second target synchronization signal.

[0104] The pull-down resistor R5 in the embodiment of the present application can enable the control end of the tri-state buffer to input a low level when the second switch tube Q2 is disconnected.

[0105] It should be noted that the tri-state buffer in the embodiment of the present application is enabled at a low level.

[0106] The tri-state buffer in the embodiment of the present application may be a single-channel tri-state buffer, such as Figure 7 and Figure 8 As shown, the output driving capability of a single-channel three-state buffer is limited. If there are many modules or units that need to receive signals, you can consider adding multiple single-channel three-state buffers, such as Figure 7 In addition, in order to meet the needs of multiple modules or units receiving signals, the tri-state buffer in the embodiment of the present application can also be a multi-channel tri-state buffer. The multi-channel tri-state buffer can refer to Figure 7 There are multiple single-channel three-state buffers in the example, which will not be given as examples here.

[0107] Since the tri-state buffer is under the control of the control end, the output signal is related to the power supply end of the tri-state buffer, so there is no need to consider whether the high level of the initial synchronization signal is 3.3V, 5V or 12V. As long as the input initial synchronization signal is high, the initial synchronization signal controls the first switch tube Q1 to be turned on, the second switch tube to be turned on, and the output first target synchronization signal is high. Under the control of the high level, the tri-state buffer outputs the DC voltage output by the DC power supply DC; when the input initial synchronization signal is low, the initial synchronization signal controls the first switch tube Q1 to be turned off, the second switch tube Q2 to be turned off, the output first target synchronization signal is low, and the tri-state buffer outputs a low level under the control of the low level. Since the high level of the second target synchronization signal output by the tri-state buffer is the DC voltage of the DC source DC, the DC voltage is certain, so the high level of the second target synchronization signal is certain, no matter how many V the high level of the initial synchronization signal output by the signal output end is, the high level of the output second target synchronization signal is the DC voltage output by the DC source DC, thereby improving the compatibility between devices.

[0108] In addition, according to the characteristics of the three-state buffer, the DC source DC and the initial synchronization signal can be isolated, thereby protecting the subsequent signal receiving circuit. At the same time, the filtering network composed of resistors and capacitors in the three-state buffer can suppress the high-frequency noise and glitches of the DC voltage output by the DC source DC.

[0109] In the embodiment of the present application, according to the characteristics of the diode, the DC voltage output by the DC power supply DC will generate a certain voltage drop on the diode D2 after passing through the diode D2, thereby causing the high level of the output first target synchronization signal to be lower than the DC voltage, while the high level of the second target synchronization signal output by the three-state buffer is the DC voltage output by the DC source DC. At the same time, the three-state buffer can suppress high-frequency noise and glitches of the DC voltage. Therefore, compared with the high level of the first target synchronization signal output by the second switch tube Q2, the high level of the second target synchronization signal will be more stable and more accurate.

[0110] The following describes the embodiments of the present application using four cases where the high level of PPS is 1.8V, 3.3V, 5V and 12V, combined with simulation waveform diagrams.

[0111] The embodiment of the present application evaluates the system performance through a simulation tool, sets relevant parameters at the input end, simulates a real second pulse input signal, the signal frequency is 1Hz, the pulse width is 1ms, the rising edge and the falling edge are 10ns, and the DC voltage output by the DC source is 3.3V. In the simulation process, the parameters of each component are not changed, and only the high level of the input initial synchronization signal is changed, taking 3.3V, 5V, 12V and 1.8V as examples, the high level of the second target synchronization signal obtained at the output end is observed, and the delay of the output second target synchronization signal relative to the input initial synchronization signal is observed:

[0112] like Fig. 9 As shown in FIG. 1 , the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is a waveform diagram of 1.8V, as shown in FIG. Fig.10 As shown in FIG. 1 , when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 1.8V, the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V. Fig.11 , which is a waveform diagram of the delay of the rising edge of the second target synchronization signal relative to the rising edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 1.8V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V; Fig.12 This is a waveform diagram of the delay of the falling edge of the second target synchronization signal relative to the falling edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 1.8V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V.

[0113] like Fig.13 As shown in FIG. 1 , the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is a waveform diagram of 3.3V. Fig.14As shown in FIG. 1 , when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 3.3V, the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V, as shown in FIG. Fig.15 , which is a waveform diagram of the delay of the rising edge of the second target synchronization signal relative to the rising edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 3.3V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V; Fig.16 This is a waveform diagram of the delay of the falling edge of the second target synchronization signal relative to the falling edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 3.3V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V.

[0114] like Fig.17 As shown in FIG. 1 , the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is a waveform diagram of 5V. Fig.18 As shown in FIG. 1 , when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 5V, the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V. Fig.19 is a waveform diagram of the delay of the rising edge of the second target synchronization signal relative to the rising edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 5V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V, Fig. 20 This is a waveform diagram of the delay of the falling edge of the second target synchronization signal relative to the falling edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 5V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V.

[0115] like Fig.21 As shown in FIG. 1 , the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is a waveform diagram of 12V. Fig. 22 As shown in FIG. 1 , when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 12V, the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V. Fig.23 is a waveform diagram of the delay of the rising edge of the second target synchronization signal relative to the rising edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 12V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V, Fig.24This is a waveform diagram of the delay of the falling edge of the second target synchronization signal relative to the falling edge of the initial synchronization signal when the high level of the initial synchronization signal input to the input end of the synchronization signal generating circuit is 12V and the high level of the second target synchronization signal output from the output end of the synchronization signal generating circuit is 3.3V.

[0116] from Figure 9 to Figure 24 It can be seen that no matter how many V the high level of the initial synchronization signal is, after the initial synchronization signal passes through the synchronization signal generating circuit provided in this application, the output second target synchronization signal is 3.3V, that is, the DC voltage output by the DC source. In addition, the delay between the rising edge of the second target synchronization signal and the rising edge of the initial synchronization signal, as well as the delay between the falling edge of the second target synchronization signal and the falling edge of the initial synchronization signal are both between 1us and 3us, which are within an acceptable range.

[0117] Based on the same inventive concept, an embodiment of the present application also provides a synchronization signal generating module, which includes any one of the above-mentioned synchronization signal generating circuits.

[0118] Those skilled in the art may make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A synchronization signal generating circuit, It is characterized in that include: DC source, switch module and adjustment module; The positive electrode of the DC source is connected to the first end of the switch module, and the negative electrode of the DC source is grounded; the second end of the switch module is used to output the first target synchronization signal, the control end of the switch module is used to input the initial synchronization signal, and the third end of the switch module is grounded; The switch module is used to, under the control of the initial synchronization signal, conduct the path between the DC source and the second end of the switch module to output the DC voltage output by the DC source, and disconnect the path between the DC source and the second end of the switch module to output a low level; The control end of the adjustment module is connected to the second end of the switch module, and the input end of the adjustment module is connected to the positive electrode of the DC source; The adjustment module is used to compare the first target synchronization signal with a threshold, and output the DC voltage or low-level signal according to the comparison result to generate at least one second target synchronization signal; Wherein, the adjustment module includes at least one tri-state buffer; For each three-state buffer, the control end of the three-state buffer is connected to the second end of the switch module, the power supply end of the three-state buffer serves as the input end of the adjustment module, the enable end of the three-state buffer is grounded, and the output end of the three-state buffer is used to output the second target synchronization signal.

2. The circuit as claimed in claim 1, It is characterized in that The switch module includes a first switch unit and a second switch unit; The control end of the first switch unit is used to input the initial synchronization signal, the first end of the first switch unit is connected to the control end of the second switch unit, the second end of the first switch unit is grounded, the first end of the second switch unit is connected to the positive electrode of the DC source, and the second end of the second switch unit is used to output the first target synchronization signal; The first switch unit is used to conduct the path between the first end of the first switch unit and the second end of the first switch unit when the initial synchronization signal is at a high level, and to disconnect the path between the first end of the first switch unit and the second end of the first switch unit when the initial synchronization signal is at a low level; The second switch unit is used to turn on the path between the first end of the first switch unit and the second end of the second switch unit to output the DC voltage when the path between the first end of the first switch unit and the second end of the first switch unit is turned on, and to turn off the path between the first end of the second switch unit and the second end of the second switch unit to output the low level when the path between the first end of the first switch unit and the second end of the first switch unit is turned off.

3. The circuit as claimed in claim 2, It is characterized in that The first switch unit includes a first voltage-dividing resistor, a second voltage-dividing resistor and a first switch tube; The first end of the first voltage-dividing resistor serves as the control end of the first switch unit, and the second end of the first voltage-dividing resistor is connected to the control end of the first switch tube and the first end of the second voltage-dividing resistor; The second end of the second voltage-dividing resistor is grounded; The first end of the first switch tube serves as the first end of the first switch unit, and the second end of the first switch tube is grounded.

4. The circuit as claimed in claim 2, It is characterized in that The second switch unit includes a third voltage-dividing resistor, a fourth voltage-dividing resistor, a pull-down resistor and a second switch tube; The first end of the third voltage-dividing resistor serves as the control end of the second switch unit, and the second end of the third voltage-dividing resistor is connected to the first end of the fourth voltage-dividing resistor and the control end of the second switch tube; The second end of the fourth voltage-dividing resistor is connected to the positive electrode of the DC source and the first end of the second switch tube; The second end of the second switch tube is connected to the first end of the pull-down resistor to serve as the second end of the second switch unit; The second end of the pull-down resistor is grounded.

5. The circuit as claimed in claim 2, It is characterized in that The switch module also includes a diode; The anode of the diode is connected to the positive electrode of the DC source, and the cathode of the diode is connected to the first end of the second switch unit.

6. The circuit as claimed in claim 4, It is characterized in that The switch module also includes a capacitor; The capacitor is connected in parallel with the third voltage-dividing resistor.

7. The circuit as claimed in claim 1, It is characterized in that Also included are anti-static diodes; The cathode of the anti-static diode is connected to the control end of the switch module, and the anode of the anti-static diode is grounded.

8. A synchronization signal generating module, It is characterized in that It comprises the synchronization signal generating circuit as claimed in any one of claims 1 to 7.

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