Page table prediction method, memory access operation method, electronic device, and electronic apparatus

Abstract

A page table prediction method, a storage access operation method, an electronic device and an electronic apparatus. The page table prediction method comprises: obtaining a target virtual page number of a target virtual page of a first granularity in which a target virtual address requiring page table prediction is located; in response to at least one second table item comprising a reference merging table item marked as available for prediction and a reference virtual page of a second granularity corresponding to the reference merging table item being located in an extended virtual page of a third granularity, predicting a predicted physical page address corresponding to the target virtual page number based on the target virtual address and a physical page address corresponding to a reference virtual page number of the reference virtual page, the reference merging table item being obtained by merging X sub-table items in sequence, and X physical pages corresponding to the order of the X sub-table items in sequence also corresponding in sequence. The method improves the accuracy of address prediction and improves the utilization rate of the TLB.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a page table prediction method, a storage access operation method, an electronic device, and an electronic device. Background Technology

[0002] In the field of computer technology, programmers can write programs using any virtual address (VA) within the system's defined range instead of physical addresses. The addresses used by the Central Processing Unit (CPU) when executing applications are virtual addresses. Typically, different processes running in a system are assigned different virtual address spaces, each covering a relatively large range. For example, when allocating memory to a process or when a process accesses memory, virtual addresses need to be mapped to physical addresses (PAs), which are the actual physical memory access addresses.

[0003] Virtual and physical addresses are managed through page tables. The CPU first determines the virtual page number (VPN) based on the virtual address passed from the program, reads the page table from physical memory, finds the corresponding physical page number (PPN) in the page table, and then accesses the actual physical memory address based on the physical page number. In other words, the CPU must access physical memory at least twice during this process. To reduce the number of times the CPU accesses physical memory, a Translation Lookaside Buffer (TLB), also known as a page table cache or address redirection cache, is introduced into the processor core. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a page table prediction method. This method is based on page table merging technology to predict the virtual address to physical address translation relationship, which improves the accuracy of address prediction and reduces the latency caused by page table traversal due to TLB capacity limitations.

[0005] This disclosure provides at least one embodiment of a page table prediction method for a translation backup buffer, wherein the translation backup buffer includes a plurality of first entries of first granularity and at least one second entry of second granularity, each of the at least one second entry being obtained by merging a plurality of sub-entries of first granularity. The method includes: obtaining the target virtual page number of the target virtual page of the first granularity where the target virtual address to be predicted is located; in response to the at least one second entry including a reference merge entry marked as available for prediction and the target virtual page and the reference virtual page of the second granularity corresponding to the reference merge entry being located in the same extended virtual page of a third granularity, predicting the predicted physical page address corresponding to the target virtual page number based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, wherein the reference merge entry is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutively ordered, the third granularity being Y times the second granularity, and X and Y being integers greater than 1.

[0006] For example, in the page table prediction method provided in at least one embodiment of this disclosure, the second granularity is 2 times the first granularity. n The third particle size is twice the size of the second particle size. m The multiple, where m and n are positive integers.

[0007] For example, the page table prediction method provided in at least one embodiment of this disclosure further includes determining whether the at least one second table entry includes the reference merged table entry marked as available for prediction.

[0008] For example, at least one embodiment of the page table prediction method provided in this disclosure further includes determining whether the target virtual page and the reference virtual page of the second granularity corresponding to the reference merged table entry are located within the same extended virtual page of the third granularity.

[0009] For example, in the page table prediction method provided in at least one embodiment of this disclosure, each of the plurality of sub-table entries represents a correspondence between a virtual page of a first granularity and a physical page of a first granularity, and each of the at least one second table entry represents a correspondence between a virtual page of a second granularity and a physical page of a second granularity. The method further includes: in response to the plurality of virtual pages of the first granularity being located within the same virtual page of the second granularity and the plurality of physical pages of the first granularity being located within the same physical page of the second granularity, merging the plurality of sub-table entries into a single second table entry.

[0010] For example, in the page table prediction method provided in at least one embodiment of this disclosure, the third granularity is 2. kBit, k is an integer greater than 1, based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, predict the predicted physical page address corresponding to the target virtual page number, including: obtaining the highest bit to the kth bit of the predicted physical page address from the highest bit to the kth bit of the physical page address corresponding to the reference virtual page number; setting the (k-1)th bit to the 0th bit of the physical page address corresponding to the target virtual page number as the (k-1)th bit to the 0th bit of the predicted physical page address.

[0011] This disclosure provides at least one embodiment of a storage access operation method, the method comprising: obtaining a target virtual address of object data used by a memory access instruction; querying a translation backing buffer using the target virtual address; in response to the query that the translation backing buffer is missing, performing page table prediction using the target virtual address to obtain a predicted physical page address; obtaining a predicted target physical address corresponding to the target virtual address using the predicted physical page address; and performing subsequent operations required by the memory access instruction using the predicted target physical address, wherein the translation backing buffer includes a plurality of first entries of first granularity and at least one second entry of second granularity, each of the at least one second entry being obtained by merging a plurality of sub-entries of first granularity, and performing page table prediction using the target virtual address. This includes: obtaining the target virtual page number of the target virtual page at the first granularity where the target virtual address is located; in response to the at least one second table entry including a reference merge table entry marked as usable for prediction and the target virtual page and the reference virtual page corresponding to the reference merge table entry at the second granularity being located in the same extended virtual page at the third granularity, predicting the predicted physical page address corresponding to the target virtual page number based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, wherein the reference merge table entry is obtained by merging X consecutive sub-table entries, and the X physical pages corresponding to the X consecutive sub-table entries are also consecutively arranged, the third granularity is Y times the second granularity, and X and Y are integers greater than 1.

[0012] For example, in the storage access operation method provided in at least one embodiment of this disclosure, the subsequent operations required for the memory access instruction using the predicted target physical address include querying at least one level private cache using the predicted target physical address; in response to a hit in the query of the at least one level private cache, obtaining the data corresponding to the predicted target physical address from the at least one level private cache; or in response to a failure in querying the at least one level private cache, pausing the subsequent operations.

[0013] For example, in the storage access operation method provided in at least one embodiment of this disclosure, the at least one level private cache includes an L1 cache, or a combination of the L1 cache and the L2 cache.

[0014] For example, at least one embodiment of the storage access operation method provided in this disclosure further includes, during the subsequent operation using the predicted target physical address, performing a page table browsing operation in parallel using the target virtual address and obtaining the actual target physical page address corresponding to the target virtual address; in response to the predicted physical page address and the actual target physical page address being the same, confirming that the page table prediction is successful; or in response to the predicted physical page address and the actual target physical page address being different, confirming that the page table prediction has failed and canceling the subsequent operation already performed using the predicted target physical address.

[0015] For example, in a storage access operation method provided in at least one embodiment of this disclosure, in response to the confirmation of page table prediction success, the memory access instruction is marked as the confirmation of page table prediction success.

[0016] For example, the storage access operation method provided in at least one embodiment of this disclosure, after obtaining the predicted target physical address corresponding to the target virtual address, further includes saving the target virtual address and the predicted target physical address for the memory access instruction, and marking the memory access instruction as using the predicted target physical address in the subsequent operation.

[0017] For example, in the storage access operation method provided in at least one embodiment of this disclosure, for the memory access instruction, at least one of the following parameters is set: a first parameter, used to identify whether the predicted target physical address is used; a second parameter, used to identify whether the physical address used in the subsequent operation is valid; and a third parameter, used to identify whether the page table prediction is confirmed to be successful.

[0018] At least one embodiment of this disclosure provides a storage management apparatus, which includes a management unit and a translation backup buffer, wherein the translation backup buffer is configured to manage a plurality of first entries of first granularity and at least one second entry of second granularity, each of the at least one second entry being obtained by merging a plurality of sub-entries of first granularity; the management unit is configured to obtain the target virtual page number of the target virtual page of the first granularity where the target virtual address to be page table predicted is located; and the management unit is further configured to, in response to the at least one second entry including a reference marked as available for prediction The target virtual page and the reference virtual page corresponding to the reference merged entry are located in the same extended virtual page of the third granularity. Based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, the predicted physical page address corresponding to the target virtual page number is predicted. The reference merged entry is obtained by merging X consecutive sub-entries of the packet. The X physical pages corresponding to the X consecutive sub-entries are also consecutive. The third granularity is Y times the second granularity, where X and Y are integers greater than 1.

[0019] At least one embodiment of this disclosure also provides an electronic device including a control unit; and a storage management device as described in any embodiment of this disclosure; wherein the control unit is configured to obtain the target virtual address of object data used by a memory access instruction, query the translation backing buffer using the target virtual address, and in response to the query that the translation backing buffer is missing, obtain the predicted physical page address obtained by the storage management device through page table prediction using the target virtual address, obtain the predicted target physical address corresponding to the target virtual address using the predicted physical page address, and perform subsequent operations required by the memory access instruction using the predicted target physical address.

[0020] For example, the electronic device provided in at least one embodiment of this disclosure further includes at least one level of private cache; wherein the control unit is further configured to query the at least one level of private cache using the predicted target physical address; in response to a successful query of the at least one level of private cache, to obtain data corresponding to the predicted target physical address from the at least one level of private cache; or, in response to a failed query of the at least one level of private cache, to suspend the subsequent operations.

[0021] For example, in an electronic device provided in at least one embodiment of this disclosure, the storage management device further includes a page table lookup unit. The storage management device is configured to allow the page table lookup unit to perform a page table browsing operation using the target virtual address and obtain the actual target physical page address corresponding to the target virtual address. The control unit is further configured to confirm that the page table prediction is successful in response to the predicted physical page address being the same as the actual target physical page address, or to confirm that the page table prediction fails in response to the predicted physical page address being different from the actual target physical page address, and to cancel the subsequent operation already performed using the predicted target physical address.

[0022] At least one embodiment of this disclosure also provides an electronic device, which includes the electronic device provided in any embodiment of this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1 A schematic flowchart illustrating a page table prediction method provided in at least one embodiment of this disclosure;

[0025] Figure 2A A schematic diagram illustrating the correspondence between VPN and PPN in a second table entry that can be used for page table prediction, provided by at least one embodiment of this disclosure;

[0026] Figure 2B A schematic diagram illustrating the correspondence between VPN and PPN in a second table entry that is not available for page table prediction, provided in at least one embodiment of this disclosure;

[0027] Figure 3 A schematic diagram of a first and second entry structure in a TLB provided for at least one embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram illustrating the situation of a TLB query with a second entry, provided for at least one embodiment of this disclosure.

[0029] Figure 5 A schematic flowchart illustrating a storage access operation method provided in at least one embodiment of this disclosure;

[0030] Figure 6 A schematic diagram of a memory access instruction provided for at least one embodiment of this disclosure;

[0031] Figure 7 for Figure 5 A schematic diagram of the confirmation process of the predicted target physical address obtained in step S240;

[0032] Figure 8 for Figure 5 An exemplary flowchart of step S250;

[0033] Figure 9 A schematic block diagram of a storage management device provided for at least one embodiment of this disclosure;

[0034] Figure 10 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure;

[0035] Figure 11 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure; and

[0036] Figure 12 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0040] In a computer system, the Memory Management Unit (MMU) sits between the execution unit (such as the CPU or its processor core) and the memory, providing the translation from virtual addresses to physical addresses. The System Memory Management Unit (SMMU) is widely used in various System-on-Chip (SoC) devices, sitting between I / O peripherals and, for example, a bus. As a memory management unit, it is also primarily used to perform the translation from virtual addresses to physical addresses for peripherals.

[0041] The Page Load Balancer (TLB) is a cache integrated within the MMU or SMMU for page tables, used to improve the translation speed from virtual to physical addresses. The TLB typically has a fixed number of slots to store tagged page table entries that map virtual addresses to physical addresses. The search keyword is the virtual address, and the search result is the physical address. For example, when the CPU receives a virtual address from an application, it first checks the TLB to see if the corresponding page table data exists. If the requested virtual address exists in the TLB (called a TLB hit), the corresponding physical address is quickly obtained from the TLB, providing a very fast match result. This obtained physical address can then be used directly to access physical memory. Conversely, if the requested virtual address is not in the TLB (called a TLB miss), the page tables in physical memory need to be traversed to perform the virtual-to-physical address translation, which takes longer.

[0042] If the TLB hit rate is high, the number of physical memory accesses caused by traversing the page table is greatly reduced, even negligible. However, with the increasing volume of data accessed by applications such as big data and cloud computing, the locality between data is decreasing, thus reducing the TLB hit rate compared to traditional applications. As a cache for virtual and physical addresses, the TLB typically doesn't store many entries, usually around 64. While using large page tables (e.g., 2MB / 1GB) can improve the TLB hit rate, large page tables waste physical memory and increase I / O accesses. Furthermore, various operating systems (OS) do not fully support large page tables.

[0043] In the event of a TLB miss, page table prediction is typically used to improve address translation efficiency. The inventors of this disclosure note two main methods for page table prediction. One method involves adding a cache outside the TLB to predict the translation relationship between virtual and physical addresses. This cache is then used to predict the physical address corresponding to the missing virtual address when the TLB is missing. However, this method requires additional cache space, significantly increasing chip area and power consumption, ultimately increasing chip cost. The other method utilizes the existing TLB structure, relaxing the hit condition when searching the TLB. Even if the virtual page number does not match, a TLB hit is considered successful if a page number closest to the virtual page number can be found in the TLB. While this method does not require additional cache, the prediction condition is too simplistic, greatly increasing the risk of prediction failure.

[0044] This disclosure provides at least one embodiment of a page table prediction method for a translation backup buffer, wherein the translation backup buffer includes a plurality of first entries of first granularity and at least one second entry of second granularity, each of the at least one second entry being obtained by merging a plurality of sub-entries of first granularity. The method includes: obtaining the target virtual page number of the target virtual page of the first granularity where the target virtual address to be page table predicted is located; in response to at least one second entry including a reference merge entry marked as available for prediction and the target virtual page and the reference virtual page of the second granularity corresponding to the reference merge entry being located in the same extended virtual page of a third granularity, predicting the predicted physical page address corresponding to the target virtual page number based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, wherein the reference merge entry is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutively connected, the third granularity being Y times the second granularity, and X and Y being integers greater than 1.

[0045] At least one embodiment of this disclosure also provides a storage access operation method for performing the above-described page table prediction method in the event of a TLB absence.

[0046] Several embodiments of this disclosure also provide a storage management apparatus, electronic device, or electronic device corresponding to performing the page table prediction method described above.

[0047] This disclosure provides a page table prediction method, a memory access operation method, an electronic device, and an electronic device, all based on at least one embodiment, which predict the virtual address to physical address translation relationship based on page table merging technology. This method improves the accuracy of address prediction, thereby reducing the latency caused by page table traversal due to TLB capacity limitations. For example, in at least one embodiment, it improves TLB utilization without requiring changes to the TLB structure or the addition of additional structures.

[0048] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0049] Figure 1 This is a schematic flowchart illustrating a page table prediction method provided in at least one embodiment of the present disclosure.

[0050] For example, such as Figure 1 The page table prediction method shown is used to perform the translation from the target virtual address to the predicted physical page address within the TLB. For example, the TLB includes multiple first entries at a first granularity and at least one second entry at a second granularity, each second entry being obtained by merging multiple sub-entries at the first granularity. Figure 1 As shown, the page table prediction method includes the following steps S110 to S150.

[0051] In step S110, the target virtual page number of the first-granularity target virtual page where the target virtual address to be predicted for page table is located is obtained.

[0052] In step S120, it is determined whether at least one second entry includes a reference merge entry that is marked as usable for prediction.

[0053] Step S130 is executed only if it is determined in step S120 that at least one second entry in the TLB includes a reference merge entry that is marked as available for prediction; otherwise, proceed to step S150 without performing page table prediction.

[0054] In step S130, it is determined whether the target virtual page and the reference virtual page corresponding to the reference merged table entry at the second granularity are located within the same extended virtual page at the third granularity.

[0055] Step S140 is executed only if it is determined in step S130 that the target virtual page and the reference virtual page corresponding to the reference merged table entry are located within the same extended virtual page of the third granularity; otherwise, proceed to step S150 without performing page table prediction.

[0056] Step S140: Based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, predict the predicted physical page address corresponding to the target virtual page number.

[0057] It should be noted that the page table prediction method described above is executed, for example, in the case of a TLB miss. When a TLB hit occurs, the actual target physical page address corresponding to the target virtual address is directly retrieved from the TLB, without executing the page table prediction method described above.

[0058] For example, each second entry is obtained by merging multiple sub-entries from the first granularity. The upper limit of the number of sub-entries included in each second entry is determined by the multiple of the second granularity relative to the first granularity. For example, if the second granularity is Z times the first granularity, then each second entry can include 2 to Z sub-entries, where Z is an integer greater than 1; the third granularity is Y times the second granularity, where Y is an integer greater than 1. For example, in some examples, the second granularity is 2 times the first granularity. n The third particle size is twice that of the second particle size. m The multiple, where m and n are positive integers.

[0059] For example, in some examples, when m=6, n=3, and the first granularity is 4K, the second granularity is 32K, and the third granularity is 2M. In this case, the target virtual page size where the target virtual address to be predicted is located is 4K, and the page size corresponding to each sub-entry of the first and second entries is also 4K; 2 to 8 first entries located in the same 32K virtual page are merged as sub-entries to obtain a second entry, and the page size corresponding to this second entry is 32K; the size of the extended virtual page is 2M, or it can be 128K, 512K, or 1M, and the embodiments of this disclosure do not limit this.

[0060] Figure 2A A schematic diagram illustrating the correspondence between VPN and PPN in a second table entry that can be used for page table prediction, provided by at least one embodiment of this disclosure; Figure 2B This is a schematic diagram illustrating the correspondence between VPN and PPN in a second table entry that is not available for page table prediction, provided by at least one embodiment of this disclosure.

[0061] For example, in Figure 1 In step S120, the reference merge entry marked as usable for prediction is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutive. For the reference merge entry, the corresponding virtual page and physical page are aligned with each other.

[0062] For example, such as Figure 2A and Figure 2B As shown, a second entry with a 32K granularity stored in the TLB is obtained by merging eight sub-entries with a 4K granularity. VPN 0 to VPN 7 are the eight virtual page numbers included in this second entry, and PPN 0 to PPN 7 are the eight physical page numbers involved in the eight virtual page numbers in this second entry.

[0063] For example, such as Figure 2AAs shown, the virtual page numbers VPN 0 to VPN 7 in the second entry are sequentially consecutive (i.e., they are sequentially consecutive within a 32K virtual page in the virtual memory space, for example, the virtual page numbers are consecutively consecutive from smallest to largest). The physical page numbers PPN 0 to PPN 7 corresponding to the sequentially consecutive virtual page numbers VPN 0 to VPN 7 are also sequentially consecutive (i.e., they are sequentially consecutive within a 32K physical page in the physical memory space, for example, the physical addresses corresponding to these physical page numbers are consecutively consecutive from smallest to largest). That is, VPN 0 corresponds to PPN 0, VPN 1 corresponds to PPN 1, ..., VPN 7 corresponds to PPN 7. At this point, the virtual pages corresponding to virtual page numbers VPN 0 to VPN 7 and the physical pages corresponding to physical page numbers PPN 0 to PPN 7 are aligned with each other. This second entry is marked as a reference merge entry that can be used for prediction.

[0064] For example, such as Figure 2B As shown, although the eight virtual page numbers VPN 0 to VPN 7 included in the second table are sequentially consecutive, the physical page numbers corresponding to these consecutive virtual page numbers VPN 0 to VPN 7 are not sequentially consecutive, as shown below. Figure 2B As shown, for example, VPN 0 corresponds to PPN 2, ..., VPN 2 corresponds to PPN 0, ..., VPN 7 corresponds to PPN 4. The order of the physical page numbers corresponding to the consecutive virtual page numbers VPN 0 to VPN 7 is PPN 2, ..., PPN 0, ..., PPN 6, ..., PPN 4. In this case, the virtual pages corresponding to the virtual page numbers VPN 0 to VPN 7 are not aligned with the physical pages corresponding to the physical page numbers PPN 0 to PPN 7, so this second entry cannot be used for prediction.

[0065] For example, during system initialization, the operating system tends to allocate consecutive physical pages to consecutive virtual pages, aligning virtual pages with their corresponding physical pages. Although this alignment decreases over a large granularity as system runtime or the number of running programs increases, it may still be preserved with a high probability within a certain granularity. Therefore, page table prediction can be performed using this alignment within such a granularity. Consequently, the TLB typically has multiple second entries where the corresponding physical page numbers of consecutive virtual page numbers are also consecutively ordered. This means the TLB can have multiple reference merge entries that can be marked for prediction, which can then be used in the page table prediction method provided in this embodiment.

[0066] Figure 3 This is a schematic diagram of a first and second entry structure within a TLB, provided for at least one embodiment of the present disclosure.

[0067] For example, such as Figure 3 As shown, the TLB is configured to allow the inclusion of first and / or second entries. For example, depending on the system's operating state, the TLB may include only the first entry, or both the first and second entries, or only the second entry. For instance, when the system first starts running, the TLB typically contains less content, such as only the first entry. As the system runs longer, the content in the TLB increases and may become full. In this case, multiple first entries that meet the merging criteria can be merged as sub-entries to obtain a second entry. After merging, the multiple first entries that were sub-entries are removed from the TLB and stored in a location dedicated to storing sub-entries. At certain points in time, due to the merging, the TLB may contain only the second entry. For example, each second-granularity second entry is obtained by merging multiple first-granularity sub-entries and then storing them in the TLB. Each sub-entry represents the correspondence between a first-granularity virtual page and a first-granularity physical page, and each second-granularity second entry represents the correspondence between a second-granularity virtual page and a second-granularity physical page. For example, if multiple first-granularity virtual pages are located within the same second-granularity virtual page, and the corresponding multiple first-granularity physical pages are located within the same second-granularity physical page, then multiple sub-table entries can be merged into one second table entry, and the merged second table entry can replace the multiple sub-table entries and be stored in the TLB.

[0068] For example, in a 64-bit system architecture, such as Figure 3 As shown, at a certain point in system operation, the TLB includes multiple first entries with a first granularity of 4K and at least one second entry with a second granularity of 32K, with page size information marked as auxiliary information in the corresponding first or second entry. At this time, the target virtual page size of the target virtual address for which page table prediction is needed is 4K, and the page size corresponding to the first entry and each sub-entry is also 4K. For example, the page size corresponding to the second entry obtained by merging 8 sub-entries is 32K.

[0069] It should be noted that at least one embodiment of this disclosure is also applicable to other types of system architectures besides 64-bit system architecture, and the page size corresponding to the first and second entries in the TLB may also include other page sizes supported by the adopted system architecture. For example, the first granularity may be 1KB, 32KB, 64KB, 1M or 2M, etc., and the second granularity may be 1KB, 4KB, 64KB, 1M or 2M, etc. The embodiments of this disclosure do not limit this.

[0070] For example, such as Figure 3As shown, the sub-entry represents the mapping between 4K granularity virtual pages and 4K granularity physical pages, and the second entry represents the mapping between 32K granularity virtual pages and 32K granularity physical pages. For example, if eight adjacent 4K granularity virtual pages are located within the same 32K granularity virtual page, and the corresponding eight 4K granularity physical pages are located within the same 32K granularity physical page, then these eight sub-entries can be merged into a single second entry. Furthermore, if multiple virtual pages and multiple physical pages corresponding to multiple sub-entries of a second entry are aligned with each other, then that second entry is labeled as a reference merge entry that can be used for prediction.

[0071] For example, such as Figure 3 The first and second entries shown record the corresponding page size information. Therefore, when performing a TLB query, for example, the number of bits in the VPN in the virtual address to be compared can be determined based on the page size corresponding to the currently queried TLB entry. For example, when the page size corresponding to the first entry is 4K, the VPN to be compared can be determined to be the most significant bit to the 12th bit (correspondingly, bits 0 to 11 are used as the offset within each 4K page); while when the page size corresponding to the second entry is 32K, the VPN to be compared can be determined to be the most significant bit to the 15th bit (correspondingly, bits 0 to 14 are used as the offset within a 32K page).

[0072] For example, in some examples, for a target virtual address to be queried, the VPN corresponding to the first entry at a 4K granularity (i.e., the most significant bit to the 12th bit of the target virtual address) is first compared with each entry in the TLB at the 4K granularity. If the VPN of the target virtual address matches a first entry in the TLB, a TLB hit is determined. If the most significant bit to the 12th bit of the target virtual address VPN fails to match a first entry in the TLB, the most significant bit to the 15th bit of the target virtual address is compared with a second entry at a 32K granularity. If the most significant bit to the 15th bit of the target virtual address matches a second entry in the TLB, the 14th to 12th bits of the target virtual address are used to further query the multiple sub-entries included in that second entry. If a match is found with any of these sub-entries, a TLB hit is determined; otherwise, a TLB miss is determined. By adopting... Figure 3 The TLB configuration shown can substantially expand the TLB capacity and reduce the number of comparisons during TLB queries, especially in the case of missing TLB entries, thus improving system efficiency.

[0073] For example, the third particle size is 2 k Bit, k is an integer greater than 1. In Figure 1In step S130, it is determined whether the target virtual page and the reference virtual page corresponding to the reference merged entry are located within the same extended virtual page of the third granularity. That is, it is determined whether the most significant bits to the kth bit of the virtual address corresponding to the target virtual page and the most significant bits to the kth bit of the virtual address corresponding to the reference virtual page match. If they do, then the target virtual page and the reference virtual page are located within the same extended virtual page of the third granularity. k Expanding the granularity of virtual pages.

[0074] For example, in some cases, k = 21, the target virtual page size is 4K, and the reference virtual page size is 32K. If the most significant bits to the 21st bit of the virtual address corresponding to the target virtual page match the most significant bits to the 21st bit of the virtual address corresponding to the reference virtual page, then the 4K target virtual page and the 32K reference virtual page reside within the same 2M extended virtual page.

[0075] For example, in Figure 1 In step S140, in order to obtain the predicted physical page address, the highest to the kth bits of the predicted physical page address are obtained from the highest to the kth bits of the physical page address corresponding to the reference virtual page number of the reference virtual page; the (k-1)th to the 0th bits of the physical page address corresponding to the target virtual page number are set as the (k-1)th to the 0th bits of the predicted physical page address.

[0076] For example, in some cases, k=21, the target virtual page size is 4K, and the reference virtual page size is 32K. The most significant bits to the 21st bit of the predicted physical page address are the most significant bits to the 21st bit of the physical page address corresponding to the reference virtual page number, and the 20th bits to the 0th bit of the predicted physical page address are the 20th bits to the 0th bit of the physical page address corresponding to the target virtual page number.

[0077] Figure 4 This is a schematic diagram illustrating the situation of a TLB query with a second entry, provided for at least one embodiment of this disclosure.

[0078] For example, such as Figure 4 As shown, in, for example Figure 1 In step S110, the target virtual page number of the first-granularity target virtual page where the target virtual address to be predicted for page table is located is obtained. For example... Figure 4 As shown, taking a 48-bit target virtual address as an example, for a page size of 4K granularity, bits 11 to 0 of the target virtual address are the offset part within the page; bits 47 to 12 of the target virtual address are the index part, which is the virtual page number VPN used for page table lookup.

[0079] It should be noted that page table prediction is performed in the event of a TLB missing table. Specifically, if comparing each entry from the 47th to the 12th bit of the VPN in the TLB against the 4K-granularity first entry (and the 4K-granularity sub-entries of the second entry, if present) all fails to match, then if, for example... Figure 1 In step S120, if it is determined that at least one second entry included in the TLB further includes a reference merge entry marked as usable for prediction, then... Figure 4 The image shows a comparison of the 47th to 15th bits of the VPN with a reference merged entry at a 32K granularity.

[0080] For example, such as Figure 4 As shown, the sub-entries in the second page table represent the mapping relationship between 4K granular virtual pages and 4K granular physical pages. The 32K granularity reference merged entry is obtained by merging 2 to 8 sub-entries (for example, the specific number of sub-entries depends on the actual situation). When querying whether a VPN matches a second page table entry, bits 47 to 15 of the VPN are compared with the 32K granularity second table entry. If they match, bits 14 to 12 of the VPN are compared with the multiple sub-entries included in the second table entry.

[0081] In the case of a missing TLB, compare bits 47 through 21 of the VPN with a reference merge entry at a 32K granularity. For example, as... Figure 4 As shown, in, for example Figure 1 In step S130, if bits 47 to 21 of the VPN match the highest bits to 21 of the VPN corresponding to the reference virtual page, meaning the 4K target virtual page and the 32K reference virtual page are located within the same 2M extended virtual page, then it can be assumed that the virtual page number and physical page number within this 2M extended virtual page are aligned. This allows for, for example... Figure 1 The prediction of the physical page address in step S140.

[0082] For example, such as Figure 4 As shown, in, for example Figure 1 In step S140, the highest to 21st bits of the predicted physical page address can be obtained from the highest to 21st bits of the physical page address corresponding to the reference virtual page number; the 20th to 12th bits of the predicted physical page address can be obtained from the 20th to 12th bits of the target virtual page number; since the page offset portion of the actual target physical page address is the same as the page offset portion of the target virtual address, the 11th to 0th bits of the predicted physical page address (page offset portion) can be obtained from the 11th to 0th bits of the target virtual address (page offset portion).

[0083] In at least one embodiment of the page table prediction method provided in this disclosure, the virtual address to physical address translation relationship is predicted based on page table merging technology. This page table prediction method improves the accuracy of address prediction. For example, in at least one example, the predicted physical page address can be obtained without changing the TLB structure or adding additional structures, thereby improving the utilization of the TLB.

[0084] Figure 5 This is a schematic flowchart illustrating a storage access operation method provided in at least one embodiment of the present disclosure.

[0085] For example, such as Figure 5 The storage access operation method shown is used to translate a target virtual address into a predicted target physical address in a computer system, and then use the predicted target physical address to access the physical address. This physical address can point to, for example, a storage address in a storage device, or to a functional circuit module within the computer system, such as a Direct Memory Access (DMA) unit, a PCIe device, or an I / O device. Figure 5 As shown, the storage access operation method includes the following steps S210 to S250.

[0086] Step S210: Obtain the target virtual address of the object data used by the memory access instruction;

[0087] Step S220: Use the target virtual address to query the translation backup buffer;

[0088] Step S230: In response to the missing target virtual address query translation backup buffer, perform page table prediction using the target virtual address to obtain the predicted physical page address;

[0089] Step S240: Use the predicted physical page address to obtain the predicted target physical address corresponding to the target virtual address;

[0090] Step S250: Perform the subsequent operations required for the memory access instruction using the predicted target physical address.

[0091] For example, in step S210, the target virtual address of the object data used by the memory access instruction can be, for example... Figure 1 The target virtual address in step S110. For example, the memory access instructions included in the executed computer program may be load instructions or store instructions, etc. The memory access instructions include one or more object data, which are virtual addresses used in the computer program. In the description of the embodiments of this disclosure, these are referred to as "target virtual addresses". In order to access these object data, it is necessary to use the physical addresses of these object data. Therefore, virtual address to physical address conversion is required.

[0092] For example, in step S220, the target virtual address is used to query the TLB to determine whether the query result is a TLB hit or a TLB miss. If the query result is a TLB miss, then the operation in step S230 is performed.

[0093] For example, in step S230, page table prediction is performed using the target virtual address, i.e., performing, for example... Figure 1 The page table prediction method in steps S110 to S150 obtains the predicted physical page address through page table prediction. The page table prediction process is similar to... Figure 1 The basic structure is the same, and the repeated parts will not be repeated.

[0094] For example, the predicted physical page address is the starting address of the predicted physical page (PPN) referred to by the predicted physical page number (VPN) obtained from the target virtual page number (VPN). Therefore, in step S240, the predicted physical page address and the page offset portion of the target virtual address are used to obtain the predicted target physical address corresponding to the target virtual address. In step S250, the subsequent operations required for the memory access instruction are performed using the predicted target physical address. During the execution of the memory access instruction using the predicted target physical address, since the success of the prediction has not yet been confirmed, although the memory access instruction can continue to be executed, it cannot be marked as finished or retired during the execution process to exit the pipeline. Instead, it is necessary to wait for confirmation of the prediction success and determine how to proceed based on the confirmation result (for example, as described below).

[0095] Figure 6 This is a schematic diagram of a memory access instruction provided for at least one embodiment of the present disclosure.

[0096] For example, such as Figure 6 As shown, for memory access instructions that use the target virtual address, at least one of the following parameters is set in the processor core's instruction processing pipeline:

[0097] (1) The first parameter (PaSpec) is used to indicate whether the predicted target physical address is used. For example, PaSpec=1 indicates that the predicted target physical address is used, and PaSpec=0 indicates that the predicted target physical address is not used.

[0098] (2) The second parameter (PaVal) is used to identify whether the physical address used in the subsequent operation is valid. For example, when PaVal=1, it means that the physical address used in the subsequent operation is valid (i.e., the actual target physical page address), and when PaVal=0, it means that the physical address used in the subsequent operation is invalid (i.e., not the actual target physical page address).

[0099] (3) The third parameter (PaConfirmVal) is used to indicate whether the page table prediction is successful. For example, when PaConfirmVal=1, it means that the predicted target physical address is correct (that is, the predicted target physical address is the same as the actual target physical page address, thus confirming that the previous page table prediction was successful). When PaConfirmVal=0, it means that the predicted target physical address is incorrect (that is, the predicted target physical address is different from the actual target physical page address, thus confirming that the previous page table prediction failed).

[0100] These parameters can be stored in registers for pipelined access by instructions within the processor core. For example, such as... Figure 6 As shown, by, for example Figure 5 After obtaining the predicted target physical address in steps S210 to S240, the predicted target physical address (PA) needs to be stored separately in the queue entry of the memory access instruction, and the predicted target physical address (PA) cannot overwrite the original target virtual address (VA). In addition, the first parameter PaSpec = 1, the second parameter PaVal = 0, and the third parameter PaConfirmVal = 0 of the memory access instruction are marked as using the predicted target physical address for operation.

[0101] For example, if in, for example Figure 5 In step S220, if the query result is a TLB hit, then it is not necessary to execute, for example... Figure 5 In step S230 or for example Figure 1 In the page table prediction method of steps S110 to S150, the first parameter PaSpec of the memory access instruction is marked as 0, the second parameter PaVal is marked as 1, and the third parameter PaConfirmVal is marked as 1, so as to mark the memory access instruction as operating using a valid actual target physical page address.

[0102] Figure 7 for Figure 5 A schematic diagram of the confirmation process of the predicted target physical address obtained in step S240.

[0103] For example, such as Figure 7 As shown, in executing, for example Figure 5 During the storage access operation, a page table walking operation is performed in parallel in physical memory to obtain the actual target physical page address. Then, the predicted target physical address is compared with the actual target physical page address to confirm whether the predicted target physical address obtained from the page table prediction is correct, and the confirmation result is marked, for example... Figure 6In the third parameter (PaConfirmVal) of the memory access instruction shown. For example, if the prediction is confirmed to be successful, the first parameter PaSpec of the corresponding memory access instruction is marked as 0, the second parameter PaVal as 1, and the third parameter PaConfirmVal as (1: correct, 0: incorrect).

[0104] like Figure 7 As shown, in at least one example, the process of confirming the predicted target physical address includes the following steps S261 to S263.

[0105] Step S261: During the subsequent operations using the predicted target physical address, the page table browsing operation is performed in parallel using the target virtual address to obtain the actual target physical page address corresponding to the target virtual address;

[0106] Step S262: In response to the predicted physical page address and the actual target physical page address being the same, confirm that the page table prediction was successful; or

[0107] Step S263: In response to the difference between the predicted physical page address and the actual target physical page address, confirm that the page table prediction has failed and undo subsequent operations that have been performed using the predicted target physical address.

[0108] For example, such as Figure 7 As shown, when in, for example Figure 5 When step 220 uses the target virtual address to query the TLB and the query result is that the TLB is missing, in executing, for example... Figure 5 While performing page table prediction in step 230, perform, for example... Figure 7 In step S261, a page table browsing operation is performed in physical memory to obtain the actual target physical page address.

[0109] For example, such as Figure 7As shown, after obtaining the actual target physical page address in step S261, the predicted target physical address is compared with the actual target physical page address to confirm whether the predicted target physical address obtained from the page table prediction is correct. For example, in step S262, if the predicted physical page address and the actual target physical page address are the same, the page table prediction is confirmed to be successful. At this time, the first parameter PaSpec of the memory access instruction is marked as 0, the second parameter PaVal as 1, and the third parameter PaConfirmVal as 1. That is, it is considered that the memory access instruction in the instruction processing pipeline is using the actual target physical page address, and subsequent operations continue until the execution of the memory access instruction ends normally. Conversely, in step S263, if the predicted physical page address and the actual target physical page address are different, the page table prediction is confirmed to be unsuccessful, and the first parameter PaSpec of the memory access instruction is marked as 0, the second parameter PaVal as 1, and the third parameter PaConfirmVal as 0. Since the prediction is confirmed to be unsuccessful, the data obtained using the predicted physical page address is invalid, and thus the prediction is cancelled. Figure 5 In step 250, the subsequent operations have already been performed using the predicted target physical address; then, in the instruction processing pipeline, the actual target physical page address will be used to execute the corresponding memory access instruction again, and the first parameter PaSpec of the memory access instruction will be marked as 0, the second parameter PaVal as 1, and the third parameter PaConfirmVal as 1. The process of executing the memory access instruction is the same as the normal operation, and will not be described in detail here.

[0110] In at least one embodiment of this disclosure, in the event of a missing TLB, the Memory Management Unit (MMU) initiates a page table traversal. Once the MMU completes the page table traversal and obtains the actual physical page address corresponding to the actual physical page number corresponding to the target virtual page number, it uses this result to fill the TLB and re-enables the corresponding memory access instruction to access the TLB again. Since this memory access instruction is marked as using a predicted target physical address (i.e., PaSpec = 1), the predicted physical page address and the target virtual address are sent to the TLB together. The TLB is queried using the target virtual address. If the TLB query is successful, the actual physical page address obtained from the TLB is compared with the predicted physical page address. The comparison result and the actual physical page address are sent to the memory access instruction queue, and the address of this instruction is marked as [PaVal = 1, PaSpec = 0, PaConfirmVal = (1: correct, 0: incorrect)]. If the query fails during this re-access of the TLB, the system reports an error, or the MMU restarts the page table traversal and repeats the above operations.

[0111] In the storage access operation method provided in at least one embodiment of this disclosure, after, for example Figure 7The verification process for the predicted target physical address shown can confirm whether the predicted target physical address obtained from the page table prediction is correct, thus effectively preventing erroneous operations caused by page table prediction failure. Furthermore, in scenarios where the TLB is missing, data access using the predicted target physical address and page table traversal to find the actual target physical page address can be performed simultaneously, effectively hiding the overhead caused by page table traversal.

[0112] Figure 8 for Figure 5 An exemplary flowchart of step S250. For example, as shown... Figure 8 As shown, in at least one example, the subsequent operations required for a memory access instruction using the predicted target physical address include the following steps S251 to S253.

[0113] Step S251: Use the predicted target physical address to query at least one level of private cache;

[0114] Step S252: In response to a query indicating a hit in at least one level private cache, retrieve the data corresponding to the predicted target physical address from the at least one level private cache; or

[0115] Step S253: In response to the failure to query at least one level of private cache, suspend subsequent operations.

[0116] For example, in a multi-core processor, the private cache in each processor core may include one or more levels of cache. For instance, in one example, the private cache may only include L1 cache, then the corresponding public (or shared) cache may include L2 cache, L3 cache, etc. Or, the private cache may include a combination of L1 cache and L2 cache, then the corresponding public (or shared) cache may include L3 cache, etc.

[0117] Furthermore, the L1 cache can be further divided into data L1 cache (L1D cache) and instruction L1 cache (L1I cache). In at least one embodiment of this disclosure, the virtual address is currently the virtual address of the target data. Therefore, if the L1 cache is accessed during operation, the L1D cache is actually accessed. For the sake of simplicity, the access operation of the L1D cache will not be described in detail in this disclosure.

[0118] In at least one embodiment of this disclosure, taking a private cache including a combination of L1 cache and L2 cache as an example, in step S251, after the corresponding memory access instruction obtains the predicted target physical address, the predicted target physical address is used to query the L1 cache. If the predicted target physical address query in the L1 cache hits, then as in step S252, the data corresponding to the predicted target physical address is obtained from the L1 cache for further processing. This further processing is the same as the normal operation and will not be described in detail here. If the predicted target physical address query in the L1 cache misses, then the missing request is sent to the L2 cache, and at the same time, it is marked that this missing request used the predicted target physical address. As a result, the corresponding memory access instruction sleeps in the memory access queue, and the sleep type is marked as "predicted address L1 missing". Furthermore, if the L2 cache hits, the data corresponding to the predicted target physical address is retrieved from the L2 cache for further processing, as in step S252. This further processing is the same as the normal operation and will not be described in detail here. However, if the L2 cache also misses, the L2 cache does not need to send a miss request to a shared cache such as the L3 cache. That is, as in step S253, subsequent operations are paused. At the same time, the L2 cache also needs to inform the L1 cache that the current access using the predicted target physical address has ended but no valid data has been obtained. If the predicted target physical address obtained from the page table prediction corresponding to the memory access instruction has not yet been confirmed, then the process continues to wait for the MMU unit to complete the page table traversal until the predicted target physical address is confirmed to be correct. Conversely, if the predicted target physical address obtained from the page table prediction corresponding to the memory access instruction has been confirmed to be correct, then the data can be accessed again using the actual physical page address. The process of accessing the new data is the same as the normal process and will not be described in detail here.

[0119] For example, if querying at least one level of private cache fails in step S253, then wait for, for example... Figure 7 After the page table browsing operation in physical memory in step S261 is completed, the data access is restarted using the actual target physical page address obtained from the page table browsing. This restarted data access process is the same as the normal process without page table prediction, and will not be described in detail here.

[0120] In the storage access operation method provided in at least one embodiment of this disclosure, for example... Figure 8 In the data access operation shown, the operation using the predicted target physical address is restricted to one or more levels of private cache. In this case, since the L2 cache will not send the missing request to the subsequent public cache (L3 cache), the I / O interface will not be accessed. This effectively solves the problem of the I / O interface being speculatively executed due to page table prediction, and can also effectively prevent the problem of invalid bandwidth occupation caused by incorrect predicted target physical address accessing physical memory.

[0121] Figure 9 This is a schematic block diagram of a storage management device provided for at least one embodiment of the present disclosure.

[0122] For example, such as Figure 9 As shown, at least one embodiment of this disclosure provides a storage management device 100 for performing address translation in a computer system, such as converting a virtual address to a physical address, thereby allowing access to a target address using the converted physical address. The target address may point to a storage address in a storage device, or to a functional circuit module within the computer system, such as a direct memory access (DMA) unit, a PCIe device, etc.

[0123] For example, such as Figure 9 As shown, the storage management device 100 includes a management unit 101 and a translation backup buffer (TLB) 102. The translation backup buffer 102 can be used for, for example... Figure 1 The page table prediction method is shown. For example, the translation backup buffer 102 is configured to manage multiple first entries of first granularity and at least one second entry of second granularity, each second entry being obtained by merging X sub-entries of the first granularity, where X is an integer greater than 1.

[0124] For example, management unit configuration 101 is used to execute, for example Figure 1 The page table prediction method shown is as follows: Obtain the target virtual page number of the target virtual page at the first granularity where the target virtual address to be predicted is located; in response to at least one second table entry including a reference merge table entry marked as available for prediction and the target virtual page and the reference virtual page corresponding to the reference merge table entry at the second granularity being located within the same extended virtual page at the third granularity, predict the predicted physical page address corresponding to the target virtual page number based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page.

[0125] For example, a reference merge entry marked as usable for prediction is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutive.

[0126] For example, each second entry is obtained by merging multiple sub-entries of the first granularity. For instance, if the second granularity is Z times the first granularity, then a single second entry includes 2 to Z sub-entries. The third granularity is Y times the second granularity, where Y is an integer greater than 1. In some examples, the second granularity is 2 times the first granularity. n The third particle size is twice that of the second particle size. m The multiples of m and n are positive integers. The embodiments disclosed herein are not limited in this respect.

[0127] For example, such as Figure 9 As shown, in some examples, the storage management device 100 also includes a PageWalker Unit (PWU) 103. For example, the storage management device 100 allows the PageWalker Unit 103 to perform a page table browsing operation in physical memory using a target virtual address and obtain the actual target physical page address corresponding to the target virtual address.

[0128] For example, the storage management device 100 may be a storage management unit (MMU) or a system storage management unit (SMMU), or other electronic components capable of address translation. The embodiments disclosed herein do not limit this.

[0129] The storage management apparatus provided in at least one embodiment of this disclosure predicts the virtual address to physical address translation relationship based on page table merging technology, improving the accuracy of address prediction and reducing the latency caused by page table traversal due to TLB capacity limitations. For example, in at least one example, there is no need to change the TLB structure or add additional structures, thus improving TLB utilization. Furthermore, in scenarios where the TLB is missing, data access using the predicted target physical address and page table traversal to find the actual target physical page address can be performed simultaneously, effectively hiding the overhead caused by page table traversal.

[0130] Figure 10 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure.

[0131] For example, such as Figure 10 As shown, the electronic device 200 is, for example, a processor core, including a memory management device 100 and a control unit 202. For example, the processor core can be a Complex Instruction Set Computer (CISC) or a Reduced Instruction Set Computer (RISC), and can be used in single-core or multi-core processors; the embodiments of this disclosure do not limit this. The memory management device 100 is the memory management device provided in any embodiment of this disclosure, for example... Figure 9 The storage management device 100 shown.

[0132] For example, refer to again Figure 10 At least one embodiment of this disclosure provides a computer system that includes a plurality of electronic devices 200 and an L3 cache 300 shared by the electronic devices 200, such as a multi-core processor.

[0133] For example, control unit 202 is configured to perform, for example Figure 5The storage access operation method shown is as follows: obtain the target virtual address of the object data used by the storage access instruction; use the target virtual address to query the translation backing buffer 102; in response to the target virtual address query translation backing buffer 102 being missing, obtain the predicted physical page address obtained by the storage management device through page table prediction using the target virtual address; use the predicted physical page address to obtain the predicted target physical address corresponding to the target virtual address; use the predicted target physical address to perform the subsequent operations required by the storage access instruction.

[0134] For example, such as Figure 10 As shown, in some examples, the electronic device 200 also includes one or more levels of private cache, for example, the private cache includes only L1 cache, or a combination of L1 cache and L2 cache. For example, as Figure 10 The example shown is a combination of L1 cache and L2 cache, i.e., electronic device 200 includes L1 / L2 cache 203.

[0135] For example, control unit 202 is also configured to perform such as Figure 8 The following operations are required for a memory access instruction using the predicted target physical address: query L1 / L2 cache 203 using the predicted target physical address; in response to a hit in L1 / L2 cache 203, retrieve the data corresponding to the predicted target physical address from L1 / L2 cache 203; or, in response to a failure to query L1 / L2 cache 203, suspend the subsequent operations.

[0136] For example, in the specific process of the control unit 202 querying the L1 / L2 cache 203, the L1 cache is first queried using the predicted target physical address. If the L1 cache hits the predicted target physical address query, the data corresponding to the predicted target physical address is retrieved from the L1 cache for further processing; if the L1 cache misses the predicted target physical address query, a miss request is sent to the L2 cache, and this miss request is marked as using the predicted target physical address. If the L2 cache hits, the data corresponding to the predicted target physical address is retrieved from the L2 cache for further processing; if the L2 cache also misses, then the L2 cache does not need to send a miss request to the L3 cache 300, i.e., subsequent operations are paused.

[0137] The electronic device provided in at least one embodiment of this disclosure, when performing data access operations, does not access the I / O interface because the L2 cache does not send missing requests to the L3 cache. This effectively solves the problem of the I / O interface being speculatively executed due to page table prediction, and can effectively prevent the problem of invalid bandwidth occupation caused by incorrectly predicted target physical addresses accessing physical memory.

[0138] Figure 11This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0139] For example, such as Figure 11 As shown, the electronic device 10 is the aforementioned computer system, including an electronic device 200. The electronic device 200 is any electronic device provided in any embodiment of this disclosure, such as... Figure 10 The electronic device 200 shown is any device with computing capabilities, such as a computer, server, smartphone, tablet computer, etc., and the embodiments disclosed herein are not limited thereto.

[0140] Figure 12 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0141] For example, such as Figure 12 As shown, the electronic device 400 is, for example, suitable for implementing the storage access operation method provided in the embodiments of this disclosure. The electronic device 400 may be a terminal device or a server, etc. It should be noted that... Figure 12 The illustrated electronic device 400 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0142] For example, such as Figure 12 As shown, the electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 41, which may include, for example, a storage management device according to any embodiment of this disclosure, and may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 42 or a program loaded from a storage device 48 into a random access memory (RAM) 43. The RAM 43 also stores various programs and data required for the operation of the electronic device 400. The processing device 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44. Typically, the following devices may be connected to the I / O interface 45: input devices 46 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 37 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 48 including, for example, magnetic tape, hard disk, etc.; and communication devices 49. The communication device 49 may allow the electronic device 400 to communicate wirelessly or wiredly with other electronic devices to exchange data.

[0143] Although Figure 10 An electronic device 400 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 400 may alternatively implement or have more or fewer devices.

[0144] For detailed specifications and technical effects of the 10 / 400 electronic device, please refer to the description of the processor above, which will not be repeated here.

[0145] The following points need to be clarified regarding this disclosure:

[0146] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0147] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0148] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A page table prediction method for a translation backup buffer, wherein, The translation backup buffer includes multiple first entries at a first granularity and at least one second entry at a second granularity, each of the at least one second entry being obtained by merging multiple sub-entries at the first granularity. The method includes: Obtain the target virtual page number of the first-granularity target virtual page where the target virtual address for which the page table prediction needs to be performed is located; In response to the at least one second entry including a reference merged entry marked as available for prediction, and the target virtual page and the reference virtual page corresponding to the reference merged entry being located within the same extended virtual page of the third granularity, the predicted physical page address corresponding to the target virtual page number is predicted based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page. The reference merged entry is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutive. The third granularity is Y times the second granularity, where X and Y are integers greater than 1. The third granularity is 2k bits, where k is an integer greater than 1. Based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, the predicted physical page address corresponding to the target virtual page number is predicted, including: The most significant bit to the kth bit of the predicted physical page address is obtained from the most significant bit to the kth bit of the physical page address corresponding to the reference virtual page number. Set bits k-1 to 0 of the physical page address corresponding to the target virtual page number to bits k-1 to 0 of the predicted physical page address.

2. The page table prediction method according to claim 1, wherein, The second granularity is 2n times the first granularity, and the third granularity is 2m times the second granularity, where m and n are positive integers.

3. The page table prediction method according to claim 1 further includes: Determine whether the at least one second entry includes the reference merged entry that is marked as usable for prediction.

4. The page table prediction method according to claim 1 further includes: Determine whether the target virtual page and the reference virtual page of the second granularity corresponding to the reference merged table entry are located within the same extended virtual page of the third granularity.

5. The page table prediction method according to claim 1, wherein, Each of the plurality of sub-entries represents a correspondence between a virtual page of first granularity and a physical page of first granularity, and each of the at least one second entry represents a correspondence between a virtual page of second granularity and a physical page of second granularity. The method further includes: In response to multiple virtual pages of the first granularity being located within the same virtual page of the second granularity and multiple physical pages of the first granularity being located within the same physical page of the second granularity, the multiple sub-table entries are merged into one second table entry.

6. A storage access operation method, comprising: Obtain the target virtual address of the object data used by the memory access instruction; Use the target virtual address to query the translation backup buffer; In response to a missing translation backup buffer in the target virtual address query, page table prediction is performed using the target virtual address to obtain the predicted physical page address; Using the predicted physical page address, the predicted target physical address corresponding to the target virtual address is obtained; The subsequent operations required to perform the memory access instruction using the predicted target physical address. The translation backup buffer includes multiple first entries at a first granularity and at least one second entry at a second granularity, each of the at least one second entry being obtained by merging multiple sub-entries at the first granularity. Performing page table prediction using the target virtual address includes: Obtain the target virtual page number of the first-granularity target virtual page where the target virtual address is located; In response to the at least one second entry including a reference merged entry marked as available for prediction, and the target virtual page and the reference virtual page corresponding to the reference merged entry being located within the same extended virtual page of the third granularity, the predicted physical page address corresponding to the target virtual page number is predicted based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page. The reference merged entry is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutive. The third granularity is Y times the second granularity, where X and Y are integers greater than 1. The third granularity is 2k bits, where k is an integer greater than 1. Based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, the predicted physical page address corresponding to the target virtual page number is predicted, including: The most significant bit to the kth bit of the predicted physical page address is obtained from the most significant bit to the kth bit of the physical page address corresponding to the reference virtual page number. Set bits k-1 to 0 of the physical page address corresponding to the target virtual page number to bits k-1 to 0 of the predicted physical page address.

7. The storage access operation method according to claim 6, wherein, The subsequent operations required to perform the memory access instruction using the predicted target physical address include: Use the predicted target physical address to query at least one level of private cache; In response to a query indicating a hit in the at least one level private cache, the data corresponding to the predicted target physical address is retrieved from the at least one level private cache; or In response to a failure to query the at least one level private cache, the subsequent operations are suspended.

8. The storage access operation method according to claim 7, wherein, The at least one level private cache includes an L1 cache, or a combination of the L1 cache and the L2 cache.

9. The storage access operation method according to claim 6, further comprising: During the subsequent operations using the predicted target physical address, the page table browsing operation is performed in parallel using the target virtual address to obtain the actual target physical page address corresponding to the target virtual address; If the predicted physical page address and the actual target physical page address are the same, the page table prediction is confirmed to be successful. or In response to the discrepancy between the predicted physical page address and the actual target physical page address, the page table prediction is confirmed to have failed, and the subsequent operations already performed using the predicted target physical address are undone.

10. The storage access operation method according to claim 9, wherein, In response to the confirmation of a successful page table prediction, the memory access instruction is marked as a confirmation of a successful page table prediction.

11. The storage access operation method according to claim 6, further comprising, after obtaining the predicted target physical address corresponding to the target virtual address: For the memory access instruction, the target virtual address and the predicted target physical address are saved, and in the subsequent operations, the memory access instruction is marked as using the predicted target physical address.

12. The storage access operation method according to claim 11, wherein, For the memory access instruction, at least one of the following parameters is set: The first parameter is used to identify whether the predicted target physical address is used; The second parameter is used to identify whether the physical address used in the subsequent operation is valid; The third parameter is used to indicate whether the page table prediction was successful.

13. A storage management device, comprising: Management unit and translation backup buffer, The translation backup buffer is configured to manage multiple first entries of first granularity and at least one second entry of second granularity, each of the at least one second entry being obtained by merging multiple sub-entries of first granularity; The management unit is configured to obtain the target virtual page number of the first-granularity target virtual page where the target virtual address requiring page table prediction resides; and... The management unit is further configured to, in response to the at least one second entry including a reference merged entry marked as available for prediction and the target virtual page and the reference virtual page corresponding to the reference merged entry being located within the same extended virtual page of the third granularity, predict the predicted physical page address corresponding to the target virtual page number based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page. The reference merged entry is obtained by merging X consecutive sub-entries, and the X physical pages corresponding to the X consecutive sub-entries are also consecutive. The third granularity is Y times the second granularity, where X and Y are integers greater than 1. The third granularity is 2k bits, where k is an integer greater than 1. Based on the target virtual address and the physical page address corresponding to the reference virtual page number of the reference virtual page, the predicted physical page address corresponding to the target virtual page number is predicted, including: The most significant bit to the kth bit of the predicted physical page address is obtained from the most significant bit to the kth bit of the physical page address corresponding to the reference virtual page number. Set bits k-1 to 0 of the physical page address corresponding to the target virtual page number to bits k-1 to 0 of the predicted physical page address.

14. An electronic device comprising: Control unit; as well as The storage management device as described in claim 13; The control unit is configured to obtain the target virtual address of the object data used by the memory access instruction, use the target virtual address to query the translation backing buffer, and in response to the target virtual address query indicating that the translation backing buffer is missing, obtain the predicted physical page address obtained by the memory management device through page table prediction using the target virtual address, use the predicted physical page address to obtain the predicted target physical address corresponding to the target virtual address, and use the predicted target physical address to perform the subsequent operations required by the memory access instruction.

15. The electronic device of claim 14, further comprising: At least one level of private cache; The control unit is further configured to query the at least one-level private cache using the predicted target physical address; in response to a successful query of the at least one-level private cache, retrieve the data corresponding to the predicted target physical address from the at least one-level private cache; or, in response to a failed query of the at least one-level private cache, suspend the subsequent operations.

16. The electronic device according to claim 14, wherein, The storage management device also includes a page table lookup unit. The storage management device is configured to allow the page table query unit to perform page table browsing operations using the target virtual address and obtain the actual target physical page address corresponding to the target virtual address. The control unit is further configured to, in response to the predicted physical page address being the same as the actual target physical page address, confirm that the page table prediction is successful, or, in response to the predicted physical page address being different from the actual target physical page address, confirm that the page table prediction is unsuccessful and cancel the subsequent operations already performed using the predicted target physical address.

17. An electronic device comprising: The electronic device as described in any one of claims 14-16.

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