Nor flash memory controller supporting AHB protocol

Abstract

The application discloses a NorFlash memory controller supporting AHB protocol, an FPGA module and a NorFlash memory. The FPGA module is composed of an AHB bus protocol conversion module AHB_MUX, an AHB slave device configuration module AHB_SLAVE, a NorFlash memory top layer control module AHB_FLASH_TOP, a NorFlash memory page write control module AHB_PAGE_WRITE, a NorFlash memory data read control module FLASH_READ and an SPI driving module SPI_MASTER. The NorFlash memory controller supporting AHB protocol has high reliability and is fully compatible with the information storage requirements of current mainstream embedded CPUs.

Description

Technical Field

[0001] This invention relates to the field of digital logic circuits, and more specifically to a NorFlash memory controller that supports the AHB protocol. Background Technology

[0002] Currently, with the rapid development of modern microelectronics technology, high-speed storage technology is becoming increasingly mature. Due to its advantages such as high flexibility, small size, high performance, low power consumption, and ease of maintenance, coupled with its excellent non-volatility, NorFlash memory has been widely used in industrial control, smart home appliances, wearable smart devices, and mobile terminals both domestically and internationally in recent years.

[0003] The AHB (Advanced High-performance Bus) specification is part of ARM's AMBA bus specification and has been adopted by most SoC designs. AHB is commonly used in high-performance, high-clock-frequency system architectures, with typical applications such as connecting the ARM core to the system's internal high-speed RAM, NorFlash, and DMA.

[0004] Traditional NorFlash memory controllers based on the AHB bus have complex logic, lack high-speed read and write capabilities, and have poor fault tolerance, resulting in low reliability in practical applications. Summary of the Invention

[0005] To overcome the shortcomings of the above technologies, this invention provides a highly reliable NorFlash storage controller that supports the AHB protocol.

[0006] The technical solution adopted by this invention to overcome its technical problems is:

[0007] A NorFlash memory controller supporting the AHB protocol includes:

[0008] The FPGA module and NorFlash memory are provided. The FPGA module consists of an AHB bus protocol conversion module AHB_MUX, an AHB slave device configuration module AHB_SLAVE, a NorFlash memory top-level control module AHB_FLASH_TOP, a NorFlash memory page write control module AHB_PAGE_WRITE, a NorFlash memory data read control module FLASH_READ, and an SPI driver module SPI_MASTER.

[0009] The CPU sends read / write commands to the AHB bus. The AHB bus protocol conversion module AHB_MUX parses the received CPU read / write commands to obtain the read / write address and the data to be written. The parsed result is sent to the NorFlash memory top-level control module AHB_FLASH_TOP. The HB slave device configuration module AHB_SLAVE sends slave device configuration information to the NorFlash memory top-level control module AHB_FLASH_TOP according to the AHB protocol requirements.

[0010] The NorFlash memory top-level control module AHB_FLASH_TOP sends read / write requests, read / write addresses, and page write data to the NorFlash memory page write control module AHB_PAGE_WRITE and the NorFlash memory data read control module FLASH_READ, respectively, according to CPU instructions.

[0011] After receiving the write command, write address, and write data, the NorFlash memory page write control module AHB_PAGE_WRITE sends the write command, write enable, write address, and write data stream to the SPI driver module SPI_MASTER in sequence. The SPI driver module SPI_MASTER generates the NorFlash drive clock according to the SPI protocol and sends the write command, write enable, write address, and write data stream received from the NorFlash memory page write control module AHB_PAGE_WRITE to the NorFlash data line in order from low to high bits according to the timing sequence, so that the NorFlash memory can store the information.

[0012] After receiving the read command, read address, and read data, the NorFlash memory data read control module FLASH_READ sequentially sends the read command, read enable, read address, and read data stream to the SPI driver module SPI_MASTER and waits to receive the NorFlash memory data stream read by the SPI driver module SPI_MASTER. The SPI driver module SPI_MASTER generates the NorFlash drive clock according to the SPI protocol and sends the read command, read enable, read address, and read data stream received from the NorFlash memory data read control module FLASH_READ to the NorFlash data line in order from low to high bit according to the timing sequence. The NorFlash memory processes the information and reads the data of the corresponding memory page.

[0013] Furthermore, the state machine of the NorFlash memory top-level control module AHB_FLASH_TOP contains four states: RD_IDLE, FLASH_READ, FLASH_WRITE, and FLASH_RW_END. The initial state is RD_IDLE. When a read / write request arrives from the AHB bus protocol conversion module AHB_MUX, the NorFlash memory top-level control module AHB_FLASH_TOP responds to the request and jumps to FLASH_READ or FLASH_WRITE. The NorFlash memory top-level control module AHB_FLASH_TOP sends the address and starts counting the read / write data. When the count reaches 256 bytes, the state jumps back to RD_IDLE and resends the read / write request, starting a new round of read / write state transitions until all data read / write tasks are completed. After completing the required amount of data read / write, the state machine jumps from FLASH_READ or FLASH_WRITE to FLASH_RW_END, completing one read / write task.

[0014] Furthermore, the state machine of the NorFlash memory page write control module AHB_PAGE_WRITE contains five states: WR_IDLE, SEND_WR_EN, SEND_WR_CMD, SEND_WR_ADDR, and WR_DATA. The initial state is WR_IDLE. When the page write start signal from the NorFlash memory top-level control module AHB_FLASH_TOP arrives, the state jumps to SEND_WR_EN. The NorFlash memory page write control module AHB_PAGE_WRITE sends a write enable signal to the SPI driver module SPI_MASTER. When the SPI driver module SPI_MASTER... After receiving the write enable signal, R transitions to SEND_WR_CMD. The NorFlash memory page write control module AHB_PAGE_WRITE sends the specified page write operation instruction, and the state transitions to SEND_WR_ADDR and WR_DATA in one go. The NorFlash memory page write control module AHB_PAGE_WRITE sends 3 bytes of page write address to the SPI driver module SPI_MASTER in sequence and sends page write data in bytes. When all the data is written to the NorFlash memory, the state transitions to WR_IDLE and waits for the NorFlash memory top-level control module AHB_FLASH_TOP to issue the next write task.

[0015] Furthermore, the state machine of the NorFlash memory data read control module FLASH_READ contains four states: RD_IDLE, SEND_RD_CMD, SEND_RD_ADDR, and RD_DATA. The initial state is RD_IDLE. When the read signal from the NorFlash memory top-level control module AHB_FLASH_TOP arrives, the state jumps to SEND_RD_CMD. The NorFlash memory data read control module FLASH_READ sends a read command to the SPI driver module SPI_MASTER, confirming the read command from the SPI driver module SPI_MAST. After receiving the read command signal, the ER state jumps to SEND_RD_ADDR. The NorFlash memory data read control module FLASH_READ continuously sends 3 bytes of read address to the SPI driver module SPI_MASTER. After confirming that the SPI driver module SPI_MASTER has received it, the state jumps to RD_DATA. The NorFlash memory data read control module FLASH_READ starts reading data. When all the data has been read, the state jumps to RD_IDLE, waiting for the NorFlash memory top-level control module AHB_FLASH_TOP to issue the next read task.

[0016] Preferably, the above-mentioned FPGA module is composed of an FPGA chip of model XCZU9EG-FFVB1156, and the NorFlash memory is an MT25QU128ABA memory.

[0017] The beneficial effects of this invention are: the NorFlash memory controller supporting the AHB protocol has high reliability and is fully compatible with the information storage needs of current mainstream embedded CPUs. At the same time, it has extremely high market application value for subsequent research on NorFlash controllers and the development of related IP cores. Attached Figure Description

[0018] Figure 1 This is an architecture diagram of the NorFlash storage controller module of the present invention;

[0019] Figure 2 This is a diagram showing the status transitions for controlling data read / write operations in the AHB_FLASH_TOP module of this invention.

[0020] Figure 3 This is a diagram showing the write data status transitions for the FLASH_PAGE_WRITE module of the present invention.

[0021] Figure 4 This is a jump diagram of the data reading status of the FLASH_READ module of the present invention. Detailed Implementation

[0022] The following is in conjunction with the appendix Figure 1 To be continued Figure 4 The present invention will be further described below.

[0023] As attached Figure 1 As shown, a NorFlash memory controller supporting the AHB protocol includes:

[0024] The system comprises an FPGA module and a NorFlash memory. The FPGA module consists of an AHB bus protocol conversion module (AHB_MUX), an AHB slave configuration module (AHB_SLAVE), a NorFlash memory top-level control module (AHB_FLASH_TOP), a NorFlash memory page write control module (AHB_PAGE_WRITE), a NorFlash memory data read control module (FLASH_READ), and an SPI driver module (SPI_MASTER). The SPI_MASTER module receives read / write commands and data from the FLASH_PAGE_WRITE and FLASH_READ modules and sends them to the NorFlash memory according to the SPI timing sequence. It also provides the necessary drive clock and chip select signals for the NorFlash. The NorFlash memory controller, supporting the AHB protocol, acts as an AHB Slave, connecting the AHB bus and the NorFlash, facilitating communication between the CPU and the NorFlash via the AHB bus. The FPGA module design of this memory controller includes the necessary module structure for normal communication between the CPU and the NorFlash, high-speed read / write of stored data, and specific information logic processing methods.

[0025] The CPU sends read / write commands to the AHB bus. The AHB bus protocol conversion module AHB_MUX parses the received CPU read / write commands to obtain the read / write address and the data to be written. The parsed result is then sent to the NorFlash memory top-level control module AHB_FLASH_TOP. The HB slave device configuration module AHB_SLAVE sends slave device configuration information to the NorFlash memory top-level control module AHB_FLASH_TOP according to the AHB protocol requirements.

[0026] The NorFlash memory top-level control module AHB_FLASH_TOP sends read / write requests, read / write addresses, and page write data to the NorFlash memory page write control module AHB_PAGE_WRITE and the NorFlash memory data read control module FLASH_READ, respectively, based on CPU instructions.

[0027] After receiving the write command, write address, and write data, the NorFlash memory page write control module AHB_PAGE_WRITE sends the write command, write enable, write address, and write data stream to the SPI driver module SPI_MASTER in sequence. The SPI driver module SPI_MASTER generates the NorFlash drive clock according to the SPI protocol and sends the write command, write enable, write address, and write data stream received from the NorFlash memory page write control module AHB_PAGE_WRITE to the NorFlash data line in low-to-high-order order according to the timing sequence, so that the NorFlash memory can store the information.

[0028] After receiving the read command, read address, and read data, the NorFlash memory data read control module FLASH_READ sequentially sends the read command, read enable, read address, and read data stream to the SPI driver module SPI_MASTER and waits to receive the NorFlash memory data stream read by the SPI driver module SPI_MASTER. The SPI driver module SPI_MASTER generates the NorFlash drive clock according to the SPI protocol and sends the read command, read enable, read address, and read data stream received from the NorFlash memory data read control module FLASH_READ to the NorFlash data line in order from low to high bit according to the timing sequence. The NorFlash memory processes the information and reads the data of the corresponding memory page.

[0029] To address the problems of complex logic, low read / write speeds, and poor fault tolerance in traditional AHB bus-based NorFlash memory controllers, this invention comprehensively analyzes the AHB bus protocol standard, innovates the NorFlash control logic, and develops a novel NorFlash memory controller supporting the AHB protocol. The proposed AHB protocol-supporting NorFlash memory controller offers high reliability and is fully compatible with the information storage requirements of current mainstream embedded CPUs. Furthermore, this invention has significant market application value for subsequent research on NorFlash controllers and the development of related IP cores.

[0030] Further details are attached. Figure 2As shown, the state machine of the NorFlash memory top-level control module AHB_FLASH_TOP contains four states: RD_IDLE, FLASH_READ, FLASH_WRITE, and FLASH_RW_END. The initial state is RD_IDLE. When a read / write request arrives from the AHB bus protocol conversion module AHB_MUX, the NorFlash memory top-level control module AHB_FLASH_TOP responds to the request, transitioning its state to FLASH_READ or FLASH_WRITE. AHB_FLASH_TOP sends the address and starts counting the read and write data. When the count reaches 256 bytes (currently, mainstream NorFlash memory can only store 256 bytes of data per page, and a new address needs to be sent to continue reading and writing after the read and write length is exceeded), the state jumps back to RD_IDLE state and resends the read and write request, and starts a new round of read and write state jumps until all data read and write tasks are completed (e.g., a total of 500 bytes need to be read). After completing the required amount of data read and write, the state machine jumps from FLASH_READ or FLASH_WRITE to FLASH_RW_END, completing one read and write task.

[0031] Further details are attached. Figure 3 As shown, the state machine of the NorFlash memory page write control module AHB_PAGE_WRITE contains five states: WR_IDLE, SEND_WR_EN, SEND_WR_CMD, SEND_WR_ADDR, and WR_DATA. The initial state is WR_IDLE. When the page write start signal from the NorFlash memory top-level control module AHB_FLASH_TOP arrives, the state transitions to SEND_WR_EN. The NorFlash memory page write control module AHB_PAGE_WRITE sends a write enable signal to the SPI driver module SPI_MASTER. When the SPI driver module SPI_MASTER... After receiving the write enable signal, the status jumps to SEND_WR_CMD. The NorFlash memory page write control module AHB_PAGE_WRITE sends the specified page write operation instruction, and the status jumps to SEND_WR_ADDR and WR_DATA in turn. The NorFlash memory page write control module AHB_PAGE_WRITE sends 3 bytes of page write address to the SPI driver module SPI_MASTER in sequence and sends page write data in bytes. When all the data is written to the NorFlash memory, the status jumps to WR_IDLE and waits for the NorFlash memory top-level control module AHB_FLASH_TOP to issue the next write task.

[0032] Further details are attached. Figure 4 As shown, the state machine of the NorFlash memory data read control module FLASH_READ contains four states: RD_IDLE, SEND_RD_CMD, SEND_RD_ADDR, and RD_DATA. The initial state is RD_IDLE. When the read signal from the NorFlash memory top-level control module AHB_FLASH_TOP arrives, the state jumps to SEND_RD_CMD. The NorFlash memory data read control module FLASH_READ sends a read command to the SPI driver module SPI_MASTER, confirming the read command from the SPI driver module SPI_MASTER. After receiving the read command signal, R transitions to SEND_RD_ADDR. The NorFlash memory data read control module FLASH_READ continuously sends 3 bytes of read address to the SPI driver module SPI_MASTER. After confirming that the SPI driver module SPI_MASTER has received the address, the status transitions to RD_DATA. The NorFlash memory data read control module FLASH_READ begins reading data. When all data has been read, the status transitions to RD_IDLE, waiting for the NorFlash memory top-level control module AHB_FLASH_TOP to issue the next read task.

[0033] Example 1:

[0034] Furthermore, the FPGA module is constructed using a Xilinx XCZU9EG-FFVB1156 FPGA chip, which is equipped with an embedded CPU core. The NorFlash memory can be a Micron MT25QU128ABA NorFlash memory. The FPGA module and the NorFlash memory communicate via the AHB bus.

[0035] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A NorFlash memory controller supporting AHB protocol, characterized in that, The application relates to a CPU, an AHB bus, an AHB bus protocol conversion module AHB_MUX, an AHB slave device configuration module AHB_SLAVE, a NorFlash memory top layer control module AHB_FLASH_TOP, a NorFlash memory page write control module AHB_PAGE_WRITE, a NorFlash memory data read control module FLASH_READ and an SPI drive module SPI_MASTER. The CPU sends read-write instructions to the AHB bus, the AHB bus protocol conversion module AHB_MUX analyzes the received CPU read-write instructions, obtains read-write addresses and data to be written, and sends the analysis result to the NorFlash memory top layer control module AHB_FLASH_TOP, and the AHB slave device configuration module AHB_SLAVE sends slave device configuration information to the NorFlash memory top layer control module AHB_FLASH_TOP according to the AHB protocol requirement; The NorFlash memory top layer control module AHB_FLASH_TOP sends read-write requests, read-write addresses and page write data to the NorFlash memory page write control module AHB_PAGE_WRITE and the NorFlash memory data read control module FLASH_READ according to CPU instructions; After the NorFlash memory page write control module AHB_PAGE_WRITE receives write instructions, write addresses and write data, the write instructions, write enables, write-in addresses and write-in data streams are sequentially sent to the SPI drive module SPI_MASTER, the SPI drive module SPI_MASTER generates a NorFlash drive clock according to the SPI protocol, and the write instructions, write enables, write-in addresses and write-in data streams received from the NorFlash memory page write control module AHB_PAGE_WRITE are sequentially sent to NorFlash data lines from low bits to high bits according to a time sequence, and information is stored by the NorFlash memory; After the NorFlash memory data read control module FLASH_READ receives read instructions, read addresses and read data, the read instructions, read enables, read addresses and read data streams are sequentially sent to the SPI drive module SPI_MASTER, and the NorFlash memory data stream read by the SPI drive module SPI_MASTER is received, the SPI drive module SPI_MASTER generates a NorFlash drive clock according to the SPI protocol, and the read instructions, read enables, read addresses and read data streams received from the NorFlash memory data read control module FLASH_READ are sequentially sent to NorFlash data lines from low bits to high bits according to a time sequence, information is processed by the NorFlash memory, and data of a corresponding storage page is read. ​ 2. The NorFlash memory controller supporting AHB protocol according to claim 1, characterized in that: The state machine of the NorFlash memory top-level control module AHB_FLASH_TOP includes four states, namely RD_IDLE, FLASH_READ, FLASH_WRITE, and FLASH_RW_END. The initial state is RD_IDLE. When the read / write request of the AHB bus protocol conversion module AHB_MUX arrives, the NorFlash memory top-level control module AHB_FLASH_TOP responds to the request, jumps to the state of FLASH_READ or FLASH_WRITE, sends an address, and starts counting the read / write data. When 256 bytes are counted, the state jumps back to the RD_IDLE state and re-sends the read / write request to start a new round of read / write state jump. Until all data read / write tasks are completed, the state machine jumps from FLASH_READ or FLASH_WRITE to FLASH_RW_END to complete a read / write task.

3. The NorFlash memory controller supporting AHB protocol according to claim 1, characterized in that: The state machine of the NorFlash memory page write control module AHB_PAGE_WRITE includes five states, namely WR_IDLE, SEND_WR_EN, SEND_WR_CMD, SEND_WR_ADDR, and WR_DATA. The initial state is WR_IDLE. When the page write start signal of the NorFlash memory top-level control module AHB_FLASH_TOP arrives, the state jumps to SEND_WR_EN. The NorFlash memory page write control module AHB_PAGE_WRITE sends a write enable signal to the SPI drive module SPI_MASTER. After the SPI drive module SPI_MASTER receives the write enable signal, the state jumps to SEND_WR_CMD. The NorFlash memory page write control module AHB_PAGE_WRITE sends a specified page write operation instruction, and then the state jumps to SEND_WR_ADDR and WR_DATA in turn. The NorFlash memory page write control module AHB_PAGE_WRITE sends a 3-byte page write address to the SPI drive module SPI_MASTER in turn and sends page write data in byte units. When all the data is written into the NorFlash memory, the state jumps to WR_IDLE and waits for the next write task issued by the NorFlash memory top-level control module AHB_FLASH_TOP.

4. The NorFlash memory controller supporting AHB protocol according to claim 1, characterized in that: The state machine of the NorFlash memory data reading control module FLASH_READ includes four states, namely RD_IDLE, SEND_RD_CMD, SEND_RD_ADDR and RD_DATA, and the initial state is RD_IDLE; when the read signal of the NorFlash memory top control module AHB_FLASH_TOP arrives, the state jumps to SEND_RD_CMD; the NorFlash memory data reading control module FLASH_READ sends a read instruction to the SPI driving module SPI_MASTER; after the SPI driving module SPI_MASTER receives the read instruction signal, the state jumps to SEND_RD_ADDR; the NorFlash memory data reading control module FLASH_READ continuously sends 3 Byte read addresses to the SPI driving module SPI_MASTER; after the SPI driving module SPI_MASTER receives the read addresses, the state jumps to RD_DATA; the NorFlash memory data reading control module FLASH_READ starts reading data; when the data reading is completed, the state jumps to RD_IDLE, and the next reading task is waited for by the NorFlash memory top control module AHB_FLASH_TOP.

5. The NorFlash memory controller supporting AHB protocol according to claim 1, characterized in that: The FPGA module is composed of an XCZU9EG-FFVB1156 type FPGA chip, and the NorFlash memory is an MT25QU128ABA type memory.

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