Generation method and device, verification method and device, electronic device, and storage medium

Abstract

A black box file generation method and device, a black box file verification method and device, an electronic device and a computer readable storage medium. The black box file is used for verifying an object path in an integrated circuit design. The black box file generation method comprises: obtaining hierarchical structure information of the integrated circuit design, the hierarchical structure information comprising structure information and module information of the integrated circuit design; determining a plurality of first circuit modules related to the object path in the integrated circuit design using the hierarchical structure information; and generating the black box file according to module information of a second circuit module in the integrated circuit design, the second circuit module being a module other than the plurality of first circuit modules in the integrated circuit design. The black box file generation method can simplify the cumbersome steps of generating a black box file and improve the generation efficiency of the black box file.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a black box file generation method and apparatus, a verification method and apparatus, an electronic device, and a storage medium. BACKGROUND

[0002] Verification is a simulation and test work on chip function design and chip process before the chip is produced. With the continuous increase of the scale of the chip, verification has become an important part of the chip research and design industry. SUMMARY

[0003] At least one embodiment of the present disclosure provides a black box file generation method, the black box file being used for verifying an object path in an integrated circuit design. The generation method comprises: obtaining hierarchical structure information of the integrated circuit design, the hierarchical structure information comprising structure information and module information of the integrated circuit design; determining a plurality of first circuit modules related to the object path in the integrated circuit design using the hierarchical structure information; and generating the black box file according to module information of a second circuit module in the integrated circuit design, the second circuit module being a module other than the plurality of first circuit modules in the integrated circuit design.

[0004] For example, in the generation method provided by an embodiment of the present disclosure, the plurality of first circuit modules comprises a source module, a destination module and at least one intermediate module of the object path, the source module being a circuit module where a starting point of the object path is located, and the destination module being a circuit module where a terminal point of the object path is located.

[0005] For example, in the generation method provided by an embodiment of the present disclosure, the number of object paths is greater than or equal to 2, and the plurality of first circuit modules related to the object path in the integrated circuit design is determined using the hierarchical structure information, comprising: determining the source module and the destination module of each object path; obtaining at least one intermediate module of each object path using the hierarchical structure information; and obtaining the plurality of first circuit modules by taking the union of the source module, the destination module and the at least one intermediate module of the object path.

[0006] For example, in the generation method provided by an embodiment of the present disclosure, the at least one intermediate module of each object path is obtained using the hierarchical structure information, comprising: obtaining an intermediate module description file of the integrated circuit design; and obtaining the at least one intermediate module of each object path according to the intermediate module description file in combination with the hierarchical structure information.

[0007] For example, in the generation method provided by an embodiment of the present disclosure, the intermediate module description file includes at least one to-be-added module and a sub-level of each to-be-added module; and the at least one intermediate module through by each object path is obtained according to the intermediate module description file and in combination with the hierarchical structure information, including: extracting a sub-module in the sub-level of each to-be-added module from the hierarchical structure information according to the sub-level of each to-be-added module, and the at least one intermediate module through by each object path includes the to-be-added module and the sub-module.

[0008] For example, in the generation method provided by an embodiment of the present disclosure, the source module and the destination module of each object path are determined, including: obtaining a path information file of the integrated circuit design; and extracting the source module and the destination module of the object path from the path information file.

[0009] For example, in the generation method provided by an embodiment of the present disclosure, the hierarchical structure information of the integrated circuit design is obtained, including: obtaining a chip logic design file of the integrated circuit design; and obtaining the hierarchical structure information of the integrated circuit design based on the chip logic design file.

[0010] An embodiment of the present disclosure provides a verification method for verifying an object path in an integrated circuit design, including: obtaining a black box file according to the generation method provided by any one of the embodiments of the present disclosure; obtaining a path information file of the object path; and verifying the object path based on the path information file and the black box file to generate a verification result.

[0011] An embodiment of the present disclosure provides a generation device of a black box file, the black box file being used for verifying an object path in an integrated circuit design, and the generation device includes: a structure information obtaining unit configured to obtain hierarchical structure information of the integrated circuit design, the hierarchical structure information including structure information and module information of the integrated circuit design; a circuit module determining unit configured to determine a plurality of first circuit modules related to the object path in the integrated circuit design by using the hierarchical structure information; and a black box generating unit configured to generate the black box file according to module information of second circuit modules in the plurality of circuit modules of the integrated circuit design except the plurality of first circuit modules.

[0012] For example, in the generation device provided by an embodiment of the present disclosure, the number of object paths is greater than or equal to 2, and the circuit module determining unit includes: a module determining sub-unit configured to determine a source module and a destination module of each object path; a module obtaining sub-unit configured to obtain at least one intermediate module through by each object path by using the hierarchical structure information; and a calculation sub-unit configured to obtain the plurality of first circuit modules by calculating a union set of the source module, the destination module and the at least one intermediate module of all object paths.

[0013] For example, in the generation apparatus provided in an embodiment of the present disclosure, the module obtaining subunit comprises: a description file obtaining subunit configured to obtain an intermediate module description file of the integrated circuit design; and an intermediate module obtaining subunit configured to obtain at least one intermediate module through by each object path according to the intermediate module description file and in combination with the hierarchical structure information.

[0014] For example, in the generation apparatus provided in an embodiment of the present disclosure, the intermediate module description file comprises at least one to-be-added module and a sub-hierarchy of each to-be-added module; and the intermediate module obtaining subunit comprises: an extracting subunit configured to extract a sub-module in the sub-hierarchy of each to-be-added module from the hierarchical structure information according to the sub-hierarchy of each to-be-added module, and the at least one intermediate module through by each object path comprises the to-be-added module and the sub-module.

[0015] For example, in the generation apparatus provided in an embodiment of the present disclosure, the module determining subunit comprises: a path information file obtaining subunit configured to obtain a path information file of the integrated circuit design; and a path module determining subunit configured to extract a source module and a destination module of the object path from the path information file.

[0016] For example, in the generation apparatus provided in an embodiment of the present disclosure, the structure information obtaining unit comprises: a design file obtaining subunit configured to obtain a chip logic design file of the integrated circuit design; and a hierarchical structure information obtaining subunit configured to obtain the hierarchical structure information of the integrated circuit design based on the chip logic design file.

[0017] At least one embodiment of the present disclosure provides a verification apparatus for verifying an object path in an integrated circuit design, comprising: a black box obtaining unit configured to obtain a black box file according to the generation method provided in any embodiment of the present disclosure; a path information obtaining unit configured to obtain a path information file of the object path; and a verification unit configured to verify the object path based on the path information file and the black box file to generate a verification result.

[0018] At least one embodiment of the present disclosure provides an electronic device, comprising a processor; a memory comprising one or more computer program instructions; and the one or more computer program instructions are stored in the memory and implemented by the processor to implement the generation method or the verification method provided in any embodiment of the present disclosure.

[0019] At least one embodiment of the present disclosure provides a computer readable storage medium, which is non-transitory and stores computer readable instructions, and the computer readable instructions are executed by a processor to implement the generation method or the verification method provided in any embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limiting of the present disclosure.

[0021] Figure 1A A flowchart of a method for generating a black box file is shown;

[0022] Figure 1A A schematic diagram of a file format of a hierarchical structure file is shown;

[0023] Figure 1A A schematic diagram of an object path is shown;

[0024] Figure 2A A flowchart of the method of step S20 in FIG. 1 is shown;

[0025] Figure 2A A schematic diagram of a file format of a path information file is shown;

[0026] Figure 2A A schematic diagram of a file format of an intermediate module description file is shown;

[0027] Figure 3 A flowchart of another method for generating a black box file is shown;

[0028] Figure 4 A flowchart of a verification method for verifying an object path in an integrated circuit design is shown;

[0029] Figure 5 A flowchart of another verification method for verifying an object path in an integrated circuit design is shown;

[0030] Figure 6 A schematic block diagram of a black box file generation apparatus is shown;

[0031] Figure 7 A schematic block diagram of a verification apparatus for verifying an object path in an integrated circuit design is shown;

[0032] Figure 8 A schematic block diagram of an electronic device is shown;

[0033] Figure 9 a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure is shown; and

[0034] Figure 10 a schematic diagram of a computer readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0035] For the purpose of making the objects, technical solutions and advantages of embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0036] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms “one”, “a” or “the” and similar terms do not denote quantity restriction, but mean that there is at least one. The terms “include”, “contain” and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, and do not exclude other components or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like only represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0037] In the verification of a System-on-a-Chip (SoC) design, the focus of the verification can include whether the data interaction between the top layer of the SoC design and each module is correct, and whether the connection of each module is correct. A traditional verification scheme often uses a verification case written by a user to verify the SoC, but for a large SoC design, the number of interconnection signals is very large, and a very large number of verification cases need to be constructed to cover each signal path, which brings great challenges to the verification work. Using a verification tool can simplify the verification of the SoC design and make the verification of the SoC design simpler. For example, the two ends of the interconnection signal are written in a table or a script as a check basis, and the verification tool can be used to check the SoC design. In the application of large-scale SoC design verification, the verification tool also has its limitations. As the size of the SoC design becomes larger and larger, the process of loading the SoC design and analyzing the path by the verification tool is not only very time-consuming, but also occupies a large amount of memory, and even causes the analysis to fail due to insufficient memory. Therefore, when using the verification tool to analyze the SoC design, the circuit modules that do not affect the analysis of the path in the SoC design can be output to a file, which is called a black box file. When analyzing the path, the verification tool can not consider the circuit modules in the black box file, so the burden of the verification tool analysis can be reduced, and the running time and the occupied memory can be saved.

[0038] Generally, when using the black box file for verification, the premise for the black box file to take effect is that the verification tool must load the black box file before reading the design, so the black box file is currently used as an optimization means for subsequent checking. Once the design changes or the to-be-tested path changes, the black box file may need to be generated again. If the black box file is obtained by using the verification tool to analyze the SoC design, due to the large size of the SoC design and the complexity of the path, the verification tool often fails due to insufficient memory when analyzing the black box. If the black box file is manually written, if some modules that affect the path are mistakenly set as black boxes due to the user's lack of understanding of the SoC design, the final checking result will be affected, and since the number of circuit modules of the SoC design is very large, manually writing the black box file is a very tedious thing.

[0039] In the current super-large SoC, the physical implementation of the layout needs to be divided into multiple circuit modules for implementation, and then the physical design of the entire SoC is completed through the top layer design. As the size of the chip continues to increase, the area increases, and the connection between the circuit modules increases accordingly, and the line delay inevitably causes timing problems. In order to solve this problem, a buffer (for example, a flipflop) is inserted on the connection between two circuit modules to converge the timing.

[0040] The black box file is used for verifying an object path in an integrated circuit design. The method for generating the black box file comprises: obtaining hierarchical structure information of the integrated circuit design, the hierarchical structure information comprising structure information and module information of the integrated circuit design; determining a plurality of first circuit modules related to the object path in the integrated circuit design by using the hierarchical structure information; and generating the black box file according to module information of a second circuit module in the integrated circuit design, the second circuit module being a module other than the plurality of first circuit modules in the integrated circuit design. The method for generating the black box file can simplify the cumbersome steps of generating the black box file, improve the efficiency of generating the black box file, and relieve the problem of memory overflow, thereby improving the efficiency of integrated circuit design verification.

[0041] Figure 1A A flowchart of a method for generating a black box file is shown.

[0042] As shown in Figure 1A , the method can comprise steps S10-S30.

[0043] Step S10: Obtain hierarchical structure information of the integrated circuit design, the hierarchical structure information comprising structure information and module information of the integrated circuit design.

[0044] Step S20: Determine a plurality of first circuit modules related to the object path in the integrated circuit design by using the hierarchical structure information.

[0045] Step S30: Generate the black box file according to module information of a second circuit module in the integrated circuit design. Here, the second circuit module is a module other than the plurality of first circuit modules in the integrated circuit design, for example, at least part of the modules or all of the modules other than the plurality of first circuit modules.

[0046] The black box file obtained in the embodiments of the present disclosure is used for verifying the object path in the integrated circuit design.

[0047] For step S10, for example, the structure information of the integrated circuit design can comprise the hierarchical structure of the integrated circuit design, circuit modules included in each level, etc.

[0048] For example, the hierarchical structure information of the integrated circuit can comprise the module information in addition to the structure information of the integrated circuit, for example, the name of each circuit module, the instance name of each level, etc.

[0049] For example, step S10 can comprise: obtaining a chip logic design file of the integrated circuit design, and obtaining the hierarchical structure information of the integrated circuit design according to the chip logic design file.

[0050] The chip logic design file can be, for example, a register transfer level (or register transfer level, RTL) file. For example, the hierarchy information of the integrated circuit design is obtained by analyzing the RTL file by using a verification tool, which includes a connection checking tool for checking the connection of a path.

[0051] For example, the connection checking tool reads the RTL file, and after the connection checking tool finishes reading the RTL file, a command (for example, a start gui command) that enables the connection checking tool to identify a graphical interactive interface is executed, and the graphical interactive interface of the connection checking tool is entered, and at this time, the hierarchy information of the integrated circuit design is displayed in the graphical interactive interface.

[0052] In some embodiments of the present disclosure, for example, in the graphical interactive interface, an interactive operation is performed, and the connection checking tool outputs the hierarchy information of the entire integrated circuit design into a hierarchy file in response to the interactive operation. For example, the hierarchy file is named hierarchy.log.

[0053] This embodiment can automatically generate a hierarchy file according to the operation of the user, and is simple to operate, easy to implement, and saves the time for generating a black box file.

[0054] Figure 1A A schematic diagram of a file format of a hierarchy file provided by at least one embodiment of the present disclosure is shown.

[0055] As shown in Figure 1A The hierarchy file, for example, the hierarchy.log file, indicates that the top module CHIP instantiation obtains the module A (i.e., module A), the module B (i.e., module B), and the module C (i.e., module C); the module A includes a sub-level, and the sub-level includes two sub-modules, module_A1 and module_A2; the module B includes a first sub-level, and the first sub-level includes the sub-module module_B1 and the sub-module module_B2; the sub-module module_B1 of the first sub-level further includes a second sub-level, and the second sub-level includes the sub-module module_B11 and module_B12; the sub-module module_B2 of the first sub-level further includes a second sub-level, and the second sub-level includes the sub-module module_B21.

[0056] For step S20, the plurality of first circuit modules include a source module, a destination module and at least one intermediate module of the object path, wherein the source module is a circuit module where the object path starts, the destination module is a circuit module where the object path ends, and the intermediate module is a module that the object path passes through and is between the start and the end.

[0057] Figure 1A A schematic diagram of an object path is shown.

[0058] As Figure 1A shown, the start of the object path is port a and the end of the object path is port b. Port a belongs to circuit module A and port b belongs to circuit module B, so the source module of the object path is circuit module A and the destination module of the object path is circuit module B.

[0059] As Figure 1A shown, the object path passes through module C, submodule D in module C and submodule E before reaching the end point b, so module C, submodule D and submodule E are the plurality of intermediate modules of the object path.

[0060] The object path does not pass through submodule F in module C, so the at least one intermediate module of the object path does not include submodule F.

[0061] In some embodiments of the present disclosure, for step S20, the plurality of first circuit modules related to the object path in the integrated circuit design are determined, for example, from the hierarchy.log file.

[0062] In some embodiments of the present disclosure, the object path can be one or more. In the case of multiple object paths, i.e., the number of object paths is greater than or equal to 2, step S20 can include the steps described below. Figure 2A

[0063] Figure 2A An exemplary method flowchart of step S20 in FIG. 1 is shown.

[0064] As Figure 2A shown, in at least one example, this step S20 can include steps S21-S23.

[0065] Step S21: Determine the source module and the destination module of each object path.

[0066] Step S22: Use the hierarchy information to obtain at least one intermediate module of each object path.

[0067] ​Step S23: obtaining a plurality of first circuit modules including a union of the source module, the destination module and the at least one intermediate module of the object path.

[0068] The method can obtain a plurality of first circuit modules related to all object paths, thereby generating a second circuit module irrelevant to all object paths as a black box file, and thus verifying all object paths and improving verification efficiency.

[0069] For step S21, for example, a path information file of the integrated circuit design is obtained, and the source module and the destination module of the object path are extracted from the path information file.

[0070] For example, the path information file is an add.tcl file, and the script file describes some basic information of the object path, for example, can include the start point, the end point, the source module, the destination module, the gating information, the clock information and the path delay information of the object path.

[0071] In some embodiments of the present disclosure, the path information file can have a fixed format, and the user can manually or through a tool (for example, a program) fill the information of the path into the script file according to the fixed format.

[0072] In another embodiment of the present disclosure, the path information file can be automatically generated. For example, the object path includes at least one buffer, buffer information of the at least one buffer in the object path is extracted from a buffer description file of the integrated circuit design, path description information of the object path is extracted from a chip logic design file of the integrated circuit design according to the buffer information, and the path information file of the object path is generated according to the path description information. The automatically generated path information file further improves the generation efficiency of the black box file, does not need to manually write the path information file, and greatly saves the time of developing the path information file.

[0073] For example, the buffer description file can include, for example, the number of buffers to be inserted on the signal connection between two circuit modules, the signal information at both ends of the connection and the clock information used by the buffer. The path description information of the object path can include, for example, the start point and the end point of the object path, the circuit module where the start point is located and the circuit module where the end point is located.

[0074] Figure 2A A schematic diagram of a file format of a path information file provided by at least one embodiment of the present disclosure is shown.

[0075] As Figure 2AAs shown, for example, the name of the path information file can be add.tcl, in which the object path from start point a to end point b (hereinafter referred to as "a-b path"), the object path from start point c to end point d (hereinafter referred to as "c-d path"), and the object path from start point e to end point f (hereinafter referred to as "e-f path") are included.

[0076] As shown in Figure 2A , the source module of each of the a-b path and the c-d path is circuit module A, and the destination module is circuit module B; the source module of the e-f path is circuit module D, and the destination module is circuit module F.

[0077] As shown in Figure 2A , the path delay information of the object path can also be included in the path information file. For example, path_delay represents the path delay information of the object path. For example, the a-b path and the c-d path are delayed by 1 clock cycle.

[0078] For step S21, the source module and the destination module of each object path can also be determined in other ways. For example, the source module and the destination module input by the user are received.

[0079] For step S22, for example, an intermediate module description file of the integrated circuit design can be obtained; and at least one intermediate module through by each object path is obtained according to the intermediate module description file in combination with the hierarchical structure information.

[0080] In some embodiments of the present disclosure, the intermediate module description file includes at least one to-be-added module and a sub-level of each to-be-added module.

[0081] Figure 2A A schematic diagram of a file format of an intermediate module description file provided by at least one embodiment of the present disclosure is shown.

[0082] As shown in Figure 2A , for example, the intermediate module description file is add.csv. The intermediate module description file can include two columns. The first column is "Hierarchy", which represents the hierarchical structure of the to-be-added module. The second column is "Level", which represents the sub-level of the to-be-added module through by the object path.

[0083] For example, the element in the "Hierarchy" column and in the first row is CHIP.M, CHIP.M indicates that the module to be added includes circuit module CHIP and circuit module M. Circuit module CHIP may be, for example, a top-level module, and circuit module M is a submodule of the top-level module. The value of "Level" corresponding to CHIP.M is 1, indicating that the object path passes through the first-level submodule of circuit module M, for example, the first-level submodule includes submodule M1 and submodule M2.

[0084] Similarly, the element in the "Hierarchy" column and in the second row is CHIP.N, CHIP.N indicates that the module to be added includes circuit module CHIP and circuit module N. The value of "Level" corresponding to CHIP.N is 2, indicating that the object path passes through the submodule at the first-level submodule and the submodule at the second-level submodule in circuit module N. For example, the object path passes through submodule N1 and submodule N2 included in the first-level submodule of circuit module N, module N11 in the second-level submodule included in submodule N1, and the like.

[0085] For another example, the element in the "Hierarchy" column and in the third row is CHIP.L, CHIP.L indicates that the module to be added includes circuit module CHIP and circuit module L. The value of "Level" corresponding to CHIP.N is all, indicating that the object path passes through all the submodules of circuit module L.

[0086] In some embodiments of the present disclosure, for example Figure 1A The intermediate module description file add.csv shown in the table can be obtained by user writing.

[0087] In some embodiments of the present disclosure, for example Figure 2A The "Hierarchy" column in the intermediate module description file add.csv shown in the table can be automatically generated by a verification tool or other tools, and the "Level" column can be obtained by user filling.

[0088] For example, in the case of Figure 3The object path shown not only passes through the circuit module C, but also passes through the sub-module D instantiated from the circuit module C, and the sub-module E instantiated from the sub-module D. It is very tedious to manually add the sub-modules D and E into the file (for example, a table) recording the information of the intermediate modules. Therefore, a level information "Level" is provided. If the hierarchy of the circuit module C is filled in the "Hierarchy" column, and 2 is filled in the "Level" column, it means that the circuit module C, the modules D, E and F in the two levels below the circuit module C are all included in the intermediate modules through which the object path passes, thereby reducing the tediousness of obtaining the intermediate modules. If only the circuit module C needs to be added, and the sub-module instantiated from the circuit module C does not need to be added, 0 is filled in the "Level" column. If the design of the circuit module C is not clear, and it is only known that the object path passes through the circuit module C and some sub-modules below the circuit module C, "all" is filled in the "Level" column, which means that the circuit module C and all the modules in the levels below the circuit module C are included in the intermediate modules through which the object path passes.

[0089] For step S22, for example, according to the level of each to-be-added module, the sub-modules in the level of each to-be-added module are extracted from the hierarchy information, and each object path passes through at least one intermediate module including the to-be-added module and the sub-modules.

[0090] For example, the intermediate module description file is an add.csv file in Figure 3 The add.csv file is read to obtain that the to-be-added modules include CHIP.M, CHIP.N and CHIP.L, and the add.csv file is read to further obtain that the object path passes through the sub-modules in the first level of the circuit module M, the sub-modules in the first level and the sub-modules in the second level of the circuit module N, and all the sub-modules included in the circuit module L. According to the information obtained by reading the add.csv file, for example, the sub-modules in the first level of the circuit module M are M1, the first level of the circuit module N includes the sub-module N1 and the sub-module N2, and the sub-module N1 includes the sub-module N11 in the second level, and the like, which are extracted from the hierarchy.log file described above. Therefore, the at least one intermediate module through which the object path passes can include the circuit module M, the sub-module M1, the circuit module N, the sub-module N1, the sub-module N2 and the sub-module N11, and the like.

[0091] For step S23, the union refers to the merging of elements in multiple sets into one set. For example, the elements in the set obtained by merging the source module, the destination module and the at least one intermediate module in the multiple object paths are the multiple first circuit modules. There is no repeated circuit module in the set obtained after merging. For example, only one of the repeated circuit modules in the source module, the destination module and the at least one intermediate module in the multiple object paths is retained, thereby obtaining the union of the source module, the destination module and the at least one intermediate module of all the object paths.

[0092] For example, the multiple object paths include a first object path and a second object path, and the multiple first circuit modules of the first object path may, for example, include circuit module P1, circuit module P2 and circuit module P3, and the multiple first circuit modules of the second object path may also include circuit module Q1, circuit module P2 and circuit module Q2. Here, circuit module P2 is a repeated circuit module for the first object path and the second object path, and therefore only one circuit module P2 is retained. Therefore, the multiple first circuit modules obtained after the union processing include circuit module P1, circuit module P2 and circuit module P3, circuit module Q1 and circuit module Q2.

[0093] For step S30, for example, the required second circuit module is obtained by using the command (for example, –set_blackbox–exclude{}) provided by the verification tool in the black box setting mode, and a black box file is generated according to the module information of the second circuit module. The command –set_blackbox–exclude{} is used to generate a black box file according to the circuit modules in the integrated circuit design except those in the curly braces after –exclude{}. For example, the user can input the multiple first circuit modules into the curly braces after –exclude{}, and the verification tool can automatically generate a black box file.

[0094] For example, –set_blackbox–exclude{CHIP,A,A1,A2,B,B1,B2,B11…}, the verification tool sets the circuit modules in the integrated circuit design except {CHIP,A,A1,A2,B,B1,B2,B11…} as a black box file.

[0095] Figure 2A A flowchart of another method for generating a black box file provided by at least one embodiment of the present disclosure is shown.

[0096] As shown in Figure 2A The method includes steps S301-S309.

[0097] Step S301: Read the chip logic design file of the integrated circuit, for example, the RTL file.

[0098] Step S302: Start the connection checking tool interactive interface. For example, execute the start_gui command recognizable by the connection checking tool to enter the graphical interactive interface of the connection checking tool.

[0099] Step S303: For example, the hierarchy of the integrated circuit design is displayed in the graphical interactive interface, right-click the “Hierarchy” window in the graphical interactive interface, and output the entire integrated circuit hierarchy to a hierarchy file through the “Export Hierarchy” option in the pop-up dialog box. The file is saved as hierarchy.log, for example.

[0100] Step S304: Obtain the path information file, which is the add.tcl file described above, for example.

[0101] Step S305: Obtain the intermediate module description file, which is the add.csv file described above, for example.

[0102] Step S306: For example, extract the source module name and destination module name in the path information file (saved as the add.tcl file, for example) and find the corresponding circuit module in the hierarchy file (hierarchy.log).

[0103] Step S307: Extract the module information (for example, the information in the “Hierarchy” column) and the corresponding sub-level information (the information in the “Level” column) in the intermediate module description file (for example, the add.csv file) and find the required intermediate module in the hierarchy file (hierarchy.log). Figure 4

[0104] Step S308: Remove duplicate circuit modules to obtain a plurality of first circuit modules including the union of the source module, the destination module, and at least one intermediate module of the object path. For example, execute the step S23 described above. Figure 4

[0105] Step S309: For example, generate a black box file using the –set_blackbox–exclude{} provided by the verification tool.

[0106] ​​At least one embodiment of the present disclosure further provides a verification method for verifying an object path in an integrated circuit design. The verification method can include obtaining a black box file according to the generation method of any of the above embodiments; obtaining a path information file of the object path; and verifying the object path based on the path information file and the black box file to generate a verification result. The verification method can simplify the cumbersome steps of the black box file, alleviate the problem of failure of the verification tool to automatically generate the black box file, greatly reduce the time required for verification, and improve the verification efficiency.

[0107] Figure 5 A flowchart of a verification method for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown.

[0108] As shown in Figure 5 , the verification method can include steps S401-S403.

[0109] Step S401: Obtain a black box file according to the generation method of the black box file.

[0110] Step S402: Obtain a path information file of the object path.

[0111] Step S403: Verify the object path based on the path information file and the black box file to generate a verification result.

[0112] In the above verification method, for step S401, the black box file can be generated according to the generation method of any of the above embodiments.

[0113] In the above verification method, for step S402, the path information file is, for example, the add.tcl file described above. The path information file can be written by the user himself. For example, according to the access path input by the user, the path information file is read.

[0114] In some other embodiments of the present disclosure, for example, the path information file can be automatically generated. For example, the object path includes at least one buffer, buffer information of the at least one buffer in the object path is extracted from a buffer description file for the integrated circuit design; path description information of the object path is extracted from a chip logic design file (for example, an RTL file) of the integrated circuit design according to the buffer information; and a path information file including path information of the object path is generated according to the path description information.

[0115] For step S403, for example, the verification tool reads the path information file and the black box file, and verifies the object path according to the path information file and the black box file to generate a verification result.

[0116] Figure 6A flowchart of another verification method for verifying an object path in an integrated circuit design is shown.

[0117] As shown in Figure 6 , the verification method can include steps S501-S507.

[0118] Step S501: Obtain a chip logic design file (e.g., an RTL file) of an integrated circuit design.

[0119] Step S502: Obtain a path information file, e.g., the add.tcl file described above.

[0120] Step S503: Obtain a black box file according to the generation method of a black box file provided by any embodiment of the present disclosure. By setting modules unrelated to the path to be tested in the integrated circuit design as black boxes, the analysis efficiency of the verification tool can be improved.

[0121] Step S504: Obtain a verification script (e.g., a run.tcl file) for running the verification tool. For example, the verification tool can be a connection checking tool, and the run.tcl file can include basic setting commands of the connection checking tool, commands for reading the black box file, commands for reading the design file, commands for reading the path description file, and commands for starting path checking.

[0122] Step S505: Run the run.tcl file.

[0123] Step S506: Generate a verification result, which can be a result file vcf.log, for example.

[0124] Step S507: Debug the path that fails the verification through a debugging command or an interactive interface. For example, analyze the reason for the verification failure, modify the integrated circuit design, or modify the path information file add.tcl.

[0125] Figure 1A A schematic block diagram of a black box file generation apparatus 600 is shown.

[0126] For example, as shown in Figure 1A , the black box file generation apparatus 600 includes a structure information obtaining unit 610, a circuit module determining unit 620, and a black box generating unit 630. The black box file is used for verifying an object path in an integrated circuit design.

[0127] The structure information obtaining unit 610 is configured to obtain hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information includes structure information and module information of the integrated circuit design. The hierarchical structure information can also include the instance name of each level.

[0128] The structure information obtaining unit 610 may, for example, perform Figure 1A Step S10 described.

[0129] The circuit module determining unit 620 is configured to determine, using the hierarchy information, a plurality of first circuit modules related to the object paths in the integrated circuit design.

[0130] The circuit module determining unit 620 may, for example, perform Figure 6 Step S20 described.

[0131] The black box generating unit 630 is configured to generate the black box file according to module information of second circuit modules in the plurality of circuit modules of the integrated circuit design, except the plurality of first circuit modules.

[0132] The black box generating unit 630 may, for example, perform Figure 7 Step S30 described.

[0133] For example, in the generation apparatus provided by an embodiment of the present disclosure, the number of object paths is greater than or equal to 2, the circuit module determining unit includes: a module determining subunit configured to determine a source module and a destination module of each object path; a module obtaining subunit configured to obtain at least one intermediate module passed by each object path using the hierarchy information; and a calculating subunit configured to calculate a union set of the source module, the destination module, and the at least one intermediate module of all object paths to obtain the plurality of first circuit modules.

[0134] For example, in the generation apparatus provided by an embodiment of the present disclosure, the module obtaining subunit includes: a description file obtaining subunit configured to obtain an intermediate module description file of the integrated circuit design; and an intermediate module obtaining subunit configured to obtain the at least one intermediate module passed by each object path according to the intermediate module description file in combination with the hierarchy information.

[0135] For example, in the generation apparatus provided by an embodiment of the present disclosure, the intermediate module description file includes at least one to-be-added module and a sub-level of each to-be-added module; the intermediate module obtaining subunit includes: an extracting subunit configured to extract a sub-module in the sub-level of each to-be-added module from the hierarchy information according to the sub-level of each to-be-added module, and the at least one intermediate module passed by each object path includes the to-be-added module and the sub-module.

[0136] For example, in the generation apparatus provided by an embodiment of the present disclosure, the module determining subunit includes: a path information file obtaining subunit configured to obtain a path information file of the integrated circuit design; and a path module determining subunit configured to extract the source module and the destination module of the object path from the path information file.

[0137] For example, in the generation apparatus provided by an embodiment of the present disclosure, the structure information obtaining unit comprises: a design file obtaining subunit configured to obtain a chip logic design file of the integrated circuit design; and a hierarchy information obtaining subunit configured to obtain the hierarchy information of the integrated circuit design based on the chip logic design file.

[0138] For example, the structure information obtaining unit 610, the circuit module determining unit 620 and the black box generating unit 630 can be hardware, software, firmware and any feasible combination thereof. For example, the structure information obtaining unit 610, the circuit module determining unit 620 and the black box generating unit 630 can be a special-purpose or general-purpose circuit, chip or device, etc., or a combination of a processor and a memory. The specific implementation form of each unit is not limited in the embodiments of the present disclosure.

[0139] It should be noted that in the embodiments of the present disclosure, each unit of the generation apparatus 600 corresponds to each step of the verification method described above, and the specific functions of the generation apparatus 600 can be referred to the related description of the generation method, which will not be described here. Figure 7 The components and structures of the generation apparatus 600 shown are only exemplary and are not limiting, and the generation apparatus 600 can also include other components and structures as needed.

[0140] Figure 4 A schematic block diagram of a verification apparatus 700 for verifying an object path in an integrated circuit design is shown.

[0141] For example, as shown in the figure, the verification apparatus 700 can include a black box obtaining unit 710, a path information obtaining unit 720 and a verification unit 730. Figure 4

[0142] The black box obtaining unit 710 is configured to obtain a black box file according to the generation method provided by any embodiment of the present disclosure.

[0143] The black box obtaining unit 710 may, for example, perform the steps S401 described above. Figure 4

[0144] The path information obtaining unit 720 is configured to obtain a path information file of the object path.

[0145] The path information obtaining unit 720 may, for example, perform the steps S402 described above. Figure 7

[0146] The verification unit 730 is configured to verify the object path based on the path information file and the black box file to generate a verification result. ​​​

[0147] The verification unit 730 may, for example, perform Figure 8 The step S403 described.

[0148] For example, the black box acquisition unit 710, the path information acquisition unit 720, and the verification unit 730 can be hardware, software, firmware, and any feasible combination thereof. For example, the black box acquisition unit 710, the path information acquisition unit 720, and the verification unit 730 can be a special-purpose or general-purpose circuit, chip, or device, or a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation forms of the above-mentioned units.

[0149] It should be noted that in at least one embodiment of the present disclosure, the units of the verification device 700 correspond to the steps of the above-mentioned verification method, and the specific functions of the verification device 700 can be referred to the related description of the verification method, which will not be repeated here. Figure 8 The components and structures of the verification device 700 shown are only exemplary and are not limiting, and the verification device 700 can also include other components and structures as needed.

[0150] At least one embodiment of the present disclosure also provides an electronic device including a processor and a memory including one or more computer program instructions. The one or more computer program instructions are stored in the memory and implemented by the processor to implement the instructions of the above-mentioned black box file generation method or verification method. The electronic device can improve the cumbersome steps of simplifying the generation of the black box file, improve the generation efficiency of the black box file, and improve the verification efficiency.

[0151] Figure 9 A schematic block diagram of an electronic device provided by some embodiments of the present disclosure is shown. As Figure 9 The electronic device 800 includes a processor 810 and a memory 820. The memory 820 is used to store non-transitory computer readable instructions (such as one or more computer program modules). The processor 810 is used to run the non-transitory computer readable instructions, and the non-transitory computer readable instructions can perform one or more steps of the above-mentioned bus device design method when executed by the processor 810. The memory 820 and the processor 810 can be interconnected by a bus system and / or other forms of connection mechanism (not shown).

[0152] For example, the processor 810 can be a central processing unit (CPU), a graphics processing unit (GPU), or other form of processing unit having data processing and / or program executing capabilities. For example, the central processing unit (CPU) can be of X86 or ARM architecture, etc. The processor 810 can be a general purpose processor or a special purpose processor, and can control other components in the electronic device 800 to perform desired functions.

[0153] For example, the memory 820 can include any combination of one or more computer program products. The computer program product can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, and / or the like. One or more computer program modules can be stored on the computer-readable storage media, and the processor 810 can run the one or more computer program modules to implement various functions of the electronic device 800. Various application programs and various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0154] It should be noted that, in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 800 can refer to the description of the design method of the bus device above, and will not be described here.

[0155] Figure 9 Another schematic block diagram of an electronic device is provided for some embodiments of the present disclosure. The electronic device 900 is suitable for implementing the design method of the bus device provided by the embodiments of the present disclosure, for example. The electronic device 900 can be a terminal device, etc. It should be noted that, Figure 9 The electronic device 900 shown is only an example, which does not bring any limitation to the functions and use range of the embodiments of the present disclosure.

[0156] As Figure 10 shown, the electronic device 900 can include a processing device (such as a central processor, a graphics processor, etc.) 910, which can perform various appropriate actions and processes according to programs stored in a read-only memory (ROM) 920 or programs loaded from a storage device 980 to a random access memory (RAM) 930. Various programs and data required for the operation of the electronic device 900 are also stored in the RAM 930. The processing device 910, the ROM 920, and the RAM 930 are connected to each other through a bus 940. An input / output (I / O) interface 950 is also connected to the bus 940.

[0157] Generally, the following devices can be connected to the I / O interface 950: input devices 960 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; output devices 970 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, and the like; storage devices 980 including, for example, a tape, a hard disk, and the like; and communication devices 990. The communication devices 990 can allow the electronic device 900 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although Figure 10 The electronic device 900 is shown with various devices, but it is understood that not all of the shown devices are required to be implemented or possessed, and the electronic device 900 can instead implement or possess more or fewer devices.

[0158] For example, according to embodiments of the present disclosure, the above-mentioned generation method and verification method of the black box file can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product including a computer program carried on a non-transitory computer readable medium, the computer program including program code for executing the above-mentioned design method of the bus device. In such embodiments, the computer program can be downloaded and installed from a network through the communication device 990, or installed from the storage device 980, or installed from the ROM 920. When the computer program is executed by the processing device 910, the functions defined in the generation method and verification method of the black box file provided by embodiments of the present disclosure can be implemented.

[0159] At least one embodiment of the present disclosure also provides a computer readable storage medium for storing non-transitory computer readable instructions which, when executed by a computer, can implement the above-mentioned generation method and verification method of the black box file. With the computer readable storage medium, the cumbersome steps of simplifying the generation of the black box file can be improved, the generation efficiency of the black box file can be improved, and the verification efficiency can be improved.

[0160] Figure 8 A schematic diagram of a storage medium provided for some embodiments of the present disclosure is shown. As Figure 8 shown, the storage medium 1000 is used to store non-transitory computer readable instructions 1010. For example, when the non-transitory computer readable instructions 1010 are executed by a computer, one or more steps according to the above-mentioned generation method and verification method of the black box file can be performed.

[0161] For example, the storage medium 1000 can be applied in the above-mentioned electronic device 800. For example, the storage medium 1000 can be the memory 820 in the electronic device 800 as ​ shown. For example, the relevant description of the storage medium 1000 can refer to ​The corresponding description of the memory 820 in the electronic device 800 shown here will not be repeated.

[0162] The following points need to be explained:

[0163] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0164] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined to obtain new embodiments.

[0165] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for generating black-box files, wherein, The black-box file is used to verify object paths in integrated circuit design, and the generation method includes: Obtain the hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information includes the structural information and module information of the integrated circuit design; Using the hierarchical information, multiple first circuit modules related to the object path in the integrated circuit design are identified; and The black-box file is generated based on the module information of the second circuit module in the integrated circuit design, wherein the second circuit module is a module in the integrated circuit design other than the plurality of first circuit modules. The plurality of first circuit modules include a source module, a destination module, and at least one intermediate module traversed by the object path. The source module is the circuit module where the starting point of the object path is located, and the destination module is the circuit module where the ending point of the object path is located. The at least one intermediate module includes at least one module to be added and sub-modules of each module to be added. Each of the at least one intermediate module is obtained based on an intermediate module description file. The intermediate module description file includes the at least one module to be added and sub-levels of each module to be added, and the sub-modules are located in the sub-levels.

2. The generation method according to claim 1, wherein, The number of object paths is greater than or equal to 2. Using the hierarchical information, the plurality of first circuit modules related to the object path in the integrated circuit design are determined, including: Determine the source and destination modules for each object path; Using the hierarchical information, at least one intermediate module traversed by each object path is obtained; and The plurality of first circuit modules are obtained by obtaining the union of the source module, the destination module and at least one intermediate module of the object path.

3. The generation method according to claim 2, wherein, Using the hierarchical information, obtaining the at least one intermediate module traversed by each object path includes: Obtain the intermediate module description file of the integrated circuit design; and Based on the intermediate module description file and the hierarchical structure information, the at least one intermediate module traversed by each object path is obtained.

4. The generation method according to claim 3, wherein, The intermediate module description file includes at least one module to be added and sub-levels for each module to be added; Based on the intermediate module description file and the hierarchical structure information, at least one intermediate module traversed by each object path is obtained, including: Based on the sub-level of each module to be added, extract the sub-module located in the sub-level of each module to be added from the hierarchical structure information. The at least one intermediate module traversed by each object path includes the module to be added and the sub-module.

5. The generation method according to claim 2, wherein, Determining the source module and the destination module for each object path includes: Obtain the path information file of the integrated circuit design; and Extract the source module and the destination module of the object path from the path information file.

6. The generation method according to any one of claims 1 to 5, wherein, Obtaining the hierarchical structure information of the integrated circuit design includes: Obtain the chip logic design file of the integrated circuit design; and The hierarchical structure information of the integrated circuit design is obtained based on the chip logic design file.

7. A verification method for verifying object paths in integrated circuit design, comprising: The black-box file is obtained by the generation method according to any one of claims 1 to 6; Obtain the path information file of the object path; as well as Based on the path information file and the black-box file, the object path is verified to generate a verification result.

8. An apparatus for generating black-box files, wherein, The black-box file is used to verify object paths in integrated circuit design, and the device includes: The structural information acquisition unit is configured to acquire the hierarchical structure information of the integrated circuit design, wherein the hierarchical structure information includes the structural information and module information of the integrated circuit design; A circuit module determination unit is configured to use the hierarchical information to determine a plurality of first circuit modules in the integrated circuit design that are related to the object path; and The black-box generation unit is configured to generate the black-box file based on module information of a second circuit module (excluding the plurality of first circuit modules) among the plurality of circuit modules in the integrated circuit design. The plurality of first circuit modules include a source module, a destination module, and at least one intermediate module traversed by the object path. The source module is the circuit module where the starting point of the object path is located, and the destination module is the circuit module where the ending point of the object path is located. The at least one intermediate module includes at least one module to be added and sub-modules of each module to be added. Each of the at least one intermediate module is obtained based on an intermediate module description file. The intermediate module description file includes the at least one module to be added and sub-levels of each module to be added, and the sub-modules are located in the sub-levels.

9. A verification apparatus for verifying object paths in integrated circuit design, comprising: The black-box acquisition unit is configured to acquire the black-box file using the generation method according to any one of claims 1 to 6; The path information acquisition unit is configured to acquire the path information file of the object path; as well as The verification unit is configured to verify the object path and generate a verification result based on the path information file and the black-box file.

10. An electronic device, comprising: processor; Memory, which includes one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the generation method according to any one of claims 1-6 or the verification method according to claim 7.

11. A computer-readable storage medium that non-transitoryly stores computer-readable instructions, wherein, When the computer-readable instructions are executed by a processor, they implement the generation method of any one of claims 1-6 or the verification method of claim 7.

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