A method for preparing a semiconductor device structure

Abstract

The present invention provides a method for preparing a semiconductor device structure. The preparation method includes: forming a mask pattern layer on a substrate, and forming spaced trenches and active regions in the substrate based on the mask pattern layer; removing a part of the mask pattern layer to expose the top corners of the active regions, and forming a first oxide layer on the trench surfaces to cover the exposed top corners and the trench surfaces; filling the trenches with an insulator to form a first insulating layer, and etching the first insulating layer and the first oxide layer to expose the top corners of the active regions; implanting a halogen element into the top corners, and removing the active regions implanted with the halogen element by an etching process; forming a second oxide layer on the surfaces of the top corners of the active regions, and filling the trenches with an insulator to form a second insulating layer. By implanting a halogen element into the top corners of the active regions, the present invention controls the etching rate of the top corners of the active regions, effectively controls the rounding of the top corners of the active regions, thereby reducing the influence of parasitic devices caused by the uneven shape of the top corners, and is beneficial to improving the device reliability.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and particularly relates to a method for preparing a semiconductor device structure. Background Art

[0002] After the microelectronic process enters the deep sub-micron stage, in order to achieve high-density and high-performance device circuits, the isolation and planarization processes are becoming increasingly important. Among them, the shallow trench isolation (STI) process has received much attention. The STI process realizes excellent isolation performance and a flat surface through a silicon nitride isolation layer. However, at the edge top corners of the active region and the shallow trench of its device, parasitic devices are likely to be generated due to the uneven morphology, thus affecting the switching performance of the device.

[0003] In the prior art, the silicon nitride above the top corner of the active region is etched back by a hot phosphoric acid solution to expose the top corner, and then an oxide layer is grown on the trench surface including the top corner to round the top corner. However, due to the inability to precisely control the growth shape of the oxide layer at the top corner of the active region during the process, the rounding effect is not ideal. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for preparing a semiconductor device structure, which is used to solve the problem that the shape of the rounding of the top corner of the active region in the prior art cannot be precisely controlled.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor device structure, and the preparation method includes the following steps:

[0006] Provide a substrate, form a mask pattern layer on the substrate, form spaced-apart trenches in the substrate based on the mask pattern layer, and separate a plurality of active regions in the substrate through the trenches;

[0007] Remove a part of the mask pattern layer to expose the top corner of each active region;

[0008] Form a first oxide layer on the trench surface, and the first oxide layer covers the exposed top corner of each active region and the trench surface;

[0009] Fill the trench with an insulator for the first time to form a first insulating layer;

[0010] Etch the first insulating layer and the first oxide layer in the trench to expose the top corner of each active region;

[0011] Inject a halogen element at the top corner, and use an etching process to remove the part of the halogen element injected at the top corner of each active region. By controlling the distribution of the halogen element at the top corner of each active region, the etching morphology of the top corner is controlled.

[0012] Form a second oxide layer at the top corner of each active region.

[0013] Fill the trench with an insulator for the second time to form a second insulating layer.

[0014] Optionally, the mask pattern layer includes a pad oxide layer, a silicon nitride layer, and an oxide layer. The pad oxide layer is located on the substrate, the silicon nitride layer is located on the pad oxide layer, and the oxide layer is located on the silicon nitride layer.

[0015] Optionally, use a wet etching method with a hot phosphoric acid solution to remove part of the mask pattern layer to expose the top corner of each active region.

[0016] Optionally, both the first insulating layer and the second insulating layer are formed by a high-density plasma oxide filling method.

[0017] Optionally, etch the first insulating layer in the trench by a wet etching method to expose the top corner of each active region.

[0018] Optionally, use a wet etching method to remove the part of the halogen element injected at the top corner of each active region.

[0019] Optionally, both the first oxide layer and the second oxide layer are formed by a furnace process.

[0020] Optionally, the thickness of the second oxide layer is equal to the thickness of the first oxide layer.

[0021] Optionally, the thickness of the first oxide layer is 100 angstroms.

[0022] Optionally, the halogen element includes one or any combination of fluorine, chlorine, bromine, iodine, astatine, and tennessine.

[0023] As described above, the preparation method of the semiconductor device structure of the present invention has the following beneficial effects:

[0024] By ion-injecting a halogen element at the top corner of the active region, the present invention controls the etching rate of the top corner of the active region, effectively controls the rounding of the top corner of the active region, thereby reducing the influence of parasitic devices caused by the uneven shape of the top corner, and is beneficial to improving device reliability. Description of the Drawings

[0025] Figures 1-9It shows a schematic structural diagram presented by each step of the preparation method of the semiconductor device structure in the embodiment of the present invention.

[0026] Description of component labels

[0027] 100 substrate 101 groove 102 active region 200 mask pattern layer 201 pad oxide layer 202 silicon nitride layer 203 oxide layer 300 top corner 301 first oxide layer 302 halogen element implantation beam 303 second oxide layer 401 first insulating layer 402 second insulating layer Specific embodiments

[0028] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] When detailing the embodiments of the present invention, for ease of explanation, the schematic diagrams showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0030] For convenience of description, spatial relationship terms such as "beneath", "below", "lower", "under", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation in addition to the directions depicted in the drawings.

[0031] In the context of the present application, the structure in which the first feature is "above" the second feature described may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0032] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0033] In the shallow trench isolation (STI) technology, the growth rate of the oxide layer at the top corner of the active region is smaller than that of the surface of the active region at other positions, resulting in a thinner oxide layer at the top corner of the active region, thus generating an uneven shape, which easily causes charge concentration, leading to channel edge inversion, thereby generating a low-threshold path. Combined with the thinner oxide layer, it is easy to cause an increase in the subthreshold leakage current of the active device, form parasitic devices, generate the double-peak effect or the warping effect, and at the same time reduce the breakdown voltage of the oxide layer, thus affecting the switching performance and reliability of the semiconductor device. In the existing technology, generally, the silicon nitride layer and the pad oxide layer of the STI device are wet etched back with a hot phosphoric acid solution to expose the top corner, and then an oxide layer is grown at the top corner. The rounding of the top corner of the active region is achieved by oxidizing the material at the top corner of the active region during its growth process. However, due to the difficulty in controlling the specific morphology of the oxide layer grown at the top corner of the active region, it is impossible to achieve an ideal rounding effect for the sharp shape of the top corner of the active region. Embodiment 1

[0034] To solve the above technical problems, as Figure 1 shown, and referring to Figures 2~9 , the present invention provides a method for preparing a semiconductor device structure. The preparation method includes the following steps:

[0035] Step 1): Provide a substrate 100, form a mask pattern layer on the substrate 100, and form spaced-apart trenches 101 in the substrate 100 based on the mask pattern layer, and separate a plurality of active regions 102 in the substrate 100 through the trenches 101;

[0036] Step 2): Remove part of the mask pattern layer to expose the top corner 300 of each active region 102;

[0037] Step 3): Form a first oxide layer 301 on the surface of the trenches 101. The first oxide layer 301 covers the exposed top corner 300 of each active region 102 and the surface of the trenches 101;

[0038] Step 4): First fill the trenches 101 with an insulator to form a first insulating layer 401;

[0039] Step 5): Etch the first insulating layer 401 and the first oxide layer 301 in the trenches 101 to expose the top corner 300 of each active region 102;

[0040] Step 6): Ion implant a halogen element at the top corner 300, and use an etching process to remove the part of the halogen element implanted at the top corner 300 of each active region 102, and control the etching morphology of the top corner 300 by controlling the distribution of the halogen element at the top corner 300 of each active region 102;

[0041] Step 7): Form a second oxide layer 303 at the top corner 300 of each active region 102;

[0042] Step 8): The trench 101 is filled for the second time with an insulator to form a second insulating layer 402.

[0043] The preparation method of the semiconductor device structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the preparation method sequence of the semiconductor device structure protected by the present invention, and those skilled in the art can change it according to the actual measurement steps. Figures 1-9 Only the preparation method steps of the semiconductor device structure in one example are shown.

[0044] First, as Figure 1 shown, perform Step 1), provide a substrate 100, form a mask pattern layer on the substrate 100, and form spaced trenches 101 in the substrate 100 based on the mask pattern layer, and each active region 102 is separated in the substrate 100 through the trenches 101.

[0045] As an example, the substrate 100 is silicon, and other suitable materials such as gallium nitride, gallium arsenide, silicon carbide, indium phosphide, etc. can also be selected according to actual needs. Practitioners should replace the materials and conditions of etching, filling, growth, etc. in the subsequent steps according to different substrate 100 materials to successfully prepare the target device.

[0046] Specifically, when forming the trench 101, first etch the mask pattern layer 200 with photoresist as an etching mask, and the etching position is the preset trench 101 position; then form the trench 101 on the substrate 100 through dry etching. Preferably, a fluorination technique is used to improve the etching resistance of the photoresist.

[0047] Specifically, the trench 101 is etched in the substrate 100 by reactive ion etching (RIE). Preferably, fluorination is performed during the RIE process to form a trench 101 with a smooth bottom corner and inclined sidewalls, which helps to improve the filling quality in subsequent steps and the electrical characteristics of the trench 101 structure. RIE can achieve a large aspect ratio trench 101 through excellent anisotropic etching, and at the same time cause less damage to the substrate 100. Preferably, the substrate 100 is subjected to soft etching before RIE etching, so that a wedge-shaped slope descending from the edge to the center is formed at the position where the trench 101 is etched, so as to more easily obtain a uniform circular top angle 300 at the surface edge of each active region 102.

[0048] As an example, the mask pattern layer includes a pad oxide layer 201, a silicon nitride layer 202, and an oxide layer 203. The pad oxide layer 201 is located on the substrate 100, the silicon nitride layer 202 is located on the pad oxide layer 201, and the oxide layer 203 is located on the silicon nitride layer 202. Among them, the silicon nitride layer 202 serves as an isolation mask. Since the oxidation rate of silicon nitride is slow, it can protect the underlying substrate 100 from oxidation. To prevent the stress of silicon nitride from generating interface states on the substrate 100 and causing defects, the pad oxide layer 201 is used as a buffer layer to release the stress between the silicon nitride and the substrate 100, improve the interface characteristics between the substrate 100 and the oxide filled in the subsequent steps, and at the same time improve the adhesion between the substrate 100 and the silicon nitride layer 202. Specifically, the silicon nitride layer 202 serves as a polishing stop layer during the subsequent chemical mechanical polishing (CMP) for planarization, and the thickness of the silicon nitride layer 202 should ensure that the device step height after CMP is sufficient to allow cleaning and etching before the growth of the gate oxide.

[0049] As an example, the pad oxide layer 201 is formed by thermal oxidation to improve the quality of the pad oxide layer 201 and enhance its ability to protect the substrate 100. Specifically, the oxidation temperature and oxidation time of thermal oxidation are determined by the thickness of the pad oxide layer 201 preset by the practitioners.

[0050] As an example, the thickness of the deposited oxide layer is between 100 angstroms and 200 angstroms.

[0051] Preferably, the thickness of the pad oxide layer 201 is 100 angstroms.

[0052] Optionally, the silicon nitride layer 202 is prepared by growing a silicon nitride thin film through plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). Specifically, when the required silicon nitride thickness is less than 20 nm, PECVD is selected to prepare the silicon nitride layer 202 to produce a silicon nitride layer 202 with good quality and dense structure in the case of a relatively thin growth thickness; when the internal metal lines of the device are complex and dense, the LPCVD method is selected to prepare the silicon nitride layer 202 to be carried out under lower temperature conditions to avoid the influence of high temperature on the metal lines.

[0053] As an example, the material of the oxide layer 203 is silicon dioxide, and the oxide layer 203 serves as a mask for etching the silicon nitride layer 202, and its masking effect is stronger than that of ordinary photoresist.

[0054] Next, as Figure 2 shown, step 2) is performed to remove part of the mask pattern layer to expose the apex 300 of each active region 102.

[0055] As an example, a wet etching method using a hot phosphoric acid solution is used to remove part of the mask pattern layer to expose the apex angle 300 of each active region 102. Since phosphoric acid does not react with silicon dioxide, the hot phosphoric acid solution has good uniformity and high selectivity when etching silicon nitride, and can achieve good etch-back. Preferably, the volume percentage of the hot phosphoric acid solution is 80% to 88%, and the solution temperature is 155°C to 165°C.

[0056] Then, as Figure 3 shown, step 3) is performed to form a first oxide layer 301 on the surface of the trench 101. The first oxide layer 301 covers the exposed apex angle 300 of each active region 102 and the surface of the trench 101. The first oxide layer 301 is used to round the apex angle 300 of each active region 102 in subsequent steps, improve the insulation of the apex angle 300, and reduce the damage introduced on the surface of the substrate 100 during the etching process. Preferably, the thickness of the first oxide layer 301 is the same as the thickness of the pad oxide layer 201.

[0057] Preferably, the first oxide layer 301 is formed by a furnace tube process. Specifically, the furnace tube process uses thermal oxidation for chemical vapor deposition (CVD) to improve the electrical quality of the first oxide layer 301.

[0058] Next, as Figure 4 shown, step 4) is performed to fill the trench 101 with an insulator for the first time to form a first insulating layer 401. The first insulating layer 401 is formed by a high density plasma (HDP) oxide filling method. Since HDP uses an alternating filling method of deposition and etching, it avoids the generation of voids or pinching off in the case of a large aspect ratio. Specifically, the reaction gases used in the HDP process include oxygen, silane used in the chemical vapor deposition process, and hydrogen used in the sputtering process. Practitioners can adjust the ratios of oxygen, silane, and hydrogen according to the actual device type and aspect ratio to avoid chamfering and void generation and obtain the best filling effect.

[0059] Preferably, after the first HDP filling, steam annealing is first performed to eliminate the gaps in the first insulating layer 401; then nitrogen annealing is performed to make the first insulating layer 401 denser, so that the corrosion rate of the filled first insulating layer 401 is reduced to be close to the corrosion rate of the pad oxide layer 201, reducing the loss of the filled insulator during the surface cleaning process before the growth of the gate oxide layer due to the corrosion rate of the deposited insulator during the HDP filling process being higher than the corrosion rate of the pad oxide layer 201, and preventing the edge leakage of the STI structure from being aggravated. Specifically, the nitrogen annealing process is carried out at 900°C.

[0060] As an example, the insulator used for the first filling is silicon dioxide.

[0061] Then, as Figure 5As shown, step 5) is performed to etch the insulating layer in the trench 101 to expose the apex angle 300 of each active region 102. Specifically, the insulating layer in the trench 101 is etched until the top of the insulating layer is lower than the top of the trench 101.

[0062] As an example, the top of the etched insulating layer is 1 - 7 nm lower than the top of the shallow trench 101.

[0063] As an example, a wet etching method is used to etch the insulating layer in the trench 101 to expose the apex angle 300 of each active region 102. Wet etching has high selectivity for materials and is easier to obtain a precise micro-profile.

[0064] In another example, a dry etching process is used to etch the insulating layer so that the thickness of the insulating layer above the silicon nitride layer 202 is a predetermined thickness; then a wet etching process is used to etch the insulating layer so that the top of the insulating layer in the trench 101 is lower than the top of the trench 101 to expose the apex angle 300 of each active region 102. The above combined etching method can improve the etching efficiency, reduce the etching cost, improve the flatness of the etched surface, and at the same time ensure the precision of the etching at the apex angle 300.

[0065] Next, as Figure 6 shown, step 6) is performed to implant a halogen element at the apex angle 300 through the halogen element implantation beam 302, and by controlling the distribution of the halogen element at the apex angle 300 of each active region 102, the etching morphology of the apex angle 300 is controlled.

[0066] As an example, the halogen element includes one of fluorine, chlorine, bromine, iodine, astatine, and tennessine.

[0067] The present invention changes the etching rate of each active region 102 implanted with a halogen element by utilizing the strong oxidizing property of the halogen element, thereby achieving the purpose of controlling the specific shape at the apex angle 300 of each active region 102 to precisely control the rounding of the apex angle 300 of each active region 102.

[0068] Specifically, after the halogen element is ion-implanted, a rapid thermal annealing process is performed on the implanted region to make the implantation effect in the implanted region more uniform, so as to improve the control accuracy of the shape at the apex angle 300 of each active region 102.

[0069] As an example, when ion-implanting, the halogen element implantation beam 302 rotates and implants at a preset angle with the normal of the substrate 100 as the rotation center to achieve uniform ion implantation dose at the apex angle 300 of each active region 102 at various positions.

[0070] Specifically, the implantation angle of the halogen element implantation beam 302 forms a preset angle with the top surface of each active region 102. The preset angle is determined by the longitudinal depth of the trench 101, the top opening width of the trench 101, and the thickness of the mask pattern layer 200, so as to ensure that ions can be implanted into the apex region 300 through the preset angle.

[0071] Specifically, the ion implantation energy of the halogen element implantation beam 302 should ensure that ions do not pass through the mask pattern layer 200 to reach the surface of each active region 102. As an example, the ion implantation energy is 5 Kev - 10 Kev. Preferably, the ion implantation is carried out in multiple times with multiple energies to improve the uniformity of ion implantation at the apex 300.

[0072] Then, as Figure 7 shown, step 7) is carried out to remove the first oxide layer 301 at the apex 300 and the part of each active region 102 containing the halogen element implantation through an etching process. The oxide layer near each un-implanted active region 102 will also be etched during the above etching process. However, since the etching rate of each active region 102 after ion implantation of the halogen element in step 6) can generally increase by several hundred times, the degree of etching of each un-implanted active region 102 will not significantly affect the morphology of the apex 300 of each active region 102.

[0073] As an example, a wet etching method is used to remove the first oxide layer 301 at the apex 300 and the part of each active region 102 containing the halogen element implantation.

[0074] Next, as Figure 8 shown, step 8) is carried out to form a second oxide layer 303 at the apex 300 of each active region 102.

[0075] Preferably, the second oxide layer 303 is formed by a furnace process. Specifically, the furnace process uses thermal oxidation for chemical vapor deposition (CVD) to improve the electrical quality of the first oxide layer 301.

[0076] Preferably, the thickness of the second oxide layer 303 is equal to the thickness of the first oxide layer 301.

[0077] Finally, as Figure 9 shown, step 9) is carried out to secondarily fill the trench 101 with an insulator to form a second insulating layer 402.

[0078] Preferably, the second insulating layer 402 is formed by a high density plasma (HDP) oxide filling method.

[0079] Preferably, the material of the second insulating layer 402 is the same as the material of the first insulating layer 401.

[0080] Preferably, after the second HDP filling, steam annealing is first performed to eliminate the gaps in the second insulating layer 402; then nitrogen annealing is performed to make the second insulating layer 402 denser, so that the corrosion rate of the filled second insulating layer 402 is reduced to be close to that of the liner oxide layer 201, so as to reduce the loss of the filled insulating material during the surface cleaning process before growing the gate oxide layer due to the corrosion rate of the deposited insulator during the HDP filling process being higher than that of the liner oxide layer 201, and prevent the leakage at the edge of the STI structure from being aggravated. Specifically, the nitrogen annealing process is carried out at 900 °C.

[0081] As an example, after step 9) is completed, the second insulating layer 402 is etched back or chemically mechanically polished (CMP) so that the insulating layer only fills the trench 101, that is, the second insulating layer 402 flush with the bottom surface of the silicon nitride layer 202 in the trench 101 is obtained, and the silicon nitride layer 202 is exposed; then the silicon nitride layer 202 is removed, and devices are fabricated in each active region 102. Specifically, the silicon nitride layer 202 is etched using dry etching, in cooperation with the protection of the liner oxide layer 201, to minimize the damage to the substrate 100 caused by the etching.

[0082] As an example, the above preparation method is used to prepare devices such as CMOS, VDMOS, IGBT, etc. that adopt the shallow trench isolation process (STI). Embodiment 2

[0083] This embodiment provides a method for preparing a semiconductor device structure. The basic steps can refer to Embodiment 1. Among them, compared with Embodiment 1, the difference in this embodiment is that the halogen elements implanted include any combination of one or more of fluorine, chlorine, bromine, iodine, astatine, and tennessine. The co-implantation of mixed halogen elements is beneficial to adjusting the depth of the shallow junction formed by the implantation, reducing the diffusion of the implanted halogen elements beyond the expected position, so as to reduce the defect sites generated on the surface of the substrate 100 and improve the reliability of the fabricated devices.

[0084] In summary, the method for preparing a semiconductor device structure of the present invention can control the etching rate of the active region apex by implanting halogen elements into the active region apex, effectively control the rounding of the active region apex, thereby reducing the influence of parasitic devices caused by the uneven shape of the apex, and being beneficial to improving the device reliability.

[0085] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0086] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device structure, characterized in that, The preparation method includes the steps of: Providing a substrate, forming a mask pattern layer on the substrate, forming spaced-apart trenches in the substrate based on the mask pattern layer, and separating a plurality of active regions in the substrate through the trenches; Removing a part of the mask pattern layer to expose the apex angles of each of the active regions; Forming a first oxide layer on the surface of the trenches, the first oxide layer covering the exposed apex angles of each of the active regions and the surface of the trenches; Filling the trenches with an insulator for the first time to form a first insulating layer; Etching the first insulating layer and the first oxide layer in the trenches to expose the apex angles of each of the active regions; Ion-implanting a halogen element at the apex angles, removing the part of the halogen element implanted at the apex angles of each of the active regions by an etching process, and controlling the shape at the apex angles of each active region by controlling the distribution of the halogen element at the apex angles of each active region, and precisely controlling the rounding of the apex angles of each active region; Forming a second oxide layer at the apex angles of each of the active regions; Filling the trenches with an insulator for the second time to form a second insulating layer.

2. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that, The mask pattern layer includes a pad oxide layer, a silicon nitride layer, and an oxide layer. The pad oxide layer is located on the substrate, the silicon nitride layer is located on the pad oxide layer, and the oxide layer is located on the silicon nitride layer.

3. The method for preparing the semiconductor device structure according to claim 1, wherein, Removing a part of the mask pattern layer by wet etching with a hot phosphoric acid solution to expose the apex angles of each of the active regions.

4. The method for preparing a semiconductor device structure according to claim 1, wherein, Both the first insulating layer and the second insulating layer are formed by a high-density plasma oxide filling method.

5. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that, Etching the first insulating layer in the trenches by a wet etching method to expose the apex angles of each of the active regions.

6. The method for preparing a semiconductor device structure according to claim 1, wherein, Removing the part of the halogen element implanted at the apex angles of each of the active regions by a wet etching method.

7. The manufacturing method of the semiconductor device structure according to claim 1, characterized in that, Both the first oxide layer and the second oxide layer are formed by a furnace process.

8. The method for manufacturing the semiconductor device structure according to claim 1, wherein, The thickness of the second oxide layer is equal to the thickness of the first oxide layer.

9. The method for manufacturing a semiconductor device structure according to claim 1, wherein, The thickness of the first oxide layer is 100 angstroms.

10. The manufacturing method of the semiconductor device structure according to any one of claims 1-9, characterized in that, The halogen element includes one or any combination of fluorine, chlorine, bromine, iodine, astatine, and tennessine.

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