Display panel and electronic device

Abstract

Embodiments of the present application provide a display panel and a display device, by arranging a first data signal line and a second data signal line with relatively more wires in a third metal layer, and arranging a first connection line and a second connection line with relatively less wires in a fourth metal layer, the number of wires in the fourth metal layer is reduced, the area occupied by the wires in the fourth metal layer is reduced, and the risk of the pixel electrode above the fourth metal layer being tilted is reduced, and the uniformity of color display at different viewing angles of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display device manufacturing, and more specifically, to a display panel and an electronic device. Background Technology

[0002] Organic light-emitting diode (OLED) display devices typically consist of multiple stacked metal layers. Metal traces or structures in different metal layers are used to form signal lines with different functions or to form different transistor electrodes in the switching unit. Above the metal layers, pixel electrodes (e.g., anodes) are disposed to drive the light-emitting material. The pixel electrodes have a relatively large area and often cover the electrode lines in the metal layers, causing angular color shifts in the light-emitting pixels and degrading the overall display effect of the display panel. Summary of the Invention

[0003] To overcome at least one of the technical problems mentioned in the above-mentioned technical background, embodiments of this application provide a display panel, characterized in that the display panel includes:

[0004] substrate;

[0005] A first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a pixel electrode layer are stacked on one side of the substrate.

[0006] The third metal layer includes a first data signal line, a second data signal line, and a first power signal line extending along a first direction;

[0007] The fourth metal layer includes a first connecting line and a second connecting line, which extend along a second direction; the first direction is perpendicular to the second direction.

[0008] The pixel electrode layer includes at least one pixel electrode.

[0009] In one possible implementation, the fourth metal layer further includes a second power signal line extending along the first direction. The second power signal line includes an extension portion and a break portion. Two adjacent extension portions along the first direction are spaced apart by the break portion. The first connection line and the second connection line extend along the second direction through the break portion.

[0010] The extension of the second power signal line is electrically connected to the first power signal line through a through-hole in the insulating material between the third metal layer and the fourth metal layer.

[0011] In one possible implementation, the at least one pixel electrode includes at least one first electrode, wherein a first orthographic projection of the first electrode on the substrate does not coincide with a second orthographic projection of the extension portion of the second power signal line on the substrate; and the first orthographic projection of the first electrode on the substrate at least partially coincides with a third orthographic projection of the first connecting line and the second connecting line on the substrate.

[0012] Preferably, the axis of symmetry of the first orthographic projection along the second direction coincides with the axis of symmetry of the third orthographic projection along the second direction.

[0013] In one possible implementation, the at least one pixel electrode includes at least one second electrode, wherein the fourth orthographic projection of the second electrode on the substrate at least partially overlaps with the second orthographic projection of the extension portion of the second power signal line on the substrate, and the axis of symmetry of the fourth orthographic projection along the first direction coincides with the axis of symmetry of the second orthographic projection along the first direction.

[0014] In one possible implementation, the at least one pixel electrode includes at least one third electrode, wherein the sixth orthographic projection of the third electrode on the substrate does not coincide with the third orthographic projection of the first connecting line and the second connecting line on the substrate; the sixth orthographic projection of the third electrode on the substrate at least partially coincides with the fifth orthographic projection of the disconnected portion of the second power signal line on the substrate, and the axis of symmetry of the sixth orthographic projection along the first direction coincides with the axis of symmetry of the fifth orthographic projection along the first direction.

[0015] In one possible implementation, at least one side of the first power signal line is provided with a trace compensation portion, and the seventh orthographic projection of the trace compensation portion on the substrate is adjacent to the fifth orthographic projection of the disconnected portion of the second power signal line on the substrate.

[0016] In one possible implementation, the area of ​​the seventh orthographic projection is equal to the area of ​​the fifth orthographic projection.

[0017] In one possible implementation, the trace compensation portion includes a first portion and a second portion, the first portion and the second portion being located on both sides of the first power signal line, respectively.

[0018] In one possible implementation, the first connecting line and the second connecting line are power signal connecting lines; or the first connecting line and the second connecting line are a power signal connecting line and a data signal connecting line, respectively.

[0019] Another object of this application is to provide an electronic device, which includes the display panel provided in this application.

[0020] Compared with the prior art, this application has the following beneficial effects:

[0021] The display panel and electronic device provided in this application embodiment reduce the number of traces in the fourth metal layer by placing the first and second data signal lines with a relatively large number of traces in the third metal layer and the first and second connecting lines with a relatively small number of traces in the fourth metal layer. This reduces the area occupied by the traces in the fourth metal layer, thereby reducing the risk of the pixel electrodes located above the fourth metal layer tilting and improving the uniformity of color display on different viewing angles of the display panel. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a display panel after the fan-out area has been compressed.

[0024] Figure 2 This is a schematic diagram of a display panel data winding.

[0025] Figure 3 This is one of the schematic diagrams of the wiring of the third and fourth metal layers in the prior art;

[0026] Figure 4 This is the second schematic diagram of the wiring of the third and fourth metal layers in the prior art;

[0027] Figure 5 for Figure 4 A cross-sectional view of position AA shown;

[0028] Figure 6 This is a schematic diagram showing the tilt of the anode electrode;

[0029] Figure 7 This is a cross-sectional view of the display panel provided in this embodiment;

[0030] Figure 8 This is one of the wiring diagrams of the third and fourth metal layers provided in this embodiment;

[0031] Figure 9 This is the second schematic diagram of the wiring of the third and fourth metal layers provided in this embodiment;

[0032] Figure 10This is the third schematic diagram of the wiring of the third and fourth metal layers provided in this embodiment;

[0033] Figure 11 for Figure 10 A cross-sectional view showing the location of BB;

[0034] Figure 12 for Figure 10 A cross-sectional view at the CC position shown;

[0035] Figure 13 This is the fourth schematic diagram of the routing of the third and fourth metal layers provided in this embodiment;

[0036] Figure 14 for Figure 13 A cross-sectional view of the location DD shown;

[0037] Figure 15 The fifth schematic diagram of the routing of the third and fourth metal layers provided in this embodiment. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0040] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0041] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0043] Typically, the vertical data signal traces in the display panel need to be connected one by one to the fan-out traces 401 in the fan-out area at the edge of the display panel, thereby electrically connecting to the driver chip through the fan-out traces 401. Please refer to... Figure 1 In some display panels, the fan-out area is compressed to reduce the bezel width, reducing the original length D1 to a length D2. However, due to limitations in trace width and density, the fan-out lines can hardly have a large slope, so the width of the fan-out area is also shortened from W1 to W2.

[0044] However, after compressing the fan-out area, some of the first data signal lines 211 in the display panel cannot be directly connected to the fan-out area. For example, please refer to... Figure 2 ,exist Figure 2 In the illustrated display panel, the first data signal line 211 in region Z1 can be directly connected to the fan-out trace 401 in the fan-out region at the edge of the display panel. However, the first data signal line 211 in region Z2 cannot be directly connected to the fan-out trace 401 in the fan-out region at the edge of the display panel. Therefore, in this type of display panel, a second data signal line 212 is added as a data signal winding on the basis of the original first data signal line 211. The second data signal line 212 in region Z1 can be directly connected to the fan-out trace 401 in the fan-out region at the edge of the display panel, and then connected to the first data signal line 211 in region Z2 through the horizontal first connecting line 221, thereby realizing the electrical connection between the first data signal line 211 in region Z2 and the driver chip.

[0045] The aforementioned traces may be located in different metal layers within the display panel. For example, a display panel typically includes multiple metal layers, with different metal layers used to form different signal traces or different electrodes of semiconductor devices. The multiple metal layers may include a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, sequentially stacked from the direction closest to the substrate 110 to the direction furthest from the substrate 110. Please refer to... Figure 3 , Figure 3 for Figure 2The diagram shows a partial top-view perspective view of a display panel. In this type of display panel, a horizontally extending first connecting line 221 is typically located in the third metal layer M3. Additionally, the third metal layer M3 also contains a horizontally extending second connecting line 222 and a vertically extending first power signal line 230. The second connecting line 222 can serve as a power signal trace, used to connect at least two power signal (Vdd) traces. A vertically extending first data signal line 211 and a second data signal line 212 are typically located in the fourth metal layer M4. Furthermore, the fourth metal layer M4 also contains a vertically extending second power signal line 240. The first power signal line 230 in the third metal layer M3 and the second power signal line 240 in the fourth metal layer M4 overlap and extend parallel to each other. Figure 3 The first metal layer M1, not shown, typically includes laterally extending scan signal traces; Figure 3 The second metal layer M2, not shown, typically includes laterally extending reference signal (REF) traces and control signal (EM) traces.

[0046] Please refer to Figure 4 ,exist Figure 3 Based on the wiring layout shown, a pixel electrode layer is also provided above the fourth metal layer M4. The pixel electrode layer typically includes the anode electrode 301 of each light-emitting pixel. Please refer to... Figure 5 , Figure 5 for Figure 4 The sectional view shown in direction AA, from Figure 4 and Figure 5 As can be seen, the anode electrode 301 covers the second power signal line 240 and the first data signal line 211 in the fourth metal layer M4, and the second power signal line 240 and the first data signal line 211 are asymmetrically distributed below the anode electrode 301.

[0047] In the multiple metal layers of a display panel, the first metal layer M1 and the second metal layer M2 are typically covered by an interlayer dielectric with high flatness. Therefore, the first metal layer M1 and the second metal layer M2 have little impact on the flatness beneath the pixel electrode layer. Please refer to... Figure 6 Between the third metal layer M3 and the pixel electrode layer, there are a first planarization layer 150 and a second planarization layer 160. The overall thickness of the two planarization layers is relatively thick, so the third metal layer M3 has little impact on the flatness below the pixel electrode layer. However, between the fourth metal layer M4 and the pixel electrode layer, there is only a second planarization layer 160. The single second planarization layer 160 is relatively thin, so the fourth metal layer M4 has a relatively greater impact on the flatness below the pixel electrode layer. For example, in... Figure 6In the partial cross-sectional view of the display panel shown, if there are traces in the fourth metal layer M4 below the anode electrode 301, the height H1 at that location will be greater than the height H2 at a location in the fourth metal layer M4 without traces. That is, the traces in the fourth metal layer M4 may raise the anode electrode 301, potentially causing the anode electrode 301 to tilt, which in turn may cause the light-emitting pixels formed based on the anode electrode 301 to tilt. Please refer again... Figure 3 In the existing wiring layout scheme, the number of vertical wirings in the fourth metal layer M4 is relatively large and dense, which makes the anode electrode 301 more likely to tilt, which can easily cause viewing angle deviation and affect the display effect of the entire display panel.

[0048] In view of this, this embodiment provides a solution that improves the symmetry of signal traces in the fourth metal layer M4, thereby reducing the risk of pixel electrodes located on the fourth metal layer M4 becoming tilted. The solution provided in this embodiment will be described in detail below.

[0049] This embodiment provides a display panel, which includes a substrate 110 and a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a pixel electrode layer stacked on one side of the substrate 110.

[0050] Specifically, please refer to Figure 7 The substrate 110 and the plurality of metal layers may also include a plurality of other film layers 120, such as buffer layers, semiconductor layers, first gate insulating layers, etc.

[0051] From the direction near the substrate 110 to the direction away from the substrate 110, the plurality of metal layers may include a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 stacked together, with adjacent metal layers isolated from each other by an insulating material. For example, a second gate insulating layer 130 is included between the first metal layer M1 and the second metal layer M2, an interlayer dielectric layer 140 is included between the second metal layer M2 and the third metal layer M3, and a first planarization layer 150 is included between the third metal layer M3 and the fourth metal layer M4. A second planarization layer 160 is also provided on the side of the fourth metal layer M4 away from the first planarization layer. The pixel electrode layer is provided on the side of the second planarization layer away from the fourth metal layer M4, and the pixel electrode layer includes at least one pixel electrode 301, which may be the anode electrode of a light-emitting pixel.

[0052] Please refer to Figure 8 , Figure 8 This is a top perspective view of the third metal layer M3 and the fourth metal layer M4 in the display panel provided in this embodiment. Figure 8As shown, in this embodiment, the third metal layer M3 may include a first data signal line 211, a second data signal line 212, and a first power signal line 230 extending along a first direction. One of the first data signal line 211 and the second data signal line 212 can be the main data signal trace, and the other can be a data signal loop added in a compressed fan-out area scheme. It should be noted that since the traces in the first metal layer M1 and the second metal layer M2 have little impact on the balance of the pixel electrode 301, the arrangement of the traces in the first metal layer M1 and the second metal layer M2 is not specifically limited in this embodiment.

[0053] The fourth metal layer M4 includes a first connecting line 221 and a second connecting line 222, which extend along a second direction. The first direction is perpendicular to the second direction.

[0054] Wherein, the first direction can be Figure 8 As shown in the longitudinal direction, the second direction can be Figure 8 The horizontal direction is shown.

[0055] Please compare and refer to the above. Figure 3 The existing wiring layout method and Figure 8 The wiring layout in the display panel provided in this embodiment, compared to the prior art, involves placing the first data signal lines 211 and 212, which originally had a relatively large number of wirings in the fourth metal layer M4, along the first direction, in the third metal layer M3. Conversely, the first connecting lines 221 and 222, which originally had a relatively small number of wirings in the third metal layer M3, along the second direction, are also placed in the third metal layer M3. This reduces the number of wirings in the fourth metal layer M4, lowers the area occupied by the wirings in the fourth metal layer M4, and consequently reduces the risk of pixel electrodes tilting on the fourth metal layer M4, improving the uniformity of color display across different viewing angles of the display panel.

[0056] In one possible implementation, please refer to Figure 9 The fourth metal layer M4 further includes a second power signal line 240, which extends along the first direction. The second power signal line 240 includes an extension portion and a break portion. Two adjacent extension portions along the first direction are spaced apart by the break portion. The first connecting line 221 and the second connecting line 222 extend along the second direction through the break portion. Thus, the break portion is provided on the second power signal line 240 so that the first connecting line 221 and the second connecting line 222, also located in the fourth metal layer M4, do not overlap with the second power signal line 240.

[0057] In this embodiment, the orthographic projection of the extended portion of the second power signal line 240 in the fourth metal layer M4 onto the third metal layer M3 coincides with the first power signal line 230. Both the first power signal line 230 and the second power signal line 240 are used to transmit the power signal Vdd.

[0058] Please refer to Figure 11 The extension portion of the second power signal line 240 can be electrically connected to the first power signal line 230 through a through-hole 250 penetrating the insulating material between the third metal layer M3 and the fourth metal layer M4. The insulating material between the third metal layer M3 and the fourth metal layer M4 may include the first planarization layer 150. Thus, each of the extension portions of the second power signal line 240 that are cut off by the disconnected portion can be electrically connected as a whole through the first power signal line 230.

[0059] In one possible implementation, please refer to Figure 10 The at least one pixel electrode 301 in the pixel electrode layer includes at least one first electrode 310. The first orthographic projection of the first electrode 310 on the substrate 110 does not coincide with the second orthographic projection of the extension portion of the second power signal line 240 on the substrate 110. The first orthographic projection of the first electrode 310 on the substrate 110 at least partially coincides with the third orthographic projections of the first connecting line 221 and the second connecting line 222 on the substrate 110.

[0060] Optionally, please refer to again Figure 10 In some examples, the first orthographic projection of the first electrode 310 on the substrate 110 along the axis of symmetry of the second direction coincides with the axis of symmetry of the third orthographic projection along the second direction, such as... Figure 10 The first electrode 310A is shown. In other examples, the first orthographic projection of the first electrode 310 onto the substrate 110 may not coincide with the third orthographic projection along the axis of symmetry in the second direction, such as... Figure 10 The first electrode 310B is shown.

[0061] For example, please refer to Figure 11 , Figure 11 for Figure 10 The sectional view of BB position shown is as follows: Figure 11As shown in this embodiment, the first orthographic projection of the first electrode 310 on the substrate 110 does not coincide with the second orthographic projection of the extended portion of the second power signal line 240 on the substrate 110. That is, the positions of the first electrode 310 and the disconnected portion of the second power signal line 240 correspond. Therefore, in the first direction, the second power signal line 240 in the fourth metal layer M4 will not cause the first electrode 310 to tilt. Furthermore, the first orthographic projection of the first electrode 310 along the axis of symmetry in the second direction coincides with the third orthographic projection of the first connecting line 221 and the second connecting line 222 along the axis of symmetry in the second direction. The first connecting line 221 and the second connecting line 222 are symmetrically distributed below the first electrode 310. Therefore, in the second direction, the first connecting line 221 and the second connecting line 222 in the fourth metal layer M4 will also not cause the first electrode 310 to tilt.

[0062] In one possible implementation, please refer again. Figure 10 The at least one pixel electrode 301 in the pixel electrode layer includes at least one second electrode 320, wherein the fourth orthographic projection of the second electrode 320 on the substrate 110 at least partially overlaps with the second orthographic projection of the extension portion of the second power signal line 240 on the substrate 110, and the fourth orthographic projection along the axis of symmetry of the first direction coincides with the second orthographic projection along the axis of symmetry of the first direction.

[0063] For example, please refer to Figure 12 , Figure 12 for Figure 10 The sectional view at position CC is shown below. Figure 12 As shown, in this embodiment, the second electrode 320's axis of symmetry along the first direction coincides with the extended portion of the second power signal line 240's axis of symmetry along the first direction, and the orthographic projection of the second electrode 320 on the substrate 110 does not coincide with the third orthographic projections of the first connecting line 221 and the second connecting line 222 on the substrate 110. That is, the first connecting line 221 and the second connecting line 222 in the fourth metal layer M4 do not pass below the second electrode 320, therefore, in the second direction, the first connecting line 221 and the second connecting line 222 in the fourth metal layer M4 will not cause the second electrode 320 to tilt. Furthermore, the second electrode 320 is symmetrically distributed above the second power line of the fourth metal layer M4, therefore, in the first direction, the second power signal line 240 in the fourth metal layer M4 will not cause the first electrode 310 to tilt.

[0064] In one possible implementation, please refer to Figure 13The at least one pixel electrode 301 in the pixel electrode layer includes at least one third electrode 330. The sixth orthographic projection of the third electrode 330 on the substrate 110 does not coincide with the third orthographic projections of the first connecting line 221 and the second connecting line 222 on the substrate 110. The sixth orthographic projection of the third electrode 330 on the substrate 110 at least partially coincides with the fifth orthographic projection of the disconnected portion of the second power signal line 240 on the substrate 110, and the axis of symmetry of the sixth orthographic projection along the first direction coincides with the axis of symmetry of the fifth orthographic projection along the first direction.

[0065] For example, please refer to Figure 14 , Figure 14 for Figure 13 The sectional view at position DD is shown below. Figure 14 As shown, in this embodiment, the axis of symmetry of the third electrode 330 along the first direction coincides with the axis of symmetry of the disconnected portion of the second power signal line 240 along the first direction. Furthermore, the first connecting line 221 and the second connecting line 222 in the fourth metal layer M4 do not pass below the third electrode 330. Therefore, in the second direction, the first connecting line 221 and the second connecting line 222 in the fourth metal layer M4 will not cause the second electrode 320 to tilt. Also, the third electrode 330 corresponds to the position of the disconnected portion of the second power signal line 240; therefore, in the first direction, the second power signal line 240 in the fourth metal layer M4 will not cause the third electrode 330 to tilt.

[0066] In one example Figure 10 and Figure 13 The first electrode 310 shown can be the anode electrode of the green sub-pixel, the second electrode 320 can be the anode electrode of the blue sub-pixel, and the third electrode 330 can be the anode electrode of the red sub-pixel.

[0067] However, it should be noted that in this embodiment... Figure 10 and Figure 13The distribution and number of the first electrode 310, second electrode 320, and third electrode 330 shown are merely one example provided in this embodiment, and are only used to illustrate that the pixel electrode 301 can be balanced by setting it in different positions. In other implementations not shown in this embodiment, the number of the first electrode 301, second electrode 302, and third electrode 330 can be flexibly set. For example, in some implementations, the pixel electrode 301 may include only the first electrode 310, only the second electrode 320, or only the third electrode 330. The balanced positions of each pixel electrode shown in this embodiment form the four corners of a rectangle or the three corners of a triangle, and different pixel electrodes 301 correspond to different colored light-emitting sub-pixels.

[0068] In one possible implementation, please refer to Figure 15 A trace compensation portion 231 is provided on at least one side of the first power signal line 230. The seventh orthographic projection of the trace compensation portion 231 on the substrate 110 is adjacent to the fifth orthographic projection of the disconnected portion of the second power signal line 240 on the substrate 110. Optionally, the trace compensation portion 231 includes a first part and a second part, which are located on both sides of the first power signal line 230, respectively.

[0069] In this embodiment, the second power signal line 240 has a disconnected portion, which reduces the overall conductive area of ​​the first power signal line 230 and the second power signal line 240 at the disconnected portion and increases the resistance. Therefore, the trace compensation part 231 can compensate for the missing trace area on the second power signal line 240 at the disconnected portion, thereby balancing the overall conductive area of ​​the first power signal line 230 and the second power signal line 240 and maintaining the uniformity of the overall resistance of the first power signal line 230 and the second power signal line 240.

[0070] Furthermore, in this embodiment, the area of ​​the seventh orthographic projection is equal to the area of ​​the fifth orthographic projection. That is, the area of ​​the trace compensation portion 231 on the first power signal line 230 is equal to the area of ​​the disconnected portion of the second power signal line 240, which can keep the overall resistance of the first power signal line 230 and the second power signal line 240 as uniform as possible.

[0071] Optionally, in one example, the first connecting line 221 and the second connecting line 222 are power signal connecting lines. For example, for areas where it is not necessary to connect the main data signal line and the data signal winding line via a data signal serial line, the first connecting line 221 and the second connecting line 222 can both be Vdd power signal connecting lines, used to connect two Vdd power signal lines, thereby reducing the voltage drop (IR drop) at various points on the Vdd power signal lines. In another example, the first connecting line 221 and the second connecting line 222 are power signal connecting lines and data signal connecting lines, respectively. For example, for areas where it is necessary to connect the main data signal line and the data signal winding line via a data signal serial line, the first connecting line 221 and the second connecting line 222 are power signal connecting lines and data signal connecting lines, respectively. The data signal connecting line can be used to connect the data signal serial line that is directly connected to the fan-out signal trace to the main data signal line that cannot be directly connected to the fan-out signal trace. The power signal connecting line is used to connect two Vdd power signal lines, thereby reducing the voltage drop (IR drop) at various points on the power signal lines.

[0072] This application also provides an electronic device, which includes the display panel provided in this application.

[0073] In summary, the display panel and electronic device provided in this application improve the symmetry of the data signal traces in the fourth metal layer by placing the first and second data signal lines extending along the first direction in the original fourth metal layer in the third metal layer, placing the first and second connecting lines extending along the second direction in the original third metal layer in the third metal layer, and providing a break in the second power signal line so that the first and second connecting lines do not overlap with the second power signal line. This improves the uniformity of color display on the display panel from different viewing angles.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: substrate; A first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a pixel electrode layer are stacked on one side of the substrate. The third metal layer includes a first data signal line, a second data signal line, and a first power signal line extending along a first direction; The fourth metal layer includes a first connecting line and a second connecting line, which extend along a second direction; the first direction is perpendicular to the second direction. The pixel electrode layer includes at least one pixel electrode; The fourth metal layer further includes a second power signal line extending along the first direction. The second power signal line includes an extension portion and a break portion. Two adjacent extension portions along the first direction are spaced apart by the break portion. The first connecting line and the second connecting line extend along the second direction through the break portion. The extension of the second power signal line is electrically connected to the first power signal line through a through-hole in the insulating material between the third metal layer and the fourth metal layer.

2. The display panel according to claim 1, characterized in that, The at least one pixel electrode includes at least one first electrode, wherein the first orthographic projection of the first electrode on the substrate does not coincide with the second orthographic projection of the extension portion of the second power signal line on the substrate; and the first orthographic projection of the first electrode on the substrate at least partially coincides with the third orthographic projections of the first connecting line and the second connecting line on the substrate.

3. The display panel according to claim 2, characterized in that, The axis of symmetry of the first orthographic projection along the second direction coincides with the axis of symmetry of the third orthographic projection along the second direction.

4. The display panel according to claim 1, characterized in that, The at least one pixel electrode includes at least one second electrode, wherein the fourth orthographic projection of the second electrode on the substrate and the second orthographic projection of the extension portion of the second power signal line on the substrate at least partially overlap, and the axis of symmetry of the fourth orthographic projection along the first direction coincides with the axis of symmetry of the second orthographic projection along the first direction.

5. The display panel according to claim 1, characterized in that, The at least one pixel electrode includes at least one third electrode, and the sixth orthographic projection of the third electrode on the substrate does not coincide with the third orthographic projection of the first connecting line and the second connecting line on the substrate. The sixth orthographic projection of the third electrode on the substrate at least partially coincides with the fifth orthographic projection of the disconnected portion of the second power signal line on the substrate, and the axis of symmetry of the sixth orthographic projection along the first direction coincides with the axis of symmetry of the fifth orthographic projection along the first direction.

6. The display panel according to claim 1, characterized in that, At least one side of the first power signal line is provided with a trace compensation part, and the seventh orthographic projection of the trace compensation part on the substrate is adjacent to the fifth orthographic projection of the disconnected portion of the second power signal line on the substrate.

7. The display panel according to claim 6, characterized in that, The area of ​​the seventh orthographic projection is equal to the area of ​​the fifth orthographic projection.

8. The display panel according to claim 6, characterized in that, The routing compensation section includes a first part and a second part, which are located on both sides of the first power signal line, respectively.

9. The display panel according to claim 1, characterized in that, The first connecting line and the second connecting line are power signal connecting lines; or the first connecting line and the second connecting line are power signal connecting line and data signal connecting line, respectively.

10. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-9.

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